1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author:
5 * Zhigang.Wei <zhigang.wei@mediatek.com>
6 * Chunfeng.Yun <chunfeng.yun@mediatek.com>
7 */
8
9 #ifndef _XHCI_MTK_H_
10 #define _XHCI_MTK_H_
11
12 #include "xhci.h"
13
14 /**
15 * To simplify scheduler algorithm, set a upper limit for ESIT,
16 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
17 * round down to the limit value, that means allocating more
18 * bandwidth to it.
19 */
20 #define XHCI_MTK_MAX_ESIT 64
21
22 /**
23 * @fs_bus_bw: array to keep track of bandwidth already used for FS
24 * @ep_list: Endpoints using this TT
25 */
26 struct mu3h_sch_tt {
27 u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
28 struct list_head ep_list;
29 };
30
31 /**
32 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
33 *
34 * @bus_bw: array to keep track of bandwidth already used at each uframes
35 * @bw_ep_list: eps in the bandwidth domain
36 *
37 * treat a HS root port as a bandwidth domain, but treat a SS root port as
38 * two bandwidth domains, one for IN eps and another for OUT eps.
39 */
40 struct mu3h_sch_bw_info {
41 u32 bus_bw[XHCI_MTK_MAX_ESIT];
42 struct list_head bw_ep_list;
43 };
44
45 /**
46 * struct mu3h_sch_ep_info: schedule information for endpoint
47 *
48 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
49 * @num_budget_microframes: number of continuous uframes
50 * (@repeat==1) scheduled within the interval
51 * @bw_cost_per_microframe: bandwidth cost per microframe
52 * @endpoint: linked into bandwidth domain which it belongs to
53 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
54 * @sch_tt: mu3h_sch_tt linked into
55 * @ep_type: endpoint type
56 * @maxpkt: max packet size of endpoint
57 * @ep: address of usb_host_endpoint struct
58 * @allocated: the bandwidth is aready allocated from bus_bw
59 * @offset: which uframe of the interval that transfer should be
60 * scheduled first time within the interval
61 * @repeat: the time gap between two uframes that transfers are
62 * scheduled within a interval. in the simple algorithm, only
63 * assign 0 or 1 to it; 0 means using only one uframe in a
64 * interval, and 1 means using @num_budget_microframes
65 * continuous uframes
66 * @pkts: number of packets to be transferred in the scheduled uframes
67 * @cs_count: number of CS that host will trigger
68 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
69 * distribute the bMaxBurst+1 packets for a single burst
70 * according to @pkts and @repeat, repeate the burst multiple
71 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
72 * according to @pkts and @repeat. normal mode is used by
73 * default
74 * @bw_budget_table: table to record bandwidth budget per microframe
75 */
76 struct mu3h_sch_ep_info {
77 u32 esit;
78 u32 num_budget_microframes;
79 u32 bw_cost_per_microframe;
80 struct list_head endpoint;
81 struct list_head tt_endpoint;
82 struct mu3h_sch_tt *sch_tt;
83 u32 ep_type;
84 u32 maxpkt;
85 struct usb_host_endpoint *ep;
86 enum usb_device_speed speed;
87 bool allocated;
88 /*
89 * mtk xHCI scheduling information put into reserved DWs
90 * in ep context
91 */
92 u32 offset;
93 u32 repeat;
94 u32 pkts;
95 u32 cs_count;
96 u32 burst_mode;
97 u32 bw_budget_table[];
98 };
99
100 #define MU3C_U3_PORT_MAX 4
101 #define MU3C_U2_PORT_MAX 5
102
103 /**
104 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
105 * @ip_pw_ctr0~3: ip power and clock control registers
106 * @ip_pw_sts1~2: ip power and clock status registers
107 * @ip_xhci_cap: ip xHCI capability register
108 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
109 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
110 * @u2_phy_pll: usb2 phy pll control register
111 */
112 struct mu3c_ippc_regs {
113 __le32 ip_pw_ctr0;
114 __le32 ip_pw_ctr1;
115 __le32 ip_pw_ctr2;
116 __le32 ip_pw_ctr3;
117 __le32 ip_pw_sts1;
118 __le32 ip_pw_sts2;
119 __le32 reserved0[3];
120 __le32 ip_xhci_cap;
121 __le32 reserved1[2];
122 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
123 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
124 __le32 reserved2;
125 __le32 u2_phy_pll;
126 __le32 reserved3[33]; /* 0x80 ~ 0xff */
127 };
128
129 struct xhci_hcd_mtk {
130 struct device *dev;
131 struct usb_hcd *hcd;
132 struct mu3h_sch_bw_info *sch_array;
133 struct list_head bw_ep_chk_list;
134 struct mu3c_ippc_regs __iomem *ippc_regs;
135 bool has_ippc;
136 int num_u2_ports;
137 int num_u3_ports;
138 int u3p_dis_msk;
139 struct regulator *vusb33;
140 struct regulator *vbus;
141 struct clk *sys_clk; /* sys and mac clock */
142 struct clk *xhci_clk;
143 struct clk *ref_clk;
144 struct clk *mcu_clk;
145 struct clk *dma_clk;
146 struct regmap *pericfg;
147 struct phy **phys;
148 int num_phys;
149 bool lpm_support;
150 bool u2_lpm_disable;
151 /* usb remote wakeup */
152 bool uwk_en;
153 struct regmap *uwk;
154 u32 uwk_reg_base;
155 u32 uwk_vers;
156 };
157
hcd_to_mtk(struct usb_hcd * hcd)158 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
159 {
160 return dev_get_drvdata(hcd->self.controller);
161 }
162
163 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
164 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
165 int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
166 struct usb_host_endpoint *ep);
167 int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
168 struct usb_host_endpoint *ep);
169 int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
170 void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
171
172 #endif /* _XHCI_MTK_H_ */
173