1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35 #define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
36
37 struct clk;
38 struct clk_hw;
39 struct clk_core;
40 struct dentry;
41
42 /**
43 * struct clk_rate_request - Structure encoding the clk constraints that
44 * a clock user might require.
45 *
46 * @rate: Requested clock rate. This field will be adjusted by
47 * clock drivers according to hardware capabilities.
48 * @min_rate: Minimum rate imposed by clk users.
49 * @max_rate: Maximum rate imposed by clk users.
50 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
51 * requested constraints.
52 * @best_parent_hw: The most appropriate parent clock that fulfills the
53 * requested constraints.
54 *
55 */
56 struct clk_rate_request {
57 unsigned long rate;
58 unsigned long min_rate;
59 unsigned long max_rate;
60 unsigned long best_parent_rate;
61 struct clk_hw *best_parent_hw;
62 };
63
64 /**
65 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
66 *
67 * @num: Numerator of the duty cycle ratio
68 * @den: Denominator of the duty cycle ratio
69 */
70 struct clk_duty {
71 unsigned int num;
72 unsigned int den;
73 };
74
75 /**
76 * struct clk_ops - Callback operations for hardware clocks; these are to
77 * be provided by the clock implementation, and will be called by drivers
78 * through the clk_* api.
79 *
80 * @prepare: Prepare the clock for enabling. This must not return until
81 * the clock is fully prepared, and it's safe to call clk_enable.
82 * This callback is intended to allow clock implementations to
83 * do any initialisation that may sleep. Called with
84 * prepare_lock held.
85 *
86 * @unprepare: Release the clock from its prepared state. This will typically
87 * undo any work done in the @prepare callback. Called with
88 * prepare_lock held.
89 *
90 * @is_prepared: Queries the hardware to determine if the clock is prepared.
91 * This function is allowed to sleep. Optional, if this op is not
92 * set then the prepare count will be used.
93 *
94 * @unprepare_unused: Unprepare the clock atomically. Only called from
95 * clk_disable_unused for prepare clocks with special needs.
96 * Called with prepare mutex held. This function may sleep.
97 *
98 * @enable: Enable the clock atomically. This must not return until the
99 * clock is generating a valid clock signal, usable by consumer
100 * devices. Called with enable_lock held. This function must not
101 * sleep.
102 *
103 * @disable: Disable the clock atomically. Called with enable_lock held.
104 * This function must not sleep.
105 *
106 * @is_enabled: Queries the hardware to determine if the clock is enabled.
107 * This function must not sleep. Optional, if this op is not
108 * set then the enable count will be used.
109 *
110 * @disable_unused: Disable the clock atomically. Only called from
111 * clk_disable_unused for gate clocks with special needs.
112 * Called with enable_lock held. This function must not
113 * sleep.
114 *
115 * @save_context: Save the context of the clock in prepration for poweroff.
116 *
117 * @restore_context: Restore the context of the clock after a restoration
118 * of power.
119 *
120 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
121 * parent rate is an input parameter. It is up to the caller to
122 * ensure that the prepare_mutex is held across this call.
123 * Returns the calculated rate. Optional, but recommended - if
124 * this op is not set then clock rate will be initialized to 0.
125 *
126 * @round_rate: Given a target rate as input, returns the closest rate actually
127 * supported by the clock. The parent rate is an input/output
128 * parameter.
129 *
130 * @determine_rate: Given a target rate as input, returns the closest rate
131 * actually supported by the clock, and optionally the parent clock
132 * that should be used to provide the clock rate.
133 *
134 * @set_parent: Change the input source of this clock; for clocks with multiple
135 * possible parents specify a new parent by passing in the index
136 * as a u8 corresponding to the parent in either the .parent_names
137 * or .parents arrays. This function in affect translates an
138 * array index into the value programmed into the hardware.
139 * Returns 0 on success, -EERROR otherwise.
140 *
141 * @get_parent: Queries the hardware to determine the parent of a clock. The
142 * return value is a u8 which specifies the index corresponding to
143 * the parent clock. This index can be applied to either the
144 * .parent_names or .parents arrays. In short, this function
145 * translates the parent value read from hardware into an array
146 * index. Currently only called when the clock is initialized by
147 * __clk_init. This callback is mandatory for clocks with
148 * multiple parents. It is optional (and unnecessary) for clocks
149 * with 0 or 1 parents.
150 *
151 * @set_rate: Change the rate of this clock. The requested rate is specified
152 * by the second argument, which should typically be the return
153 * of .round_rate call. The third argument gives the parent rate
154 * which is likely helpful for most .set_rate implementation.
155 * Returns 0 on success, -EERROR otherwise.
156 *
157 * @set_rate_and_parent: Change the rate and the parent of this clock. The
158 * requested rate is specified by the second argument, which
159 * should typically be the return of .round_rate call. The
160 * third argument gives the parent rate which is likely helpful
161 * for most .set_rate_and_parent implementation. The fourth
162 * argument gives the parent index. This callback is optional (and
163 * unnecessary) for clocks with 0 or 1 parents as well as
164 * for clocks that can tolerate switching the rate and the parent
165 * separately via calls to .set_parent and .set_rate.
166 * Returns 0 on success, -EERROR otherwise.
167 *
168 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
169 * is expressed in ppb (parts per billion). The parent accuracy is
170 * an input parameter.
171 * Returns the calculated accuracy. Optional - if this op is not
172 * set then clock accuracy will be initialized to parent accuracy
173 * or 0 (perfect clock) if clock has no parent.
174 *
175 * @get_phase: Queries the hardware to get the current phase of a clock.
176 * Returned values are 0-359 degrees on success, negative
177 * error codes on failure.
178 *
179 * @set_phase: Shift the phase this clock signal in degrees specified
180 * by the second argument. Valid values for degrees are
181 * 0-359. Return 0 on success, otherwise -EERROR.
182 *
183 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
184 * of a clock. Returned values denominator cannot be 0 and must be
185 * superior or equal to the numerator.
186 *
187 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
188 * the numerator (2nd argurment) and denominator (3rd argument).
189 * Argument must be a valid ratio (denominator > 0
190 * and >= numerator) Return 0 on success, otherwise -EERROR.
191 *
192 * @init: Perform platform-specific initialization magic.
193 * This is not used by any of the basic clock types.
194 * This callback exist for HW which needs to perform some
195 * initialisation magic for CCF to get an accurate view of the
196 * clock. It may also be used dynamic resource allocation is
197 * required. It shall not used to deal with clock parameters,
198 * such as rate or parents.
199 * Returns 0 on success, -EERROR otherwise.
200 *
201 * @terminate: Free any resource allocated by init.
202 *
203 * @debug_init: Set up type-specific debugfs entries for this clock. This
204 * is called once, after the debugfs directory entry for this
205 * clock has been created. The dentry pointer representing that
206 * directory is provided as an argument. Called with
207 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
208 *
209 * @pre_rate_change: Optional callback for a clock to fulfill its rate
210 * change requirements before any rate change has occurred in
211 * its clock tree. Returns 0 on success, -EERROR otherwise.
212 *
213 * @post_rate_change: Optional callback for a clock to clean up any
214 * requirements that were needed while the clock and its tree
215 * was changing states. Returns 0 on success, -EERROR otherwise.
216 *
217 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
218 * implementations to split any work between atomic (enable) and sleepable
219 * (prepare) contexts. If enabling a clock requires code that might sleep,
220 * this must be done in clk_prepare. Clock enable code that will never be
221 * called in a sleepable context may be implemented in clk_enable.
222 *
223 * Typically, drivers will call clk_prepare when a clock may be needed later
224 * (eg. when a device is opened), and clk_enable when the clock is actually
225 * required (eg. from an interrupt). Note that clk_prepare MUST have been
226 * called before clk_enable.
227 */
228 struct clk_ops {
229 int (*prepare)(struct clk_hw *hw);
230 void (*unprepare)(struct clk_hw *hw);
231 int (*is_prepared)(struct clk_hw *hw);
232 void (*unprepare_unused)(struct clk_hw *hw);
233 int (*enable)(struct clk_hw *hw);
234 void (*disable)(struct clk_hw *hw);
235 int (*is_enabled)(struct clk_hw *hw);
236 void (*disable_unused)(struct clk_hw *hw);
237 int (*save_context)(struct clk_hw *hw);
238 void (*restore_context)(struct clk_hw *hw);
239 unsigned long (*recalc_rate)(struct clk_hw *hw,
240 unsigned long parent_rate);
241 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
242 unsigned long *parent_rate);
243 int (*determine_rate)(struct clk_hw *hw,
244 struct clk_rate_request *req);
245 int (*set_parent)(struct clk_hw *hw, u8 index);
246 u8 (*get_parent)(struct clk_hw *hw);
247 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
248 unsigned long parent_rate);
249 int (*set_rate_and_parent)(struct clk_hw *hw,
250 unsigned long rate,
251 unsigned long parent_rate, u8 index);
252 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
253 unsigned long parent_accuracy);
254 int (*get_phase)(struct clk_hw *hw);
255 int (*set_phase)(struct clk_hw *hw, int degrees);
256 int (*get_duty_cycle)(struct clk_hw *hw,
257 struct clk_duty *duty);
258 int (*set_duty_cycle)(struct clk_hw *hw,
259 struct clk_duty *duty);
260 int (*init)(struct clk_hw *hw);
261 void (*terminate)(struct clk_hw *hw);
262 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
263 int (*pre_rate_change)(struct clk_hw *hw,
264 unsigned long rate,
265 unsigned long new_rate);
266 int (*post_rate_change)(struct clk_hw *hw,
267 unsigned long old_rate,
268 unsigned long rate);
269 };
270
271 /**
272 * struct clk_parent_data - clk parent information
273 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
274 * @fw_name: parent name local to provider registering clk
275 * @name: globally unique parent name (used as a fallback)
276 * @index: parent index local to provider registering clk (if @fw_name absent)
277 */
278 struct clk_parent_data {
279 const struct clk_hw *hw;
280 const char *fw_name;
281 const char *name;
282 int index;
283 };
284
285 /**
286 * struct clk_init_data - holds init data that's common to all clocks and is
287 * shared between the clock provider and the common clock framework.
288 *
289 * @name: clock name
290 * @ops: operations this clock supports
291 * @parent_names: array of string names for all possible parents
292 * @parent_data: array of parent data for all possible parents (when some
293 * parents are external to the clk controller)
294 * @parent_hws: array of pointers to all possible parents (when all parents
295 * are internal to the clk controller)
296 * @num_parents: number of possible parents
297 * @flags: framework-level hints and quirks
298 */
299 struct clk_init_data {
300 const char *name;
301 const struct clk_ops *ops;
302 /* Only one of the following three should be assigned */
303 const char * const *parent_names;
304 const struct clk_parent_data *parent_data;
305 const struct clk_hw **parent_hws;
306 u8 num_parents;
307 unsigned long flags;
308 };
309
310 /**
311 * struct clk_hw - handle for traversing from a struct clk to its corresponding
312 * hardware-specific structure. struct clk_hw should be declared within struct
313 * clk_foo and then referenced by the struct clk instance that uses struct
314 * clk_foo's clk_ops
315 *
316 * @core: pointer to the struct clk_core instance that points back to this
317 * struct clk_hw instance
318 *
319 * @clk: pointer to the per-user struct clk instance that can be used to call
320 * into the clk API
321 *
322 * @init: pointer to struct clk_init_data that contains the init data shared
323 * with the common clock framework. This pointer will be set to NULL once
324 * a clk_register() variant is called on this clk_hw pointer.
325 */
326 struct clk_hw {
327 struct clk_core *core;
328 struct clk *clk;
329 const struct clk_init_data *init;
330 };
331
332 /*
333 * DOC: Basic clock implementations common to many platforms
334 *
335 * Each basic clock hardware type is comprised of a structure describing the
336 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
337 * unique flags for that hardware type, a registration function and an
338 * alternative macro for static initialization
339 */
340
341 /**
342 * struct clk_fixed_rate - fixed-rate clock
343 * @hw: handle between common and hardware-specific interfaces
344 * @fixed_rate: constant frequency of clock
345 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
346 * @flags: hardware specific flags
347 *
348 * Flags:
349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
350 * instead of what's set in @fixed_accuracy.
351 */
352 struct clk_fixed_rate {
353 struct clk_hw hw;
354 unsigned long fixed_rate;
355 unsigned long fixed_accuracy;
356 unsigned long flags;
357 };
358
359 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
360
361 extern const struct clk_ops clk_fixed_rate_ops;
362 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
363 struct device_node *np, const char *name,
364 const char *parent_name, const struct clk_hw *parent_hw,
365 const struct clk_parent_data *parent_data, unsigned long flags,
366 unsigned long fixed_rate, unsigned long fixed_accuracy,
367 unsigned long clk_fixed_flags);
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
369 const char *parent_name, unsigned long flags,
370 unsigned long fixed_rate);
371 /**
372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
373 * framework
374 * @dev: device that is registering this clock
375 * @name: name of this clock
376 * @parent_name: name of clock's parent
377 * @flags: framework-specific flags
378 * @fixed_rate: non-adjustable clock rate
379 */
380 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
381 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
382 NULL, (flags), (fixed_rate), 0, 0)
383 /**
384 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
385 * the clock framework
386 * @dev: device that is registering this clock
387 * @name: name of this clock
388 * @parent_hw: pointer to parent clk
389 * @flags: framework-specific flags
390 * @fixed_rate: non-adjustable clock rate
391 */
392 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
393 fixed_rate) \
394 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
395 NULL, (flags), (fixed_rate), 0, 0)
396 /**
397 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
401 * @parent_data: parent clk data
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
404 */
405 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
406 fixed_rate) \
407 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
408 (parent_data), (flags), (fixed_rate), 0, \
409 0)
410 /**
411 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
412 * the clock framework
413 * @dev: device that is registering this clock
414 * @name: name of this clock
415 * @parent_name: name of clock's parent
416 * @flags: framework-specific flags
417 * @fixed_rate: non-adjustable clock rate
418 * @fixed_accuracy: non-adjustable clock accuracy
419 */
420 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
421 flags, fixed_rate, \
422 fixed_accuracy) \
423 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
424 NULL, NULL, (flags), (fixed_rate), \
425 (fixed_accuracy), 0)
426 /**
427 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
428 * clock with the clock framework
429 * @dev: device that is registering this clock
430 * @name: name of this clock
431 * @parent_hw: pointer to parent clk
432 * @flags: framework-specific flags
433 * @fixed_rate: non-adjustable clock rate
434 * @fixed_accuracy: non-adjustable clock accuracy
435 */
436 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
437 parent_hw, flags, fixed_rate, fixed_accuracy) \
438 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
439 NULL, NULL, (flags), (fixed_rate), \
440 (fixed_accuracy), 0)
441 /**
442 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
443 * clock with the clock framework
444 * @dev: device that is registering this clock
445 * @name: name of this clock
446 * @parent_data: name of clock's parent
447 * @flags: framework-specific flags
448 * @fixed_rate: non-adjustable clock rate
449 * @fixed_accuracy: non-adjustable clock accuracy
450 */
451 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
452 parent_data, flags, fixed_rate, fixed_accuracy) \
453 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
454 (parent_data), NULL, (flags), \
455 (fixed_rate), (fixed_accuracy), 0)
456 /**
457 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
458 * the clock framework
459 * @dev: device that is registering this clock
460 * @name: name of this clock
461 * @parent_data: name of clock's parent
462 * @flags: framework-specific flags
463 * @fixed_rate: non-adjustable clock rate
464 */
465 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
466 flags, fixed_rate) \
467 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
468 (parent_data), (flags), (fixed_rate), 0, \
469 CLK_FIXED_RATE_PARENT_ACCURACY)
470
471 void clk_unregister_fixed_rate(struct clk *clk);
472 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
473
474 void of_fixed_clk_setup(struct device_node *np);
475
476 /**
477 * struct clk_gate - gating clock
478 *
479 * @hw: handle between common and hardware-specific interfaces
480 * @reg: register controlling gate
481 * @bit_idx: single bit controlling gate
482 * @flags: hardware-specific flags
483 * @lock: register lock
484 *
485 * Clock which can gate its output. Implements .enable & .disable
486 *
487 * Flags:
488 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
489 * enable the clock. Setting this flag does the opposite: setting the bit
490 * disable the clock and clearing it enables the clock
491 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
492 * of this register, and mask of gate bits are in higher 16-bit of this
493 * register. While setting the gate bits, higher 16-bit should also be
494 * updated to indicate changing gate bits.
495 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
496 * the gate register. Setting this flag makes the register accesses big
497 * endian.
498 */
499 struct clk_gate {
500 struct clk_hw hw;
501 void __iomem *reg;
502 u8 bit_idx;
503 u8 flags;
504 spinlock_t *lock;
505 };
506
507 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
508
509 #define CLK_GATE_SET_TO_DISABLE BIT(0)
510 #define CLK_GATE_HIWORD_MASK BIT(1)
511 #define CLK_GATE_BIG_ENDIAN BIT(2)
512
513 extern const struct clk_ops clk_gate_ops;
514 struct clk_hw *__clk_hw_register_gate(struct device *dev,
515 struct device_node *np, const char *name,
516 const char *parent_name, const struct clk_hw *parent_hw,
517 const struct clk_parent_data *parent_data,
518 unsigned long flags,
519 void __iomem *reg, u8 bit_idx,
520 u8 clk_gate_flags, spinlock_t *lock);
521 struct clk *clk_register_gate(struct device *dev, const char *name,
522 const char *parent_name, unsigned long flags,
523 void __iomem *reg, u8 bit_idx,
524 u8 clk_gate_flags, spinlock_t *lock);
525 /**
526 * clk_hw_register_gate - register a gate clock with the clock framework
527 * @dev: device that is registering this clock
528 * @name: name of this clock
529 * @parent_name: name of this clock's parent
530 * @flags: framework-specific flags for this clock
531 * @reg: register address to control gating of this clock
532 * @bit_idx: which bit in the register controls gating of this clock
533 * @clk_gate_flags: gate-specific flags for this clock
534 * @lock: shared register lock for this clock
535 */
536 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
537 clk_gate_flags, lock) \
538 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
539 NULL, (flags), (reg), (bit_idx), \
540 (clk_gate_flags), (lock))
541 /**
542 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
543 * framework
544 * @dev: device that is registering this clock
545 * @name: name of this clock
546 * @parent_hw: pointer to parent clk
547 * @flags: framework-specific flags for this clock
548 * @reg: register address to control gating of this clock
549 * @bit_idx: which bit in the register controls gating of this clock
550 * @clk_gate_flags: gate-specific flags for this clock
551 * @lock: shared register lock for this clock
552 */
553 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
554 bit_idx, clk_gate_flags, lock) \
555 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
556 NULL, (flags), (reg), (bit_idx), \
557 (clk_gate_flags), (lock))
558 /**
559 * clk_hw_register_gate_parent_data - register a gate clock with the clock
560 * framework
561 * @dev: device that is registering this clock
562 * @name: name of this clock
563 * @parent_data: parent clk data
564 * @flags: framework-specific flags for this clock
565 * @reg: register address to control gating of this clock
566 * @bit_idx: which bit in the register controls gating of this clock
567 * @clk_gate_flags: gate-specific flags for this clock
568 * @lock: shared register lock for this clock
569 */
570 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
571 bit_idx, clk_gate_flags, lock) \
572 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
573 (flags), (reg), (bit_idx), \
574 (clk_gate_flags), (lock))
575 void clk_unregister_gate(struct clk *clk);
576 void clk_hw_unregister_gate(struct clk_hw *hw);
577 int clk_gate_is_enabled(struct clk_hw *hw);
578
579 struct clk_div_table {
580 unsigned int val;
581 unsigned int div;
582 };
583
584 /**
585 * struct clk_divider - adjustable divider clock
586 *
587 * @hw: handle between common and hardware-specific interfaces
588 * @reg: register containing the divider
589 * @shift: shift to the divider bit field
590 * @width: width of the divider bit field
591 * @table: array of value/divider pairs, last entry should have div = 0
592 * @lock: register lock
593 *
594 * Clock with an adjustable divider affecting its output frequency. Implements
595 * .recalc_rate, .set_rate and .round_rate
596 *
597 * @flags:
598 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
599 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
600 * the raw value read from the register, with the value of zero considered
601 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
602 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
603 * the hardware register
604 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
605 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
606 * Some hardware implementations gracefully handle this case and allow a
607 * zero divisor by not modifying their input clock
608 * (divide by one / bypass).
609 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
610 * of this register, and mask of divider bits are in higher 16-bit of this
611 * register. While setting the divider bits, higher 16-bit should also be
612 * updated to indicate changing divider bits.
613 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
614 * to the closest integer instead of the up one.
615 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
616 * not be changed by the clock framework.
617 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
618 * except when the value read from the register is zero, the divisor is
619 * 2^width of the field.
620 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
621 * for the divider register. Setting this flag makes the register accesses
622 * big endian.
623 */
624 struct clk_divider {
625 struct clk_hw hw;
626 void __iomem *reg;
627 u8 shift;
628 u8 width;
629 u8 flags;
630 const struct clk_div_table *table;
631 spinlock_t *lock;
632 };
633
634 #define clk_div_mask(width) ((1 << (width)) - 1)
635 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
636
637 #define CLK_DIVIDER_ONE_BASED BIT(0)
638 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
639 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
640 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
641 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
642 #define CLK_DIVIDER_READ_ONLY BIT(5)
643 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
644 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
645
646 extern const struct clk_ops clk_divider_ops;
647 extern const struct clk_ops clk_divider_ro_ops;
648
649 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
650 unsigned int val, const struct clk_div_table *table,
651 unsigned long flags, unsigned long width);
652 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
653 unsigned long rate, unsigned long *prate,
654 const struct clk_div_table *table,
655 u8 width, unsigned long flags);
656 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
657 unsigned long rate, unsigned long *prate,
658 const struct clk_div_table *table, u8 width,
659 unsigned long flags, unsigned int val);
660 int divider_get_val(unsigned long rate, unsigned long parent_rate,
661 const struct clk_div_table *table, u8 width,
662 unsigned long flags);
663
664 struct clk_hw *__clk_hw_register_divider(struct device *dev,
665 struct device_node *np, const char *name,
666 const char *parent_name, const struct clk_hw *parent_hw,
667 const struct clk_parent_data *parent_data, unsigned long flags,
668 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
669 const struct clk_div_table *table, spinlock_t *lock);
670 struct clk *clk_register_divider_table(struct device *dev, const char *name,
671 const char *parent_name, unsigned long flags,
672 void __iomem *reg, u8 shift, u8 width,
673 u8 clk_divider_flags, const struct clk_div_table *table,
674 spinlock_t *lock);
675 /**
676 * clk_register_divider - register a divider clock with the clock framework
677 * @dev: device registering this clock
678 * @name: name of this clock
679 * @parent_name: name of clock's parent
680 * @flags: framework-specific flags
681 * @reg: register address to adjust divider
682 * @shift: number of bits to shift the bitfield
683 * @width: width of the bitfield
684 * @clk_divider_flags: divider-specific flags for this clock
685 * @lock: shared register lock for this clock
686 */
687 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
688 clk_divider_flags, lock) \
689 clk_register_divider_table((dev), (name), (parent_name), (flags), \
690 (reg), (shift), (width), \
691 (clk_divider_flags), NULL, (lock))
692 /**
693 * clk_hw_register_divider - register a divider clock with the clock framework
694 * @dev: device registering this clock
695 * @name: name of this clock
696 * @parent_name: name of clock's parent
697 * @flags: framework-specific flags
698 * @reg: register address to adjust divider
699 * @shift: number of bits to shift the bitfield
700 * @width: width of the bitfield
701 * @clk_divider_flags: divider-specific flags for this clock
702 * @lock: shared register lock for this clock
703 */
704 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
705 width, clk_divider_flags, lock) \
706 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
707 NULL, (flags), (reg), (shift), (width), \
708 (clk_divider_flags), NULL, (lock))
709 /**
710 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
711 * framework
712 * @dev: device registering this clock
713 * @name: name of this clock
714 * @parent_hw: pointer to parent clk
715 * @flags: framework-specific flags
716 * @reg: register address to adjust divider
717 * @shift: number of bits to shift the bitfield
718 * @width: width of the bitfield
719 * @clk_divider_flags: divider-specific flags for this clock
720 * @lock: shared register lock for this clock
721 */
722 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
723 shift, width, clk_divider_flags, \
724 lock) \
725 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
726 NULL, (flags), (reg), (shift), (width), \
727 (clk_divider_flags), NULL, (lock))
728 /**
729 * clk_hw_register_divider_parent_data - register a divider clock with the clock
730 * framework
731 * @dev: device registering this clock
732 * @name: name of this clock
733 * @parent_data: parent clk data
734 * @flags: framework-specific flags
735 * @reg: register address to adjust divider
736 * @shift: number of bits to shift the bitfield
737 * @width: width of the bitfield
738 * @clk_divider_flags: divider-specific flags for this clock
739 * @lock: shared register lock for this clock
740 */
741 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
742 reg, shift, width, \
743 clk_divider_flags, lock) \
744 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
745 (parent_data), (flags), (reg), (shift), \
746 (width), (clk_divider_flags), NULL, (lock))
747 /**
748 * clk_hw_register_divider_table - register a table based divider clock with
749 * the clock framework
750 * @dev: device registering this clock
751 * @name: name of this clock
752 * @parent_name: name of clock's parent
753 * @flags: framework-specific flags
754 * @reg: register address to adjust divider
755 * @shift: number of bits to shift the bitfield
756 * @width: width of the bitfield
757 * @clk_divider_flags: divider-specific flags for this clock
758 * @table: array of divider/value pairs ending with a div set to 0
759 * @lock: shared register lock for this clock
760 */
761 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
762 shift, width, clk_divider_flags, table, \
763 lock) \
764 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
765 NULL, (flags), (reg), (shift), (width), \
766 (clk_divider_flags), (table), (lock))
767 /**
768 * clk_hw_register_divider_table_parent_hw - register a table based divider
769 * clock with the clock framework
770 * @dev: device registering this clock
771 * @name: name of this clock
772 * @parent_hw: pointer to parent clk
773 * @flags: framework-specific flags
774 * @reg: register address to adjust divider
775 * @shift: number of bits to shift the bitfield
776 * @width: width of the bitfield
777 * @clk_divider_flags: divider-specific flags for this clock
778 * @table: array of divider/value pairs ending with a div set to 0
779 * @lock: shared register lock for this clock
780 */
781 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
782 reg, shift, width, \
783 clk_divider_flags, table, \
784 lock) \
785 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
786 NULL, (flags), (reg), (shift), (width), \
787 (clk_divider_flags), (table), (lock))
788 /**
789 * clk_hw_register_divider_table_parent_data - register a table based divider
790 * clock with the clock framework
791 * @dev: device registering this clock
792 * @name: name of this clock
793 * @parent_data: parent clk data
794 * @flags: framework-specific flags
795 * @reg: register address to adjust divider
796 * @shift: number of bits to shift the bitfield
797 * @width: width of the bitfield
798 * @clk_divider_flags: divider-specific flags for this clock
799 * @table: array of divider/value pairs ending with a div set to 0
800 * @lock: shared register lock for this clock
801 */
802 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
803 flags, reg, shift, width, \
804 clk_divider_flags, table, \
805 lock) \
806 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
807 (parent_data), (flags), (reg), (shift), \
808 (width), (clk_divider_flags), (table), \
809 (lock))
810
811 void clk_unregister_divider(struct clk *clk);
812 void clk_hw_unregister_divider(struct clk_hw *hw);
813
814 /**
815 * struct clk_mux - multiplexer clock
816 *
817 * @hw: handle between common and hardware-specific interfaces
818 * @reg: register controlling multiplexer
819 * @table: array of register values corresponding to the parent index
820 * @shift: shift to multiplexer bit field
821 * @mask: mask of mutliplexer bit field
822 * @flags: hardware-specific flags
823 * @lock: register lock
824 *
825 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
826 * and .recalc_rate
827 *
828 * Flags:
829 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
830 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
831 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
832 * register, and mask of mux bits are in higher 16-bit of this register.
833 * While setting the mux bits, higher 16-bit should also be updated to
834 * indicate changing mux bits.
835 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
836 * .get_parent clk_op.
837 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
838 * frequency.
839 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
840 * the mux register. Setting this flag makes the register accesses big
841 * endian.
842 */
843 struct clk_mux {
844 struct clk_hw hw;
845 void __iomem *reg;
846 u32 *table;
847 u32 mask;
848 u8 shift;
849 u8 flags;
850 spinlock_t *lock;
851 };
852
853 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
854
855 #define CLK_MUX_INDEX_ONE BIT(0)
856 #define CLK_MUX_INDEX_BIT BIT(1)
857 #define CLK_MUX_HIWORD_MASK BIT(2)
858 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
859 #define CLK_MUX_ROUND_CLOSEST BIT(4)
860 #define CLK_MUX_BIG_ENDIAN BIT(5)
861
862 extern const struct clk_ops clk_mux_ops;
863 extern const struct clk_ops clk_mux_ro_ops;
864
865 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
866 const char *name, u8 num_parents,
867 const char * const *parent_names,
868 const struct clk_hw **parent_hws,
869 const struct clk_parent_data *parent_data,
870 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
871 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
872 struct clk *clk_register_mux_table(struct device *dev, const char *name,
873 const char * const *parent_names, u8 num_parents,
874 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
875 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
876
877 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
878 shift, width, clk_mux_flags, lock) \
879 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
880 (flags), (reg), (shift), BIT((width)) - 1, \
881 (clk_mux_flags), NULL, (lock))
882 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
883 flags, reg, shift, mask, clk_mux_flags, \
884 table, lock) \
885 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
886 (parent_names), NULL, NULL, (flags), (reg), \
887 (shift), (mask), (clk_mux_flags), (table), \
888 (lock))
889 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
890 num_parents, flags, reg, shift, mask, \
891 clk_mux_flags, table, lock) \
892 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
893 NULL, NULL, (parent_data), (flags), (reg), \
894 (shift), (mask), (clk_mux_flags), (table), \
895 (lock))
896 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
897 shift, width, clk_mux_flags, lock) \
898 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
899 (parent_names), NULL, NULL, (flags), (reg), \
900 (shift), BIT((width)) - 1, (clk_mux_flags), \
901 NULL, (lock))
902 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
903 reg, shift, width, clk_mux_flags, lock) \
904 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
905 (parent_hws), NULL, (flags), (reg), (shift), \
906 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
907 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
908 flags, reg, shift, width, \
909 clk_mux_flags, lock) \
910 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
911 (parent_data), (flags), (reg), (shift), \
912 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
913
914 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
915 unsigned int val);
916 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
917
918 void clk_unregister_mux(struct clk *clk);
919 void clk_hw_unregister_mux(struct clk_hw *hw);
920
921 void of_fixed_factor_clk_setup(struct device_node *node);
922
923 /**
924 * struct clk_fixed_factor - fixed multiplier and divider clock
925 *
926 * @hw: handle between common and hardware-specific interfaces
927 * @mult: multiplier
928 * @div: divider
929 *
930 * Clock with a fixed multiplier and divider. The output frequency is the
931 * parent clock rate divided by div and multiplied by mult.
932 * Implements .recalc_rate, .set_rate and .round_rate
933 */
934
935 struct clk_fixed_factor {
936 struct clk_hw hw;
937 unsigned int mult;
938 unsigned int div;
939 };
940
941 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
942
943 extern const struct clk_ops clk_fixed_factor_ops;
944 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
945 const char *parent_name, unsigned long flags,
946 unsigned int mult, unsigned int div);
947 void clk_unregister_fixed_factor(struct clk *clk);
948 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
949 const char *name, const char *parent_name, unsigned long flags,
950 unsigned int mult, unsigned int div);
951 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
952
953 /**
954 * struct clk_fractional_divider - adjustable fractional divider clock
955 *
956 * @hw: handle between common and hardware-specific interfaces
957 * @reg: register containing the divider
958 * @mshift: shift to the numerator bit field
959 * @mwidth: width of the numerator bit field
960 * @nshift: shift to the denominator bit field
961 * @nwidth: width of the denominator bit field
962 * @approximation: clk driver's callback for calculating the divider clock
963 * @lock: register lock
964 *
965 * Clock with adjustable fractional divider affecting its output frequency.
966 *
967 * @flags:
968 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
969 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
970 * is set then the numerator and denominator are both the value read
971 * plus one.
972 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
973 * used for the divider register. Setting this flag makes the register
974 * accesses big endian.
975 */
976 struct clk_fractional_divider {
977 struct clk_hw hw;
978 void __iomem *reg;
979 u8 mshift;
980 u8 mwidth;
981 u32 mmask;
982 u8 nshift;
983 u8 nwidth;
984 u32 nmask;
985 u8 flags;
986 void (*approximation)(struct clk_hw *hw,
987 unsigned long rate, unsigned long *parent_rate,
988 unsigned long *m, unsigned long *n);
989 spinlock_t *lock;
990 };
991
992 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
993
994 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
995 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
996
997 extern const struct clk_ops clk_fractional_divider_ops;
998 struct clk *clk_register_fractional_divider(struct device *dev,
999 const char *name, const char *parent_name, unsigned long flags,
1000 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1001 u8 clk_divider_flags, spinlock_t *lock);
1002 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1003 const char *name, const char *parent_name, unsigned long flags,
1004 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1005 u8 clk_divider_flags, spinlock_t *lock);
1006 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1007
1008 /**
1009 * struct clk_multiplier - adjustable multiplier clock
1010 *
1011 * @hw: handle between common and hardware-specific interfaces
1012 * @reg: register containing the multiplier
1013 * @shift: shift to the multiplier bit field
1014 * @width: width of the multiplier bit field
1015 * @lock: register lock
1016 *
1017 * Clock with an adjustable multiplier affecting its output frequency.
1018 * Implements .recalc_rate, .set_rate and .round_rate
1019 *
1020 * @flags:
1021 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1022 * from the register, with 0 being a valid value effectively
1023 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1024 * set, then a null multiplier will be considered as a bypass,
1025 * leaving the parent rate unmodified.
1026 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1027 * rounded to the closest integer instead of the down one.
1028 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1029 * used for the multiplier register. Setting this flag makes the register
1030 * accesses big endian.
1031 */
1032 struct clk_multiplier {
1033 struct clk_hw hw;
1034 void __iomem *reg;
1035 u8 shift;
1036 u8 width;
1037 u8 flags;
1038 spinlock_t *lock;
1039 };
1040
1041 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1042
1043 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1044 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1045 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1046
1047 extern const struct clk_ops clk_multiplier_ops;
1048
1049 /***
1050 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1051 *
1052 * @hw: handle between common and hardware-specific interfaces
1053 * @mux_hw: handle between composite and hardware-specific mux clock
1054 * @rate_hw: handle between composite and hardware-specific rate clock
1055 * @gate_hw: handle between composite and hardware-specific gate clock
1056 * @mux_ops: clock ops for mux
1057 * @rate_ops: clock ops for rate
1058 * @gate_ops: clock ops for gate
1059 */
1060 struct clk_composite {
1061 struct clk_hw hw;
1062 struct clk_ops ops;
1063
1064 struct clk_hw *mux_hw;
1065 struct clk_hw *rate_hw;
1066 struct clk_hw *gate_hw;
1067
1068 const struct clk_ops *mux_ops;
1069 const struct clk_ops *rate_ops;
1070 const struct clk_ops *gate_ops;
1071 };
1072
1073 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1074
1075 struct clk *clk_register_composite(struct device *dev, const char *name,
1076 const char * const *parent_names, int num_parents,
1077 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1078 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1079 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1080 unsigned long flags);
1081 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1082 const struct clk_parent_data *parent_data, int num_parents,
1083 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1084 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1085 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1086 unsigned long flags);
1087 void clk_unregister_composite(struct clk *clk);
1088 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1089 const char * const *parent_names, int num_parents,
1090 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1091 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1092 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1093 unsigned long flags);
1094 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1095 const char *name,
1096 const struct clk_parent_data *parent_data, int num_parents,
1097 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1098 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1099 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1100 unsigned long flags);
1101 void clk_hw_unregister_composite(struct clk_hw *hw);
1102
1103 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1104 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1105
1106 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1107 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1108 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1109
1110 void clk_unregister(struct clk *clk);
1111 void devm_clk_unregister(struct device *dev, struct clk *clk);
1112
1113 void clk_hw_unregister(struct clk_hw *hw);
1114 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1115 void clk_sync_state(struct device *dev);
1116
1117 /* helper functions */
1118 const char *__clk_get_name(const struct clk *clk);
1119 const char *clk_hw_get_name(const struct clk_hw *hw);
1120 #ifdef CONFIG_COMMON_CLK
1121 struct clk_hw *__clk_get_hw(struct clk *clk);
1122 #else
__clk_get_hw(struct clk * clk)1123 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1124 {
1125 return (struct clk_hw *)clk;
1126 }
1127 #endif
1128
1129 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1130 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1131 const char *con_id);
1132
1133 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1134 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1135 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1136 unsigned int index);
1137 int clk_hw_get_parent_index(struct clk_hw *hw);
1138 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1139 unsigned int __clk_get_enable_count(struct clk *clk);
1140 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1141 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1142 #define clk_hw_can_set_rate_parent(hw) \
1143 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1144
1145 bool clk_hw_is_prepared(const struct clk_hw *hw);
1146 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1147 bool clk_hw_is_enabled(const struct clk_hw *hw);
1148 bool __clk_is_enabled(struct clk *clk);
1149 struct clk *__clk_lookup(const char *name);
1150 int __clk_mux_determine_rate(struct clk_hw *hw,
1151 struct clk_rate_request *req);
1152 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1153 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1154 struct clk_rate_request *req);
1155 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1156 struct clk_rate_request *req,
1157 unsigned long flags);
1158 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1159 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1160 unsigned long max_rate);
1161
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1162 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1163 {
1164 dst->clk = src->clk;
1165 dst->core = src->core;
1166 }
1167
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1168 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1169 unsigned long *prate,
1170 const struct clk_div_table *table,
1171 u8 width, unsigned long flags)
1172 {
1173 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1174 rate, prate, table, width, flags);
1175 }
1176
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1177 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1178 unsigned long *prate,
1179 const struct clk_div_table *table,
1180 u8 width, unsigned long flags,
1181 unsigned int val)
1182 {
1183 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1184 rate, prate, table, width, flags,
1185 val);
1186 }
1187
1188 /*
1189 * FIXME clock api without lock protection
1190 */
1191 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1192
1193 struct clk_onecell_data {
1194 struct clk **clks;
1195 unsigned int clk_num;
1196 };
1197
1198 struct clk_hw_onecell_data {
1199 unsigned int num;
1200 struct clk_hw *hws[];
1201 };
1202
1203 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1204
1205 /*
1206 * Use this macro when you have a driver that requires two initialization
1207 * routines, one at of_clk_init(), and one at platform device probe
1208 */
1209 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1210 static void __init name##_of_clk_init_driver(struct device_node *np) \
1211 { \
1212 of_node_clear_flag(np, OF_POPULATED); \
1213 fn(np); \
1214 } \
1215 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1216
1217 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1218 (&(struct clk_init_data) { \
1219 .flags = _flags, \
1220 .name = _name, \
1221 .parent_names = (const char *[]) { _parent }, \
1222 .num_parents = 1, \
1223 .ops = _ops, \
1224 })
1225
1226 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1227 (&(struct clk_init_data) { \
1228 .flags = _flags, \
1229 .name = _name, \
1230 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1231 .num_parents = 1, \
1232 .ops = _ops, \
1233 })
1234
1235 /*
1236 * This macro is intended for drivers to be able to share the otherwise
1237 * individual struct clk_hw[] compound literals created by the compiler
1238 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1239 */
1240 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1241 (&(struct clk_init_data) { \
1242 .flags = _flags, \
1243 .name = _name, \
1244 .parent_hws = _parent, \
1245 .num_parents = 1, \
1246 .ops = _ops, \
1247 })
1248
1249 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1250 (&(struct clk_init_data) { \
1251 .flags = _flags, \
1252 .name = _name, \
1253 .parent_data = (const struct clk_parent_data[]) { \
1254 { .fw_name = _parent }, \
1255 }, \
1256 .num_parents = 1, \
1257 .ops = _ops, \
1258 })
1259
1260 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1261 (&(struct clk_init_data) { \
1262 .flags = _flags, \
1263 .name = _name, \
1264 .parent_names = _parents, \
1265 .num_parents = ARRAY_SIZE(_parents), \
1266 .ops = _ops, \
1267 })
1268
1269 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1270 (&(struct clk_init_data) { \
1271 .flags = _flags, \
1272 .name = _name, \
1273 .parent_hws = _parents, \
1274 .num_parents = ARRAY_SIZE(_parents), \
1275 .ops = _ops, \
1276 })
1277
1278 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1279 (&(struct clk_init_data) { \
1280 .flags = _flags, \
1281 .name = _name, \
1282 .parent_data = _parents, \
1283 .num_parents = ARRAY_SIZE(_parents), \
1284 .ops = _ops, \
1285 })
1286
1287 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1288 (&(struct clk_init_data) { \
1289 .flags = _flags, \
1290 .name = _name, \
1291 .parent_names = NULL, \
1292 .num_parents = 0, \
1293 .ops = _ops, \
1294 })
1295
1296 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1297 _div, _mult, _flags) \
1298 struct clk_fixed_factor _struct = { \
1299 .div = _div, \
1300 .mult = _mult, \
1301 .hw.init = CLK_HW_INIT(_name, \
1302 _parent, \
1303 &clk_fixed_factor_ops, \
1304 _flags), \
1305 }
1306
1307 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1308 _div, _mult, _flags) \
1309 struct clk_fixed_factor _struct = { \
1310 .div = _div, \
1311 .mult = _mult, \
1312 .hw.init = CLK_HW_INIT_HW(_name, \
1313 _parent, \
1314 &clk_fixed_factor_ops, \
1315 _flags), \
1316 }
1317
1318 /*
1319 * This macro allows the driver to reuse the _parent array for multiple
1320 * fixed factor clk declarations.
1321 */
1322 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1323 _div, _mult, _flags) \
1324 struct clk_fixed_factor _struct = { \
1325 .div = _div, \
1326 .mult = _mult, \
1327 .hw.init = CLK_HW_INIT_HWS(_name, \
1328 _parent, \
1329 &clk_fixed_factor_ops, \
1330 _flags), \
1331 }
1332
1333 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1334 _div, _mult, _flags) \
1335 struct clk_fixed_factor _struct = { \
1336 .div = _div, \
1337 .mult = _mult, \
1338 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1339 _parent, \
1340 &clk_fixed_factor_ops, \
1341 _flags), \
1342 }
1343
1344 #ifdef CONFIG_OF
1345 int of_clk_add_provider(struct device_node *np,
1346 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1347 void *data),
1348 void *data);
1349 int of_clk_add_hw_provider(struct device_node *np,
1350 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1351 void *data),
1352 void *data);
1353 int devm_of_clk_add_hw_provider(struct device *dev,
1354 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1355 void *data),
1356 void *data);
1357 void of_clk_del_provider(struct device_node *np);
1358 void devm_of_clk_del_provider(struct device *dev);
1359 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1360 void *data);
1361 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1362 void *data);
1363 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1364 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1365 void *data);
1366 int of_clk_parent_fill(struct device_node *np, const char **parents,
1367 unsigned int size);
1368 int of_clk_detect_critical(struct device_node *np, int index,
1369 unsigned long *flags);
1370
1371 #else /* !CONFIG_OF */
1372
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1373 static inline int of_clk_add_provider(struct device_node *np,
1374 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1375 void *data),
1376 void *data)
1377 {
1378 return 0;
1379 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1380 static inline int of_clk_add_hw_provider(struct device_node *np,
1381 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1382 void *data),
1383 void *data)
1384 {
1385 return 0;
1386 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1387 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1388 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1389 void *data),
1390 void *data)
1391 {
1392 return 0;
1393 }
of_clk_del_provider(struct device_node * np)1394 static inline void of_clk_del_provider(struct device_node *np) {}
devm_of_clk_del_provider(struct device * dev)1395 static inline void devm_of_clk_del_provider(struct device *dev) {}
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1396 static inline struct clk *of_clk_src_simple_get(
1397 struct of_phandle_args *clkspec, void *data)
1398 {
1399 return ERR_PTR(-ENOENT);
1400 }
1401 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1402 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1403 {
1404 return ERR_PTR(-ENOENT);
1405 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1406 static inline struct clk *of_clk_src_onecell_get(
1407 struct of_phandle_args *clkspec, void *data)
1408 {
1409 return ERR_PTR(-ENOENT);
1410 }
1411 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1412 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1413 {
1414 return ERR_PTR(-ENOENT);
1415 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1416 static inline int of_clk_parent_fill(struct device_node *np,
1417 const char **parents, unsigned int size)
1418 {
1419 return 0;
1420 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1421 static inline int of_clk_detect_critical(struct device_node *np, int index,
1422 unsigned long *flags)
1423 {
1424 return 0;
1425 }
1426 #endif /* CONFIG_OF */
1427
1428 void clk_gate_restore_context(struct clk_hw *hw);
1429
1430 #endif /* CLK_PROVIDER_H */
1431