1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_IRQ_H
3 #define _LINUX_IRQ_H
4
5 /*
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
8 * within this file.
9 *
10 * Thanks. --rmk
11 */
12
13 #include <linux/cache.h>
14 #include <linux/spinlock.h>
15 #include <linux/cpumask.h>
16 #include <linux/irqhandler.h>
17 #include <linux/irqreturn.h>
18 #include <linux/irqnr.h>
19 #include <linux/topology.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22
23 #include <asm/irq.h>
24 #include <asm/ptrace.h>
25 #include <asm/irq_regs.h>
26
27 struct seq_file;
28 struct module;
29 struct msi_msg;
30 struct irq_affinity_desc;
31 enum irqchip_irq_state;
32
33 /*
34 * IRQ line status.
35 *
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
37 *
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 * to setup the HW to a sane default (used
48 * by irqdomain map() callbacks to synchronize
49 * the HW state and SW flags for a newly
50 * allocated descriptor).
51 *
52 * IRQ_TYPE_PROBE - Special flag for probing in progress
53 *
54 * Bits which can be modified via irq_set/clear/modify_status_flags()
55 * IRQ_LEVEL - Interrupt is level type. Will be also
56 * updated in the code when the above trigger
57 * bits are modified via irq_set_irq_type()
58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 * it from affinity setting
60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 * IRQ_NOREQUEST - Interrupt cannot be requested via
62 * request_irq()
63 * IRQ_NOTHREAD - Interrupt cannot be threaded
64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
65 * request/setup_irq()
66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
68 * IRQ_NESTED_THREAD - Interrupt nests into another thread
69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 * it from the spurious interrupt detection
72 * mechanism and from core side polling.
73 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
74 * IRQ_HIDDEN - Don't show up in /proc/interrupts
75 * IRQ_RAW - Skip tick management and irqtime accounting
76 */
77 enum {
78 IRQ_TYPE_NONE = 0x00000000,
79 IRQ_TYPE_EDGE_RISING = 0x00000001,
80 IRQ_TYPE_EDGE_FALLING = 0x00000002,
81 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
83 IRQ_TYPE_LEVEL_LOW = 0x00000008,
84 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 IRQ_TYPE_SENSE_MASK = 0x0000000f,
86 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
87
88 IRQ_TYPE_PROBE = 0x00000010,
89
90 IRQ_LEVEL = (1 << 8),
91 IRQ_PER_CPU = (1 << 9),
92 IRQ_NOPROBE = (1 << 10),
93 IRQ_NOREQUEST = (1 << 11),
94 IRQ_NOAUTOEN = (1 << 12),
95 IRQ_NO_BALANCING = (1 << 13),
96 IRQ_MOVE_PCNTXT = (1 << 14),
97 IRQ_NESTED_THREAD = (1 << 15),
98 IRQ_NOTHREAD = (1 << 16),
99 IRQ_PER_CPU_DEVID = (1 << 17),
100 IRQ_IS_POLLED = (1 << 18),
101 IRQ_DISABLE_UNLAZY = (1 << 19),
102 IRQ_HIDDEN = (1 << 20),
103 IRQ_RAW = (1 << 21),
104 };
105
106 #define IRQF_MODIFY_MASK \
107 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
108 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
109 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
110 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
111
112 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
113
114 /*
115 * Return value for chip->irq_set_affinity()
116 *
117 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
118 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
119 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
120 * support stacked irqchips, which indicates skipping
121 * all descendant irqchips.
122 */
123 enum {
124 IRQ_SET_MASK_OK = 0,
125 IRQ_SET_MASK_OK_NOCOPY,
126 IRQ_SET_MASK_OK_DONE,
127 };
128
129 struct msi_desc;
130 struct irq_domain;
131
132 /**
133 * struct irq_common_data - per irq data shared by all irqchips
134 * @state_use_accessors: status information for irq chip functions.
135 * Use accessor functions to deal with it
136 * @node: node index useful for balancing
137 * @handler_data: per-IRQ data for the irq_chip methods
138 * @affinity: IRQ affinity on SMP. If this is an IPI
139 * related irq, then this is the mask of the
140 * CPUs to which an IPI can be sent.
141 * @effective_affinity: The effective IRQ affinity on SMP as some irq
142 * chips do not allow multi CPU destinations.
143 * A subset of @affinity.
144 * @msi_desc: MSI descriptor
145 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
146 */
147 struct irq_common_data {
148 unsigned int __private state_use_accessors;
149 #ifdef CONFIG_NUMA
150 unsigned int node;
151 #endif
152 void *handler_data;
153 struct msi_desc *msi_desc;
154 cpumask_var_t affinity;
155 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
156 cpumask_var_t effective_affinity;
157 #endif
158 #ifdef CONFIG_GENERIC_IRQ_IPI
159 unsigned int ipi_offset;
160 #endif
161 };
162
163 /**
164 * struct irq_data - per irq chip data passed down to chip functions
165 * @mask: precomputed bitmask for accessing the chip registers
166 * @irq: interrupt number
167 * @hwirq: hardware interrupt number, local to the interrupt domain
168 * @common: point to data shared by all irqchips
169 * @chip: low level interrupt hardware access
170 * @domain: Interrupt translation domain; responsible for mapping
171 * between hwirq number and linux irq number.
172 * @parent_data: pointer to parent struct irq_data to support hierarchy
173 * irq_domain
174 * @chip_data: platform-specific per-chip private data for the chip
175 * methods, to allow shared chip implementations
176 */
177 struct irq_data {
178 u32 mask;
179 unsigned int irq;
180 unsigned long hwirq;
181 struct irq_common_data *common;
182 struct irq_chip *chip;
183 struct irq_domain *domain;
184 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
185 struct irq_data *parent_data;
186 #endif
187 void *chip_data;
188 };
189
190 /*
191 * Bit masks for irq_common_data.state_use_accessors
192 *
193 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
194 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
195 * IRQD_ACTIVATED - Interrupt has already been activated
196 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
197 * IRQD_PER_CPU - Interrupt is per cpu
198 * IRQD_AFFINITY_SET - Interrupt affinity was set
199 * IRQD_LEVEL - Interrupt is level triggered
200 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
201 * from suspend
202 * IRQD_MOVE_PCNTXT - Interrupt can be moved in process
203 * context
204 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
205 * IRQD_IRQ_MASKED - Masked state of the interrupt
206 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
207 * IRQD_WAKEUP_ARMED - Wakeup mode armed
208 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
209 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
210 * IRQD_IRQ_STARTED - Startup state of the interrupt
211 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
212 * mask. Applies only to affinity managed irqs.
213 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
214 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
215 * IRQD_CAN_RESERVE - Can use reservation mode
216 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
217 * required
218 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
219 * from actual interrupt context.
220 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
221 * irq_chip::irq_set_affinity() when deactivated.
222 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if
223 * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set.
224 */
225 enum {
226 IRQD_TRIGGER_MASK = 0xf,
227 IRQD_SETAFFINITY_PENDING = (1 << 8),
228 IRQD_ACTIVATED = (1 << 9),
229 IRQD_NO_BALANCING = (1 << 10),
230 IRQD_PER_CPU = (1 << 11),
231 IRQD_AFFINITY_SET = (1 << 12),
232 IRQD_LEVEL = (1 << 13),
233 IRQD_WAKEUP_STATE = (1 << 14),
234 IRQD_MOVE_PCNTXT = (1 << 15),
235 IRQD_IRQ_DISABLED = (1 << 16),
236 IRQD_IRQ_MASKED = (1 << 17),
237 IRQD_IRQ_INPROGRESS = (1 << 18),
238 IRQD_WAKEUP_ARMED = (1 << 19),
239 IRQD_FORWARDED_TO_VCPU = (1 << 20),
240 IRQD_AFFINITY_MANAGED = (1 << 21),
241 IRQD_IRQ_STARTED = (1 << 22),
242 IRQD_MANAGED_SHUTDOWN = (1 << 23),
243 IRQD_SINGLE_TARGET = (1 << 24),
244 IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
245 IRQD_CAN_RESERVE = (1 << 26),
246 IRQD_MSI_NOMASK_QUIRK = (1 << 27),
247 IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28),
248 IRQD_AFFINITY_ON_ACTIVATE = (1 << 29),
249 IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30),
250 };
251
252 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
253
irqd_is_setaffinity_pending(struct irq_data * d)254 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
255 {
256 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
257 }
258
irqd_is_per_cpu(struct irq_data * d)259 static inline bool irqd_is_per_cpu(struct irq_data *d)
260 {
261 return __irqd_to_state(d) & IRQD_PER_CPU;
262 }
263
irqd_can_balance(struct irq_data * d)264 static inline bool irqd_can_balance(struct irq_data *d)
265 {
266 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
267 }
268
irqd_affinity_was_set(struct irq_data * d)269 static inline bool irqd_affinity_was_set(struct irq_data *d)
270 {
271 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
272 }
273
irqd_mark_affinity_was_set(struct irq_data * d)274 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
275 {
276 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
277 }
278
irqd_trigger_type_was_set(struct irq_data * d)279 static inline bool irqd_trigger_type_was_set(struct irq_data *d)
280 {
281 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
282 }
283
irqd_get_trigger_type(struct irq_data * d)284 static inline u32 irqd_get_trigger_type(struct irq_data *d)
285 {
286 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
287 }
288
289 /*
290 * Must only be called inside irq_chip.irq_set_type() functions or
291 * from the DT/ACPI setup code.
292 */
irqd_set_trigger_type(struct irq_data * d,u32 type)293 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
294 {
295 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
296 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
297 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
298 }
299
irqd_is_level_type(struct irq_data * d)300 static inline bool irqd_is_level_type(struct irq_data *d)
301 {
302 return __irqd_to_state(d) & IRQD_LEVEL;
303 }
304
305 /*
306 * Must only be called of irqchip.irq_set_affinity() or low level
307 * hierarchy domain allocation functions.
308 */
irqd_set_single_target(struct irq_data * d)309 static inline void irqd_set_single_target(struct irq_data *d)
310 {
311 __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
312 }
313
irqd_is_single_target(struct irq_data * d)314 static inline bool irqd_is_single_target(struct irq_data *d)
315 {
316 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
317 }
318
irqd_set_handle_enforce_irqctx(struct irq_data * d)319 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
320 {
321 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
322 }
323
irqd_is_handle_enforce_irqctx(struct irq_data * d)324 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
325 {
326 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
327 }
328
irqd_is_enabled_on_suspend(struct irq_data * d)329 static inline bool irqd_is_enabled_on_suspend(struct irq_data *d)
330 {
331 return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND;
332 }
333
irqd_is_wakeup_set(struct irq_data * d)334 static inline bool irqd_is_wakeup_set(struct irq_data *d)
335 {
336 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
337 }
338
irqd_can_move_in_process_context(struct irq_data * d)339 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
340 {
341 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
342 }
343
irqd_irq_disabled(struct irq_data * d)344 static inline bool irqd_irq_disabled(struct irq_data *d)
345 {
346 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
347 }
348
irqd_irq_masked(struct irq_data * d)349 static inline bool irqd_irq_masked(struct irq_data *d)
350 {
351 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
352 }
353
irqd_irq_inprogress(struct irq_data * d)354 static inline bool irqd_irq_inprogress(struct irq_data *d)
355 {
356 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
357 }
358
irqd_is_wakeup_armed(struct irq_data * d)359 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
360 {
361 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
362 }
363
irqd_is_forwarded_to_vcpu(struct irq_data * d)364 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
365 {
366 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
367 }
368
irqd_set_forwarded_to_vcpu(struct irq_data * d)369 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
370 {
371 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
372 }
373
irqd_clr_forwarded_to_vcpu(struct irq_data * d)374 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
375 {
376 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
377 }
378
irqd_affinity_is_managed(struct irq_data * d)379 static inline bool irqd_affinity_is_managed(struct irq_data *d)
380 {
381 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
382 }
383
irqd_is_activated(struct irq_data * d)384 static inline bool irqd_is_activated(struct irq_data *d)
385 {
386 return __irqd_to_state(d) & IRQD_ACTIVATED;
387 }
388
irqd_set_activated(struct irq_data * d)389 static inline void irqd_set_activated(struct irq_data *d)
390 {
391 __irqd_to_state(d) |= IRQD_ACTIVATED;
392 }
393
irqd_clr_activated(struct irq_data * d)394 static inline void irqd_clr_activated(struct irq_data *d)
395 {
396 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
397 }
398
irqd_is_started(struct irq_data * d)399 static inline bool irqd_is_started(struct irq_data *d)
400 {
401 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
402 }
403
irqd_is_managed_and_shutdown(struct irq_data * d)404 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
405 {
406 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
407 }
408
irqd_set_can_reserve(struct irq_data * d)409 static inline void irqd_set_can_reserve(struct irq_data *d)
410 {
411 __irqd_to_state(d) |= IRQD_CAN_RESERVE;
412 }
413
irqd_clr_can_reserve(struct irq_data * d)414 static inline void irqd_clr_can_reserve(struct irq_data *d)
415 {
416 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
417 }
418
irqd_can_reserve(struct irq_data * d)419 static inline bool irqd_can_reserve(struct irq_data *d)
420 {
421 return __irqd_to_state(d) & IRQD_CAN_RESERVE;
422 }
423
irqd_set_msi_nomask_quirk(struct irq_data * d)424 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
425 {
426 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
427 }
428
irqd_clr_msi_nomask_quirk(struct irq_data * d)429 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
430 {
431 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
432 }
433
irqd_msi_nomask_quirk(struct irq_data * d)434 static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
435 {
436 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
437 }
438
irqd_set_affinity_on_activate(struct irq_data * d)439 static inline void irqd_set_affinity_on_activate(struct irq_data *d)
440 {
441 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
442 }
443
irqd_affinity_on_activate(struct irq_data * d)444 static inline bool irqd_affinity_on_activate(struct irq_data *d)
445 {
446 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
447 }
448
449 #undef __irqd_to_state
450
irqd_to_hwirq(struct irq_data * d)451 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
452 {
453 return d->hwirq;
454 }
455
456 /**
457 * struct irq_chip - hardware interrupt chip descriptor
458 *
459 * @parent_device: pointer to parent device for irqchip
460 * @name: name for /proc/interrupts
461 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
462 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
463 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
464 * @irq_disable: disable the interrupt
465 * @irq_ack: start of a new interrupt
466 * @irq_mask: mask an interrupt source
467 * @irq_mask_ack: ack and mask an interrupt source
468 * @irq_unmask: unmask an interrupt source
469 * @irq_eoi: end of interrupt
470 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
471 * argument is true, it tells the driver to
472 * unconditionally apply the affinity setting. Sanity
473 * checks against the supplied affinity mask are not
474 * required. This is used for CPU hotplug where the
475 * target CPU is not yet set in the cpu_online_mask.
476 * @irq_retrigger: resend an IRQ to the CPU
477 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
478 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
479 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
480 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
481 * @irq_cpu_online: configure an interrupt source for a secondary CPU
482 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
483 * @irq_suspend: function called from core code on suspend once per
484 * chip, when one or more interrupts are installed
485 * @irq_resume: function called from core code on resume once per chip,
486 * when one ore more interrupts are installed
487 * @irq_pm_shutdown: function called from core code on shutdown once per chip
488 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
489 * @irq_print_chip: optional to print special chip info in show_interrupts
490 * @irq_request_resources: optional to request resources before calling
491 * any other callback related to this irq
492 * @irq_release_resources: optional to release resources acquired with
493 * irq_request_resources
494 * @irq_compose_msi_msg: optional to compose message content for MSI
495 * @irq_write_msi_msg: optional to write message content for MSI
496 * @irq_get_irqchip_state: return the internal state of an interrupt
497 * @irq_set_irqchip_state: set the internal state of a interrupt
498 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
499 * @ipi_send_single: send a single IPI to destination cpus
500 * @ipi_send_mask: send an IPI to destination cpus in cpumask
501 * @irq_nmi_setup: function called from core code before enabling an NMI
502 * @irq_nmi_teardown: function called from core code after disabling an NMI
503 * @flags: chip specific flags
504 */
505 struct irq_chip {
506 struct device *parent_device;
507 const char *name;
508 unsigned int (*irq_startup)(struct irq_data *data);
509 void (*irq_shutdown)(struct irq_data *data);
510 void (*irq_enable)(struct irq_data *data);
511 void (*irq_disable)(struct irq_data *data);
512
513 void (*irq_ack)(struct irq_data *data);
514 void (*irq_mask)(struct irq_data *data);
515 void (*irq_mask_ack)(struct irq_data *data);
516 void (*irq_unmask)(struct irq_data *data);
517 void (*irq_eoi)(struct irq_data *data);
518
519 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
520 int (*irq_retrigger)(struct irq_data *data);
521 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
522 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
523
524 void (*irq_bus_lock)(struct irq_data *data);
525 void (*irq_bus_sync_unlock)(struct irq_data *data);
526
527 void (*irq_cpu_online)(struct irq_data *data);
528 void (*irq_cpu_offline)(struct irq_data *data);
529
530 void (*irq_suspend)(struct irq_data *data);
531 void (*irq_resume)(struct irq_data *data);
532 void (*irq_pm_shutdown)(struct irq_data *data);
533
534 void (*irq_calc_mask)(struct irq_data *data);
535
536 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
537 int (*irq_request_resources)(struct irq_data *data);
538 void (*irq_release_resources)(struct irq_data *data);
539
540 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
541 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
542
543 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
544 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
545
546 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
547
548 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
549 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
550
551 int (*irq_nmi_setup)(struct irq_data *data);
552 void (*irq_nmi_teardown)(struct irq_data *data);
553
554 unsigned long flags;
555 };
556
557 /*
558 * irq_chip specific flags
559 *
560 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
561 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
562 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
563 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
564 * when irq enabled
565 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
566 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
567 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
568 * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs
569 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
570 * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs
571 * in the suspend path if they are in disabled state
572 * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
573 */
574 enum {
575 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
576 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
577 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
578 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
579 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
580 IRQCHIP_ONESHOT_SAFE = (1 << 5),
581 IRQCHIP_EOI_THREADED = (1 << 6),
582 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
583 IRQCHIP_SUPPORTS_NMI = (1 << 8),
584 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9),
585 IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10),
586 };
587
588 #include <linux/irqdesc.h>
589
590 /*
591 * Pick up the arch-dependent methods:
592 */
593 #include <asm/hw_irq.h>
594
595 #ifndef NR_IRQS_LEGACY
596 # define NR_IRQS_LEGACY 0
597 #endif
598
599 #ifndef ARCH_IRQ_INIT_FLAGS
600 # define ARCH_IRQ_INIT_FLAGS 0
601 #endif
602
603 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
604
605 struct irqaction;
606 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
607 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
608
609 extern void irq_cpu_online(void);
610 extern void irq_cpu_offline(void);
611 extern int irq_set_affinity_locked(struct irq_data *data,
612 const struct cpumask *cpumask, bool force);
613 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
614
615 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
616 extern void irq_migrate_all_off_this_cpu(void);
617 extern int irq_affinity_online_cpu(unsigned int cpu);
618 #else
619 # define irq_affinity_online_cpu NULL
620 #endif
621
622 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
623 void __irq_move_irq(struct irq_data *data);
irq_move_irq(struct irq_data * data)624 static inline void irq_move_irq(struct irq_data *data)
625 {
626 if (unlikely(irqd_is_setaffinity_pending(data)))
627 __irq_move_irq(data);
628 }
629 void irq_move_masked_irq(struct irq_data *data);
630 void irq_force_complete_move(struct irq_desc *desc);
631 #else
irq_move_irq(struct irq_data * data)632 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)633 static inline void irq_move_masked_irq(struct irq_data *data) { }
irq_force_complete_move(struct irq_desc * desc)634 static inline void irq_force_complete_move(struct irq_desc *desc) { }
635 #endif
636
637 extern int no_irq_affinity;
638
639 #ifdef CONFIG_HARDIRQS_SW_RESEND
640 int irq_set_parent(int irq, int parent_irq);
641 #else
irq_set_parent(int irq,int parent_irq)642 static inline int irq_set_parent(int irq, int parent_irq)
643 {
644 return 0;
645 }
646 #endif
647
648 /*
649 * Built-in IRQ handlers for various IRQ types,
650 * callable via desc->handle_irq()
651 */
652 extern void handle_level_irq(struct irq_desc *desc);
653 extern void handle_fasteoi_irq(struct irq_desc *desc);
654 extern void handle_percpu_devid_fasteoi_ipi(struct irq_desc *desc);
655 extern void handle_edge_irq(struct irq_desc *desc);
656 extern void handle_edge_eoi_irq(struct irq_desc *desc);
657 extern void handle_simple_irq(struct irq_desc *desc);
658 extern void handle_untracked_irq(struct irq_desc *desc);
659 extern void handle_percpu_irq(struct irq_desc *desc);
660 extern void handle_percpu_devid_irq(struct irq_desc *desc);
661 extern void handle_bad_irq(struct irq_desc *desc);
662 extern void handle_nested_irq(unsigned int irq);
663
664 extern void handle_fasteoi_nmi(struct irq_desc *desc);
665 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
666
667 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
668 extern int irq_chip_pm_get(struct irq_data *data);
669 extern int irq_chip_pm_put(struct irq_data *data);
670 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
671 extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
672 extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
673 extern int irq_chip_set_parent_state(struct irq_data *data,
674 enum irqchip_irq_state which,
675 bool val);
676 extern int irq_chip_get_parent_state(struct irq_data *data,
677 enum irqchip_irq_state which,
678 bool *state);
679 extern void irq_chip_enable_parent(struct irq_data *data);
680 extern void irq_chip_disable_parent(struct irq_data *data);
681 extern void irq_chip_ack_parent(struct irq_data *data);
682 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
683 extern void irq_chip_mask_parent(struct irq_data *data);
684 extern void irq_chip_mask_ack_parent(struct irq_data *data);
685 extern void irq_chip_unmask_parent(struct irq_data *data);
686 extern void irq_chip_eoi_parent(struct irq_data *data);
687 extern int irq_chip_set_affinity_parent(struct irq_data *data,
688 const struct cpumask *dest,
689 bool force);
690 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
691 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
692 void *vcpu_info);
693 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
694 extern int irq_chip_request_resources_parent(struct irq_data *data);
695 extern void irq_chip_release_resources_parent(struct irq_data *data);
696 #endif
697
698 /* Handling of unhandled and spurious interrupts: */
699 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
700
701
702 /* Enable/disable irq debugging output: */
703 extern int noirqdebug_setup(char *str);
704
705 /* Checks whether the interrupt can be requested by request_irq(): */
706 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
707
708 /* Dummy irq-chip implementations: */
709 extern struct irq_chip no_irq_chip;
710 extern struct irq_chip dummy_irq_chip;
711
712 extern void
713 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
714 irq_flow_handler_t handle, const char *name);
715
irq_set_chip_and_handler(unsigned int irq,struct irq_chip * chip,irq_flow_handler_t handle)716 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
717 irq_flow_handler_t handle)
718 {
719 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
720 }
721
722 extern int irq_set_percpu_devid(unsigned int irq);
723 extern int irq_set_percpu_devid_partition(unsigned int irq,
724 const struct cpumask *affinity);
725 extern int irq_get_percpu_devid_partition(unsigned int irq,
726 struct cpumask *affinity);
727
728 extern void
729 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
730 const char *name);
731
732 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)733 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
734 {
735 __irq_set_handler(irq, handle, 0, NULL);
736 }
737
738 /*
739 * Set a highlevel chained flow handler for a given IRQ.
740 * (a chained handler is automatically enabled and set to
741 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
742 */
743 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)744 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
745 {
746 __irq_set_handler(irq, handle, 1, NULL);
747 }
748
749 /*
750 * Set a highlevel chained flow handler and its data for a given IRQ.
751 * (a chained handler is automatically enabled and set to
752 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
753 */
754 void
755 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
756 void *data);
757
758 void __irq_modify_status(unsigned int irq, unsigned long clr,
759 unsigned long set, unsigned long mask);
760
761 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
762
irq_set_status_flags(unsigned int irq,unsigned long set)763 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
764 {
765 irq_modify_status(irq, 0, set);
766 }
767
irq_clear_status_flags(unsigned int irq,unsigned long clr)768 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
769 {
770 irq_modify_status(irq, clr, 0);
771 }
772
irq_set_noprobe(unsigned int irq)773 static inline void irq_set_noprobe(unsigned int irq)
774 {
775 irq_modify_status(irq, 0, IRQ_NOPROBE);
776 }
777
irq_set_probe(unsigned int irq)778 static inline void irq_set_probe(unsigned int irq)
779 {
780 irq_modify_status(irq, IRQ_NOPROBE, 0);
781 }
782
irq_set_nothread(unsigned int irq)783 static inline void irq_set_nothread(unsigned int irq)
784 {
785 irq_modify_status(irq, 0, IRQ_NOTHREAD);
786 }
787
irq_set_thread(unsigned int irq)788 static inline void irq_set_thread(unsigned int irq)
789 {
790 irq_modify_status(irq, IRQ_NOTHREAD, 0);
791 }
792
irq_set_nested_thread(unsigned int irq,bool nest)793 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
794 {
795 if (nest)
796 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
797 else
798 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
799 }
800
irq_set_percpu_devid_flags(unsigned int irq)801 static inline void irq_set_percpu_devid_flags(unsigned int irq)
802 {
803 irq_set_status_flags(irq,
804 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
805 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
806 }
807
808 /* Set/get chip/data for an IRQ: */
809 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
810 extern int irq_set_handler_data(unsigned int irq, void *data);
811 extern int irq_set_chip_data(unsigned int irq, void *data);
812 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
813 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
814 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
815 struct msi_desc *entry);
816 extern struct irq_data *irq_get_irq_data(unsigned int irq);
817
irq_get_chip(unsigned int irq)818 static inline struct irq_chip *irq_get_chip(unsigned int irq)
819 {
820 struct irq_data *d = irq_get_irq_data(irq);
821 return d ? d->chip : NULL;
822 }
823
irq_data_get_irq_chip(struct irq_data * d)824 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
825 {
826 return d->chip;
827 }
828
irq_get_chip_data(unsigned int irq)829 static inline void *irq_get_chip_data(unsigned int irq)
830 {
831 struct irq_data *d = irq_get_irq_data(irq);
832 return d ? d->chip_data : NULL;
833 }
834
irq_data_get_irq_chip_data(struct irq_data * d)835 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
836 {
837 return d->chip_data;
838 }
839
irq_get_handler_data(unsigned int irq)840 static inline void *irq_get_handler_data(unsigned int irq)
841 {
842 struct irq_data *d = irq_get_irq_data(irq);
843 return d ? d->common->handler_data : NULL;
844 }
845
irq_data_get_irq_handler_data(struct irq_data * d)846 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
847 {
848 return d->common->handler_data;
849 }
850
irq_get_msi_desc(unsigned int irq)851 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
852 {
853 struct irq_data *d = irq_get_irq_data(irq);
854 return d ? d->common->msi_desc : NULL;
855 }
856
irq_data_get_msi_desc(struct irq_data * d)857 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
858 {
859 return d->common->msi_desc;
860 }
861
irq_get_trigger_type(unsigned int irq)862 static inline u32 irq_get_trigger_type(unsigned int irq)
863 {
864 struct irq_data *d = irq_get_irq_data(irq);
865 return d ? irqd_get_trigger_type(d) : 0;
866 }
867
irq_common_data_get_node(struct irq_common_data * d)868 static inline int irq_common_data_get_node(struct irq_common_data *d)
869 {
870 #ifdef CONFIG_NUMA
871 return d->node;
872 #else
873 return 0;
874 #endif
875 }
876
irq_data_get_node(struct irq_data * d)877 static inline int irq_data_get_node(struct irq_data *d)
878 {
879 return irq_common_data_get_node(d->common);
880 }
881
irq_get_affinity_mask(int irq)882 static inline struct cpumask *irq_get_affinity_mask(int irq)
883 {
884 struct irq_data *d = irq_get_irq_data(irq);
885
886 return d ? d->common->affinity : NULL;
887 }
888
irq_data_get_affinity_mask(struct irq_data * d)889 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
890 {
891 return d->common->affinity;
892 }
893
894 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
895 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)896 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
897 {
898 return d->common->effective_affinity;
899 }
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)900 static inline void irq_data_update_effective_affinity(struct irq_data *d,
901 const struct cpumask *m)
902 {
903 cpumask_copy(d->common->effective_affinity, m);
904 }
905 #else
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)906 static inline void irq_data_update_effective_affinity(struct irq_data *d,
907 const struct cpumask *m)
908 {
909 }
910 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)911 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
912 {
913 return d->common->affinity;
914 }
915 #endif
916
917 unsigned int arch_dynirq_lower_bound(unsigned int from);
918
919 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
920 struct module *owner,
921 const struct irq_affinity_desc *affinity);
922
923 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
924 unsigned int cnt, int node, struct module *owner,
925 const struct irq_affinity_desc *affinity);
926
927 /* use macros to avoid needing export.h for THIS_MODULE */
928 #define irq_alloc_descs(irq, from, cnt, node) \
929 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
930
931 #define irq_alloc_desc(node) \
932 irq_alloc_descs(-1, 1, 1, node)
933
934 #define irq_alloc_desc_at(at, node) \
935 irq_alloc_descs(at, at, 1, node)
936
937 #define irq_alloc_desc_from(from, node) \
938 irq_alloc_descs(-1, from, 1, node)
939
940 #define irq_alloc_descs_from(from, cnt, node) \
941 irq_alloc_descs(-1, from, cnt, node)
942
943 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
944 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
945
946 #define devm_irq_alloc_desc(dev, node) \
947 devm_irq_alloc_descs(dev, -1, 1, 1, node)
948
949 #define devm_irq_alloc_desc_at(dev, at, node) \
950 devm_irq_alloc_descs(dev, at, at, 1, node)
951
952 #define devm_irq_alloc_desc_from(dev, from, node) \
953 devm_irq_alloc_descs(dev, -1, from, 1, node)
954
955 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
956 devm_irq_alloc_descs(dev, -1, from, cnt, node)
957
958 void irq_free_descs(unsigned int irq, unsigned int cnt);
irq_free_desc(unsigned int irq)959 static inline void irq_free_desc(unsigned int irq)
960 {
961 irq_free_descs(irq, 1);
962 }
963
964 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
965 unsigned int irq_alloc_hwirqs(int cnt, int node);
irq_alloc_hwirq(int node)966 static inline unsigned int irq_alloc_hwirq(int node)
967 {
968 return irq_alloc_hwirqs(1, node);
969 }
970 void irq_free_hwirqs(unsigned int from, int cnt);
irq_free_hwirq(unsigned int irq)971 static inline void irq_free_hwirq(unsigned int irq)
972 {
973 return irq_free_hwirqs(irq, 1);
974 }
975 int arch_setup_hwirq(unsigned int irq, int node);
976 void arch_teardown_hwirq(unsigned int irq);
977 #endif
978
979 #ifdef CONFIG_GENERIC_IRQ_LEGACY
980 void irq_init_desc(unsigned int irq);
981 #endif
982
983 /**
984 * struct irq_chip_regs - register offsets for struct irq_gci
985 * @enable: Enable register offset to reg_base
986 * @disable: Disable register offset to reg_base
987 * @mask: Mask register offset to reg_base
988 * @ack: Ack register offset to reg_base
989 * @eoi: Eoi register offset to reg_base
990 * @type: Type configuration register offset to reg_base
991 * @polarity: Polarity configuration register offset to reg_base
992 */
993 struct irq_chip_regs {
994 unsigned long enable;
995 unsigned long disable;
996 unsigned long mask;
997 unsigned long ack;
998 unsigned long eoi;
999 unsigned long type;
1000 unsigned long polarity;
1001 };
1002
1003 /**
1004 * struct irq_chip_type - Generic interrupt chip instance for a flow type
1005 * @chip: The real interrupt chip which provides the callbacks
1006 * @regs: Register offsets for this chip
1007 * @handler: Flow handler associated with this chip
1008 * @type: Chip can handle these flow types
1009 * @mask_cache_priv: Cached mask register private to the chip type
1010 * @mask_cache: Pointer to cached mask register
1011 *
1012 * A irq_generic_chip can have several instances of irq_chip_type when
1013 * it requires different functions and register offsets for different
1014 * flow types.
1015 */
1016 struct irq_chip_type {
1017 struct irq_chip chip;
1018 struct irq_chip_regs regs;
1019 irq_flow_handler_t handler;
1020 u32 type;
1021 u32 mask_cache_priv;
1022 u32 *mask_cache;
1023 };
1024
1025 /**
1026 * struct irq_chip_generic - Generic irq chip data structure
1027 * @lock: Lock to protect register and cache data access
1028 * @reg_base: Register base address (virtual)
1029 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
1030 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
1031 * @suspend: Function called from core code on suspend once per
1032 * chip; can be useful instead of irq_chip::suspend to
1033 * handle chip details even when no interrupts are in use
1034 * @resume: Function called from core code on resume once per chip;
1035 * can be useful instead of irq_chip::suspend to handle
1036 * chip details even when no interrupts are in use
1037 * @irq_base: Interrupt base nr for this chip
1038 * @irq_cnt: Number of interrupts handled by this chip
1039 * @mask_cache: Cached mask register shared between all chip types
1040 * @type_cache: Cached type register
1041 * @polarity_cache: Cached polarity register
1042 * @wake_enabled: Interrupt can wakeup from suspend
1043 * @wake_active: Interrupt is marked as an wakeup from suspend source
1044 * @num_ct: Number of available irq_chip_type instances (usually 1)
1045 * @private: Private data for non generic chip callbacks
1046 * @installed: bitfield to denote installed interrupts
1047 * @unused: bitfield to denote unused interrupts
1048 * @domain: irq domain pointer
1049 * @list: List head for keeping track of instances
1050 * @chip_types: Array of interrupt irq_chip_types
1051 *
1052 * Note, that irq_chip_generic can have multiple irq_chip_type
1053 * implementations which can be associated to a particular irq line of
1054 * an irq_chip_generic instance. That allows to share and protect
1055 * state in an irq_chip_generic instance when we need to implement
1056 * different flow mechanisms (level/edge) for it.
1057 */
1058 struct irq_chip_generic {
1059 raw_spinlock_t lock;
1060 void __iomem *reg_base;
1061 u32 (*reg_readl)(void __iomem *addr);
1062 void (*reg_writel)(u32 val, void __iomem *addr);
1063 void (*suspend)(struct irq_chip_generic *gc);
1064 void (*resume)(struct irq_chip_generic *gc);
1065 unsigned int irq_base;
1066 unsigned int irq_cnt;
1067 u32 mask_cache;
1068 u32 type_cache;
1069 u32 polarity_cache;
1070 u32 wake_enabled;
1071 u32 wake_active;
1072 unsigned int num_ct;
1073 void *private;
1074 unsigned long installed;
1075 unsigned long unused;
1076 struct irq_domain *domain;
1077 struct list_head list;
1078 struct irq_chip_type chip_types[];
1079 };
1080
1081 /**
1082 * enum irq_gc_flags - Initialization flags for generic irq chips
1083 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1084 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1085 * irq chips which need to call irq_set_wake() on
1086 * the parent irq. Usually GPIO implementations
1087 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1088 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1089 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1090 */
1091 enum irq_gc_flags {
1092 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1093 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
1094 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
1095 IRQ_GC_NO_MASK = 1 << 3,
1096 IRQ_GC_BE_IO = 1 << 4,
1097 };
1098
1099 /*
1100 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1101 * @irqs_per_chip: Number of interrupts per chip
1102 * @num_chips: Number of chips
1103 * @irq_flags_to_set: IRQ* flags to set on irq setup
1104 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1105 * @gc_flags: Generic chip specific setup flags
1106 * @gc: Array of pointers to generic interrupt chips
1107 */
1108 struct irq_domain_chip_generic {
1109 unsigned int irqs_per_chip;
1110 unsigned int num_chips;
1111 unsigned int irq_flags_to_clear;
1112 unsigned int irq_flags_to_set;
1113 enum irq_gc_flags gc_flags;
1114 struct irq_chip_generic *gc[];
1115 };
1116
1117 /* Generic chip callback functions */
1118 void irq_gc_noop(struct irq_data *d);
1119 void irq_gc_mask_disable_reg(struct irq_data *d);
1120 void irq_gc_mask_set_bit(struct irq_data *d);
1121 void irq_gc_mask_clr_bit(struct irq_data *d);
1122 void irq_gc_unmask_enable_reg(struct irq_data *d);
1123 void irq_gc_ack_set_bit(struct irq_data *d);
1124 void irq_gc_ack_clr_bit(struct irq_data *d);
1125 void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1126 void irq_gc_eoi(struct irq_data *d);
1127 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1128
1129 /* Setup functions for irq_chip_generic */
1130 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1131 irq_hw_number_t hw_irq);
1132 struct irq_chip_generic *
1133 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1134 void __iomem *reg_base, irq_flow_handler_t handler);
1135 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1136 enum irq_gc_flags flags, unsigned int clr,
1137 unsigned int set);
1138 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1139 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1140 unsigned int clr, unsigned int set);
1141
1142 struct irq_chip_generic *
1143 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1144 unsigned int irq_base, void __iomem *reg_base,
1145 irq_flow_handler_t handler);
1146 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1147 u32 msk, enum irq_gc_flags flags,
1148 unsigned int clr, unsigned int set);
1149
1150 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1151
1152 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1153 int num_ct, const char *name,
1154 irq_flow_handler_t handler,
1155 unsigned int clr, unsigned int set,
1156 enum irq_gc_flags flags);
1157
1158 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1159 handler, clr, set, flags) \
1160 ({ \
1161 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1162 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1163 handler, clr, set, flags); \
1164 })
1165
irq_free_generic_chip(struct irq_chip_generic * gc)1166 static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1167 {
1168 kfree(gc);
1169 }
1170
irq_destroy_generic_chip(struct irq_chip_generic * gc,u32 msk,unsigned int clr,unsigned int set)1171 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1172 u32 msk, unsigned int clr,
1173 unsigned int set)
1174 {
1175 irq_remove_generic_chip(gc, msk, clr, set);
1176 irq_free_generic_chip(gc);
1177 }
1178
irq_data_get_chip_type(struct irq_data * d)1179 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1180 {
1181 return container_of(d->chip, struct irq_chip_type, chip);
1182 }
1183
1184 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1185
1186 #ifdef CONFIG_SMP
irq_gc_lock(struct irq_chip_generic * gc)1187 static inline void irq_gc_lock(struct irq_chip_generic *gc)
1188 {
1189 raw_spin_lock(&gc->lock);
1190 }
1191
irq_gc_unlock(struct irq_chip_generic * gc)1192 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1193 {
1194 raw_spin_unlock(&gc->lock);
1195 }
1196 #else
irq_gc_lock(struct irq_chip_generic * gc)1197 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
irq_gc_unlock(struct irq_chip_generic * gc)1198 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1199 #endif
1200
1201 /*
1202 * The irqsave variants are for usage in non interrupt code. Do not use
1203 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1204 */
1205 #define irq_gc_lock_irqsave(gc, flags) \
1206 raw_spin_lock_irqsave(&(gc)->lock, flags)
1207
1208 #define irq_gc_unlock_irqrestore(gc, flags) \
1209 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1210
irq_reg_writel(struct irq_chip_generic * gc,u32 val,int reg_offset)1211 static inline void irq_reg_writel(struct irq_chip_generic *gc,
1212 u32 val, int reg_offset)
1213 {
1214 if (gc->reg_writel)
1215 gc->reg_writel(val, gc->reg_base + reg_offset);
1216 else
1217 writel(val, gc->reg_base + reg_offset);
1218 }
1219
irq_reg_readl(struct irq_chip_generic * gc,int reg_offset)1220 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1221 int reg_offset)
1222 {
1223 if (gc->reg_readl)
1224 return gc->reg_readl(gc->reg_base + reg_offset);
1225 else
1226 return readl(gc->reg_base + reg_offset);
1227 }
1228
1229 struct irq_matrix;
1230 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1231 unsigned int alloc_start,
1232 unsigned int alloc_end);
1233 void irq_matrix_online(struct irq_matrix *m);
1234 void irq_matrix_offline(struct irq_matrix *m);
1235 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1236 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1237 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1238 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1239 unsigned int *mapped_cpu);
1240 void irq_matrix_reserve(struct irq_matrix *m);
1241 void irq_matrix_remove_reserved(struct irq_matrix *m);
1242 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1243 bool reserved, unsigned int *mapped_cpu);
1244 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1245 unsigned int bit, bool managed);
1246 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1247 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1248 unsigned int irq_matrix_allocated(struct irq_matrix *m);
1249 unsigned int irq_matrix_reserved(struct irq_matrix *m);
1250 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1251
1252 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1253 #define INVALID_HWIRQ (~0UL)
1254 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1255 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1256 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1257 int ipi_send_single(unsigned int virq, unsigned int cpu);
1258 int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1259
1260 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1261 /*
1262 * Registers a generic IRQ handling function as the top-level IRQ handler in
1263 * the system, which is generally the first C code called from an assembly
1264 * architecture-specific interrupt handler.
1265 *
1266 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1267 * registered.
1268 */
1269 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1270
1271 /*
1272 * Allows interrupt handlers to find the irqchip that's been registered as the
1273 * top-level IRQ handler.
1274 */
1275 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1276 #else
1277 #define set_handle_irq(handle_irq) \
1278 do { \
1279 (void)handle_irq; \
1280 WARN_ON(1); \
1281 } while (0)
1282 #endif
1283
1284 #endif /* _LINUX_IRQ_H */
1285