1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51
52 #include <linux/mlx5/device.h>
53 #include <linux/mlx5/doorbell.h>
54 #include <linux/mlx5/eq.h>
55 #include <linux/timecounter.h>
56 #include <linux/ptp_clock_kernel.h>
57 #include <net/devlink.h>
58
59 #define MLX5_ADEV_NAME "mlx5_core"
60
61 enum {
62 MLX5_BOARD_ID_LEN = 64,
63 };
64
65 enum {
66 /* one minute for the sake of bringup. Generally, commands must always
67 * complete and we may need to increase this timeout value
68 */
69 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
70 MLX5_CMD_WQ_MAX_NAME = 32,
71 };
72
73 enum {
74 CMD_OWNER_SW = 0x0,
75 CMD_OWNER_HW = 0x1,
76 CMD_STATUS_SUCCESS = 0,
77 };
78
79 enum mlx5_sqp_t {
80 MLX5_SQP_SMI = 0,
81 MLX5_SQP_GSI = 1,
82 MLX5_SQP_IEEE_1588 = 2,
83 MLX5_SQP_SNIFFER = 3,
84 MLX5_SQP_SYNC_UMR = 4,
85 };
86
87 enum {
88 MLX5_MAX_PORTS = 2,
89 };
90
91 enum {
92 MLX5_ATOMIC_MODE_OFFSET = 16,
93 MLX5_ATOMIC_MODE_IB_COMP = 1,
94 MLX5_ATOMIC_MODE_CX = 2,
95 MLX5_ATOMIC_MODE_8B = 3,
96 MLX5_ATOMIC_MODE_16B = 4,
97 MLX5_ATOMIC_MODE_32B = 5,
98 MLX5_ATOMIC_MODE_64B = 6,
99 MLX5_ATOMIC_MODE_128B = 7,
100 MLX5_ATOMIC_MODE_256B = 8,
101 };
102
103 enum {
104 MLX5_REG_QPTS = 0x4002,
105 MLX5_REG_QETCR = 0x4005,
106 MLX5_REG_QTCT = 0x400a,
107 MLX5_REG_QPDPM = 0x4013,
108 MLX5_REG_QCAM = 0x4019,
109 MLX5_REG_DCBX_PARAM = 0x4020,
110 MLX5_REG_DCBX_APP = 0x4021,
111 MLX5_REG_FPGA_CAP = 0x4022,
112 MLX5_REG_FPGA_CTRL = 0x4023,
113 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
114 MLX5_REG_CORE_DUMP = 0x402e,
115 MLX5_REG_PCAP = 0x5001,
116 MLX5_REG_PMTU = 0x5003,
117 MLX5_REG_PTYS = 0x5004,
118 MLX5_REG_PAOS = 0x5006,
119 MLX5_REG_PFCC = 0x5007,
120 MLX5_REG_PPCNT = 0x5008,
121 MLX5_REG_PPTB = 0x500b,
122 MLX5_REG_PBMC = 0x500c,
123 MLX5_REG_PMAOS = 0x5012,
124 MLX5_REG_PUDE = 0x5009,
125 MLX5_REG_PMPE = 0x5010,
126 MLX5_REG_PELC = 0x500e,
127 MLX5_REG_PVLC = 0x500f,
128 MLX5_REG_PCMR = 0x5041,
129 MLX5_REG_PMLP = 0x5002,
130 MLX5_REG_PPLM = 0x5023,
131 MLX5_REG_PCAM = 0x507f,
132 MLX5_REG_NODE_DESC = 0x6001,
133 MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 MLX5_REG_MCIA = 0x9014,
135 MLX5_REG_MFRL = 0x9028,
136 MLX5_REG_MLCR = 0x902b,
137 MLX5_REG_MTRC_CAP = 0x9040,
138 MLX5_REG_MTRC_CONF = 0x9041,
139 MLX5_REG_MTRC_STDB = 0x9042,
140 MLX5_REG_MTRC_CTRL = 0x9043,
141 MLX5_REG_MPEIN = 0x9050,
142 MLX5_REG_MPCNT = 0x9051,
143 MLX5_REG_MTPPS = 0x9053,
144 MLX5_REG_MTPPSE = 0x9054,
145 MLX5_REG_MPEGC = 0x9056,
146 MLX5_REG_MCQS = 0x9060,
147 MLX5_REG_MCQI = 0x9061,
148 MLX5_REG_MCC = 0x9062,
149 MLX5_REG_MCDA = 0x9063,
150 MLX5_REG_MCAM = 0x907f,
151 MLX5_REG_MIRC = 0x9162,
152 MLX5_REG_SBCAM = 0xB01F,
153 MLX5_REG_RESOURCE_DUMP = 0xC000,
154 };
155
156 enum mlx5_qpts_trust_state {
157 MLX5_QPTS_TRUST_PCP = 1,
158 MLX5_QPTS_TRUST_DSCP = 2,
159 };
160
161 enum mlx5_dcbx_oper_mode {
162 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
163 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
164 };
165
166 enum {
167 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
168 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
169 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
170 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
171 };
172
173 enum mlx5_page_fault_resume_flags {
174 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
175 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
176 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
177 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
178 };
179
180 enum dbg_rsc_type {
181 MLX5_DBG_RSC_QP,
182 MLX5_DBG_RSC_EQ,
183 MLX5_DBG_RSC_CQ,
184 };
185
186 enum port_state_policy {
187 MLX5_POLICY_DOWN = 0,
188 MLX5_POLICY_UP = 1,
189 MLX5_POLICY_FOLLOW = 2,
190 MLX5_POLICY_INVALID = 0xffffffff
191 };
192
193 enum mlx5_coredev_type {
194 MLX5_COREDEV_PF,
195 MLX5_COREDEV_VF
196 };
197
198 struct mlx5_field_desc {
199 int i;
200 };
201
202 struct mlx5_rsc_debug {
203 struct mlx5_core_dev *dev;
204 void *object;
205 enum dbg_rsc_type type;
206 struct dentry *root;
207 struct mlx5_field_desc fields[];
208 };
209
210 enum mlx5_dev_event {
211 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
212 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
213 };
214
215 enum mlx5_port_status {
216 MLX5_PORT_UP = 1,
217 MLX5_PORT_DOWN = 2,
218 };
219
220 enum mlx5_cmdif_state {
221 MLX5_CMDIF_STATE_UNINITIALIZED,
222 MLX5_CMDIF_STATE_UP,
223 MLX5_CMDIF_STATE_DOWN,
224 };
225
226 struct mlx5_cmd_first {
227 __be32 data[4];
228 };
229
230 struct mlx5_cmd_msg {
231 struct list_head list;
232 struct cmd_msg_cache *parent;
233 u32 len;
234 struct mlx5_cmd_first first;
235 struct mlx5_cmd_mailbox *next;
236 };
237
238 struct mlx5_cmd_debug {
239 struct dentry *dbg_root;
240 void *in_msg;
241 void *out_msg;
242 u8 status;
243 u16 inlen;
244 u16 outlen;
245 };
246
247 struct cmd_msg_cache {
248 /* protect block chain allocations
249 */
250 spinlock_t lock;
251 struct list_head head;
252 unsigned int max_inbox_size;
253 unsigned int num_ent;
254 };
255
256 enum {
257 MLX5_NUM_COMMAND_CACHES = 5,
258 };
259
260 struct mlx5_cmd_stats {
261 u64 sum;
262 u64 n;
263 struct dentry *root;
264 /* protect command average calculations */
265 spinlock_t lock;
266 };
267
268 struct mlx5_cmd {
269 struct mlx5_nb nb;
270
271 enum mlx5_cmdif_state state;
272 void *cmd_alloc_buf;
273 dma_addr_t alloc_dma;
274 int alloc_size;
275 void *cmd_buf;
276 dma_addr_t dma;
277 u16 cmdif_rev;
278 u8 log_sz;
279 u8 log_stride;
280 int max_reg_cmds;
281 int events;
282 u32 __iomem *vector;
283
284 /* protect command queue allocations
285 */
286 spinlock_t alloc_lock;
287
288 /* protect token allocations
289 */
290 spinlock_t token_lock;
291 u8 token;
292 unsigned long bitmask;
293 char wq_name[MLX5_CMD_WQ_MAX_NAME];
294 struct workqueue_struct *wq;
295 struct semaphore sem;
296 struct semaphore pages_sem;
297 int mode;
298 u16 allowed_opcode;
299 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
300 struct dma_pool *pool;
301 struct mlx5_cmd_debug dbg;
302 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
303 int checksum_disabled;
304 struct mlx5_cmd_stats *stats;
305 };
306
307 struct mlx5_port_caps {
308 int gid_table_len;
309 int pkey_table_len;
310 u8 ext_port_cap;
311 bool has_smi;
312 };
313
314 struct mlx5_cmd_mailbox {
315 void *buf;
316 dma_addr_t dma;
317 struct mlx5_cmd_mailbox *next;
318 };
319
320 struct mlx5_buf_list {
321 void *buf;
322 dma_addr_t map;
323 };
324
325 struct mlx5_frag_buf {
326 struct mlx5_buf_list *frags;
327 int npages;
328 int size;
329 u8 page_shift;
330 };
331
332 struct mlx5_frag_buf_ctrl {
333 struct mlx5_buf_list *frags;
334 u32 sz_m1;
335 u16 frag_sz_m1;
336 u16 strides_offset;
337 u8 log_sz;
338 u8 log_stride;
339 u8 log_frag_strides;
340 };
341
342 struct mlx5_core_psv {
343 u32 psv_idx;
344 struct psv_layout {
345 u32 pd;
346 u16 syndrome;
347 u16 reserved;
348 u16 bg;
349 u16 app_tag;
350 u32 ref_tag;
351 } psv;
352 };
353
354 struct mlx5_core_sig_ctx {
355 struct mlx5_core_psv psv_memory;
356 struct mlx5_core_psv psv_wire;
357 struct ib_sig_err err_item;
358 bool sig_status_checked;
359 bool sig_err_exists;
360 u32 sigerr_count;
361 };
362
363 enum {
364 MLX5_MKEY_MR = 1,
365 MLX5_MKEY_MW,
366 MLX5_MKEY_INDIRECT_DEVX,
367 };
368
369 struct mlx5_core_mkey {
370 u64 iova;
371 u64 size;
372 u32 key;
373 u32 pd;
374 u32 type;
375 };
376
377 #define MLX5_24BIT_MASK ((1 << 24) - 1)
378
379 enum mlx5_res_type {
380 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
381 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
382 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
383 MLX5_RES_SRQ = 3,
384 MLX5_RES_XSRQ = 4,
385 MLX5_RES_XRQ = 5,
386 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
387 };
388
389 struct mlx5_core_rsc_common {
390 enum mlx5_res_type res;
391 refcount_t refcount;
392 struct completion free;
393 };
394
395 struct mlx5_uars_page {
396 void __iomem *map;
397 bool wc;
398 u32 index;
399 struct list_head list;
400 unsigned int bfregs;
401 unsigned long *reg_bitmap; /* for non fast path bf regs */
402 unsigned long *fp_bitmap;
403 unsigned int reg_avail;
404 unsigned int fp_avail;
405 struct kref ref_count;
406 struct mlx5_core_dev *mdev;
407 };
408
409 struct mlx5_bfreg_head {
410 /* protect blue flame registers allocations */
411 struct mutex lock;
412 struct list_head list;
413 };
414
415 struct mlx5_bfreg_data {
416 struct mlx5_bfreg_head reg_head;
417 struct mlx5_bfreg_head wc_head;
418 };
419
420 struct mlx5_sq_bfreg {
421 void __iomem *map;
422 struct mlx5_uars_page *up;
423 bool wc;
424 u32 index;
425 unsigned int offset;
426 };
427
428 struct mlx5_core_health {
429 struct health_buffer __iomem *health;
430 __be32 __iomem *health_counter;
431 struct timer_list timer;
432 u32 prev;
433 int miss_counter;
434 u8 synd;
435 u32 fatal_error;
436 u32 crdump_size;
437 /* wq spinlock to synchronize draining */
438 spinlock_t wq_lock;
439 struct workqueue_struct *wq;
440 unsigned long flags;
441 struct work_struct fatal_report_work;
442 struct work_struct report_work;
443 struct delayed_work recover_work;
444 struct devlink_health_reporter *fw_reporter;
445 struct devlink_health_reporter *fw_fatal_reporter;
446 };
447
448 struct mlx5_qp_table {
449 struct notifier_block nb;
450
451 /* protect radix tree
452 */
453 spinlock_t lock;
454 struct radix_tree_root tree;
455 };
456
457 struct mlx5_vf_context {
458 int enabled;
459 u64 port_guid;
460 u64 node_guid;
461 /* Valid bits are used to validate administrative guid only.
462 * Enabled after ndo_set_vf_guid
463 */
464 u8 port_guid_valid:1;
465 u8 node_guid_valid:1;
466 enum port_state_policy policy;
467 };
468
469 struct mlx5_core_sriov {
470 struct mlx5_vf_context *vfs_ctx;
471 int num_vfs;
472 u16 max_vfs;
473 };
474
475 struct mlx5_fc_pool {
476 struct mlx5_core_dev *dev;
477 struct mutex pool_lock; /* protects pool lists */
478 struct list_head fully_used;
479 struct list_head partially_used;
480 struct list_head unused;
481 int available_fcs;
482 int used_fcs;
483 int threshold;
484 };
485
486 struct mlx5_fc_stats {
487 spinlock_t counters_idr_lock; /* protects counters_idr */
488 struct idr counters_idr;
489 struct list_head counters;
490 struct llist_head addlist;
491 struct llist_head dellist;
492
493 struct workqueue_struct *wq;
494 struct delayed_work work;
495 unsigned long next_query;
496 unsigned long sampling_interval; /* jiffies */
497 u32 *bulk_query_out;
498 struct mlx5_fc_pool fc_pool;
499 };
500
501 struct mlx5_events;
502 struct mlx5_mpfs;
503 struct mlx5_eswitch;
504 struct mlx5_lag;
505 struct mlx5_devcom;
506 struct mlx5_fw_reset;
507 struct mlx5_eq_table;
508 struct mlx5_irq_table;
509
510 struct mlx5_rate_limit {
511 u32 rate;
512 u32 max_burst_sz;
513 u16 typical_pkt_sz;
514 };
515
516 struct mlx5_rl_entry {
517 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
518 u16 index;
519 u64 refcount;
520 u16 uid;
521 u8 dedicated : 1;
522 };
523
524 struct mlx5_rl_table {
525 /* protect rate limit table */
526 struct mutex rl_lock;
527 u16 max_size;
528 u32 max_rate;
529 u32 min_rate;
530 struct mlx5_rl_entry *rl_entry;
531 };
532
533 struct mlx5_core_roce {
534 struct mlx5_flow_table *ft;
535 struct mlx5_flow_group *fg;
536 struct mlx5_flow_handle *allow_rule;
537 };
538
539 struct mlx5_priv {
540 /* IRQ table valid only for real pci devices PF or VF */
541 struct mlx5_irq_table *irq_table;
542 struct mlx5_eq_table *eq_table;
543
544 /* pages stuff */
545 struct mlx5_nb pg_nb;
546 struct workqueue_struct *pg_wq;
547 struct xarray page_root_xa;
548 int fw_pages;
549 atomic_t reg_pages;
550 struct list_head free_list;
551 int vfs_pages;
552 int peer_pf_pages;
553
554 struct mlx5_core_health health;
555
556 /* start: qp staff */
557 struct dentry *qp_debugfs;
558 struct dentry *eq_debugfs;
559 struct dentry *cq_debugfs;
560 struct dentry *cmdif_debugfs;
561 /* end: qp staff */
562
563 /* start: alloc staff */
564 /* protect buffer alocation according to numa node */
565 struct mutex alloc_mutex;
566 int numa_node;
567
568 struct mutex pgdir_mutex;
569 struct list_head pgdir_list;
570 /* end: alloc staff */
571 struct dentry *dbg_root;
572
573 struct list_head dev_list;
574 struct list_head ctx_list;
575 spinlock_t ctx_lock;
576 struct mlx5_events *events;
577
578 struct mlx5_flow_steering *steering;
579 struct mlx5_mpfs *mpfs;
580 struct mlx5_eswitch *eswitch;
581 struct mlx5_core_sriov sriov;
582 struct mlx5_lag *lag;
583 struct mlx5_devcom *devcom;
584 struct mlx5_fw_reset *fw_reset;
585 struct mlx5_core_roce roce;
586 struct mlx5_fc_stats fc_stats;
587 struct mlx5_rl_table rl_table;
588
589 struct mlx5_bfreg_data bfregs;
590 struct mlx5_uars_page *uar;
591 };
592
593 enum mlx5_device_state {
594 MLX5_DEVICE_STATE_UNINITIALIZED,
595 MLX5_DEVICE_STATE_UP,
596 MLX5_DEVICE_STATE_INTERNAL_ERROR,
597 };
598
599 enum mlx5_interface_state {
600 MLX5_INTERFACE_STATE_UP = BIT(0),
601 };
602
603 enum mlx5_pci_status {
604 MLX5_PCI_STATUS_DISABLED,
605 MLX5_PCI_STATUS_ENABLED,
606 };
607
608 enum mlx5_pagefault_type_flags {
609 MLX5_PFAULT_REQUESTOR = 1 << 0,
610 MLX5_PFAULT_WRITE = 1 << 1,
611 MLX5_PFAULT_RDMA = 1 << 2,
612 };
613
614 struct mlx5_td {
615 /* protects tirs list changes while tirs refresh */
616 struct mutex list_lock;
617 struct list_head tirs_list;
618 u32 tdn;
619 };
620
621 struct mlx5e_resources {
622 u32 pdn;
623 struct mlx5_td td;
624 struct mlx5_core_mkey mkey;
625 struct mlx5_sq_bfreg bfreg;
626 };
627
628 enum mlx5_sw_icm_type {
629 MLX5_SW_ICM_TYPE_STEERING,
630 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
631 };
632
633 #define MLX5_MAX_RESERVED_GIDS 8
634
635 struct mlx5_rsvd_gids {
636 unsigned int start;
637 unsigned int count;
638 struct ida ida;
639 };
640
641 #define MAX_PIN_NUM 8
642 struct mlx5_pps {
643 u8 pin_caps[MAX_PIN_NUM];
644 struct work_struct out_work;
645 u64 start[MAX_PIN_NUM];
646 u8 enabled;
647 };
648
649 struct mlx5_timer {
650 struct cyclecounter cycles;
651 struct timecounter tc;
652 u32 nominal_c_mult;
653 unsigned long overflow_period;
654 struct delayed_work overflow_work;
655 };
656
657 struct mlx5_clock {
658 struct mlx5_nb pps_nb;
659 seqlock_t lock;
660 struct hwtstamp_config hwtstamp_config;
661 struct ptp_clock *ptp;
662 struct ptp_clock_info ptp_info;
663 struct mlx5_pps pps_info;
664 struct mlx5_timer timer;
665 };
666
667 struct mlx5_dm;
668 struct mlx5_fw_tracer;
669 struct mlx5_vxlan;
670 struct mlx5_geneve;
671 struct mlx5_hv_vhca;
672
673 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
674 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
675
676 struct mlx5_core_dev {
677 struct device *device;
678 enum mlx5_coredev_type coredev_type;
679 struct pci_dev *pdev;
680 /* sync pci state */
681 struct mutex pci_status_mutex;
682 enum mlx5_pci_status pci_status;
683 u8 rev_id;
684 char board_id[MLX5_BOARD_ID_LEN];
685 struct mlx5_cmd cmd;
686 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
687 struct {
688 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
689 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
690 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
691 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
692 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
693 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
694 u8 embedded_cpu;
695 } caps;
696 u64 sys_image_guid;
697 phys_addr_t iseg_base;
698 struct mlx5_init_seg __iomem *iseg;
699 phys_addr_t bar_addr;
700 enum mlx5_device_state state;
701 /* sync interface state */
702 struct mutex intf_state_mutex;
703 unsigned long intf_state;
704 struct mlx5_priv priv;
705 struct mlx5_profile *profile;
706 u32 issi;
707 struct mlx5e_resources mlx5e_res;
708 struct mlx5_dm *dm;
709 struct mlx5_vxlan *vxlan;
710 struct mlx5_geneve *geneve;
711 struct {
712 struct mlx5_rsvd_gids reserved_gids;
713 u32 roce_en;
714 } roce;
715 #ifdef CONFIG_MLX5_FPGA
716 struct mlx5_fpga_device *fpga;
717 #endif
718 #ifdef CONFIG_MLX5_ACCEL
719 const struct mlx5_accel_ipsec_ops *ipsec_ops;
720 #endif
721 struct mlx5_clock clock;
722 struct mlx5_ib_clock_info *clock_info;
723 struct mlx5_fw_tracer *tracer;
724 struct mlx5_rsc_dump *rsc_dump;
725 u32 vsc_addr;
726 struct mlx5_hv_vhca *hv_vhca;
727 };
728
729 struct mlx5_db {
730 __be32 *db;
731 union {
732 struct mlx5_db_pgdir *pgdir;
733 struct mlx5_ib_user_db_page *user_page;
734 } u;
735 dma_addr_t dma;
736 int index;
737 };
738
739 enum {
740 MLX5_COMP_EQ_SIZE = 1024,
741 };
742
743 enum {
744 MLX5_PTYS_IB = 1 << 0,
745 MLX5_PTYS_EN = 1 << 2,
746 };
747
748 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
749
750 enum {
751 MLX5_CMD_ENT_STATE_PENDING_COMP,
752 };
753
754 struct mlx5_cmd_work_ent {
755 unsigned long state;
756 struct mlx5_cmd_msg *in;
757 struct mlx5_cmd_msg *out;
758 void *uout;
759 int uout_size;
760 mlx5_cmd_cbk_t callback;
761 struct delayed_work cb_timeout_work;
762 void *context;
763 int idx;
764 struct completion handling;
765 struct completion done;
766 struct mlx5_cmd *cmd;
767 struct work_struct work;
768 struct mlx5_cmd_layout *lay;
769 int ret;
770 int page_queue;
771 u8 status;
772 u8 token;
773 u64 ts1;
774 u64 ts2;
775 u16 op;
776 bool polling;
777 /* Track the max comp handlers */
778 refcount_t refcnt;
779 };
780
781 struct mlx5_pas {
782 u64 pa;
783 u8 log_sz;
784 };
785
786 enum phy_port_state {
787 MLX5_AAA_111
788 };
789
790 struct mlx5_hca_vport_context {
791 u32 field_select;
792 bool sm_virt_aware;
793 bool has_smi;
794 bool has_raw;
795 enum port_state_policy policy;
796 enum phy_port_state phys_state;
797 enum ib_port_state vport_state;
798 u8 port_physical_state;
799 u64 sys_image_guid;
800 u64 port_guid;
801 u64 node_guid;
802 u32 cap_mask1;
803 u32 cap_mask1_perm;
804 u16 cap_mask2;
805 u16 cap_mask2_perm;
806 u16 lid;
807 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
808 u8 lmc;
809 u8 subnet_timeout;
810 u16 sm_lid;
811 u8 sm_sl;
812 u16 qkey_violation_counter;
813 u16 pkey_violation_counter;
814 bool grh_required;
815 };
816
mlx5_buf_offset(struct mlx5_frag_buf * buf,int offset)817 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
818 {
819 return buf->frags->buf + offset;
820 }
821
822 #define STRUCT_FIELD(header, field) \
823 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
824 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
825
pci2mlx5_core_dev(struct pci_dev * pdev)826 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
827 {
828 return pci_get_drvdata(pdev);
829 }
830
831 extern struct dentry *mlx5_debugfs_root;
832
fw_rev_maj(struct mlx5_core_dev * dev)833 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
834 {
835 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
836 }
837
fw_rev_min(struct mlx5_core_dev * dev)838 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
839 {
840 return ioread32be(&dev->iseg->fw_rev) >> 16;
841 }
842
fw_rev_sub(struct mlx5_core_dev * dev)843 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
844 {
845 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
846 }
847
mlx5_base_mkey(const u32 key)848 static inline u32 mlx5_base_mkey(const u32 key)
849 {
850 return key & 0xffffff00u;
851 }
852
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)853 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
854 u8 log_stride, u8 log_sz,
855 u16 strides_offset,
856 struct mlx5_frag_buf_ctrl *fbc)
857 {
858 fbc->frags = frags;
859 fbc->log_stride = log_stride;
860 fbc->log_sz = log_sz;
861 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
862 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
863 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
864 fbc->strides_offset = strides_offset;
865 }
866
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)867 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
868 u8 log_stride, u8 log_sz,
869 struct mlx5_frag_buf_ctrl *fbc)
870 {
871 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
872 }
873
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)874 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
875 u32 ix)
876 {
877 unsigned int frag;
878
879 ix += fbc->strides_offset;
880 frag = ix >> fbc->log_frag_strides;
881
882 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
883 }
884
885 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)886 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
887 {
888 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
889
890 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
891 }
892
893 enum {
894 CMD_ALLOWED_OPCODE_ALL,
895 };
896
897 int mlx5_cmd_init(struct mlx5_core_dev *dev);
898 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
899 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
900 enum mlx5_cmdif_state cmdif_state);
901 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
902 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
903 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
904
905 struct mlx5_async_ctx {
906 struct mlx5_core_dev *dev;
907 atomic_t num_inflight;
908 struct completion inflight_done;
909 };
910
911 struct mlx5_async_work;
912
913 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
914
915 struct mlx5_async_work {
916 struct mlx5_async_ctx *ctx;
917 mlx5_async_cbk_t user_callback;
918 };
919
920 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
921 struct mlx5_async_ctx *ctx);
922 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
923 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
924 void *out, int out_size, mlx5_async_cbk_t callback,
925 struct mlx5_async_work *work);
926
927 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
928 int out_size);
929
930 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
931 ({ \
932 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
933 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
934 })
935
936 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
937 ({ \
938 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
939 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
940 })
941
942 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
943 void *out, int out_size);
944 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
945 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
946
947 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
948 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
949 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
950 void mlx5_health_flush(struct mlx5_core_dev *dev);
951 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
952 int mlx5_health_init(struct mlx5_core_dev *dev);
953 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
954 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
955 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
956 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
957 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
958 int size, struct mlx5_frag_buf *buf);
959 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
960 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
961 struct mlx5_frag_buf *buf, int node);
962 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
963 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
964 gfp_t flags, int npages);
965 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
966 struct mlx5_cmd_mailbox *head);
967 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
968 struct mlx5_core_mkey *mkey,
969 u32 *in, int inlen);
970 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
971 struct mlx5_core_mkey *mkey);
972 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
973 u32 *out, int outlen);
974 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
975 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
976 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
977 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
978 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
979 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
980 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
981 s32 npages, bool ec_function);
982 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
983 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
984 void mlx5_register_debugfs(void);
985 void mlx5_unregister_debugfs(void);
986
987 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
988 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
989 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
990 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
991 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
992 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
993
994 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
995 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
996 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
997 int size_in, void *data_out, int size_out,
998 u16 reg_num, int arg, int write);
999
1000 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1001 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1002 int node);
1003 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1004
1005 const char *mlx5_command_str(int command);
1006 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1007 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1008 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1009 int npsvs, u32 *sig_index);
1010 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1011 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1012 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1013 struct mlx5_odp_caps *odp_caps);
1014 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1015 u8 port_num, void *out, size_t sz);
1016
1017 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1018 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1019 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1020 struct mlx5_rate_limit *rl);
1021 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1022 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1023 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1024 bool dedicated_entry, u16 *index);
1025 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1026 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1027 struct mlx5_rate_limit *rl_1);
1028 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1029 bool map_wc, bool fast_path);
1030 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1031
1032 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1033 struct cpumask *
1034 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1035 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1036 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1037 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1038 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1039
mlx5_mkey_to_idx(u32 mkey)1040 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1041 {
1042 return mkey >> 8;
1043 }
1044
mlx5_idx_to_mkey(u32 mkey_idx)1045 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1046 {
1047 return mkey_idx << 8;
1048 }
1049
mlx5_mkey_variant(u32 mkey)1050 static inline u8 mlx5_mkey_variant(u32 mkey)
1051 {
1052 return mkey & 0xff;
1053 }
1054
1055 enum {
1056 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1057 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1058 };
1059
1060 enum {
1061 MR_CACHE_LAST_STD_ENTRY = 20,
1062 MLX5_IMR_MTT_CACHE_ENTRY,
1063 MLX5_IMR_KSM_CACHE_ENTRY,
1064 MAX_MR_CACHE_ENTRIES
1065 };
1066
1067 enum {
1068 MLX5_INTERFACE_PROTOCOL_IB = 0,
1069 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1070 MLX5_INTERFACE_PROTOCOL_VDPA = 2,
1071 };
1072
1073 struct mlx5_interface {
1074 void * (*add)(struct mlx5_core_dev *dev);
1075 void (*remove)(struct mlx5_core_dev *dev, void *context);
1076 int (*attach)(struct mlx5_core_dev *dev, void *context);
1077 void (*detach)(struct mlx5_core_dev *dev, void *context);
1078 int protocol;
1079 struct list_head list;
1080 };
1081
1082 int mlx5_register_interface(struct mlx5_interface *intf);
1083 void mlx5_unregister_interface(struct mlx5_interface *intf);
1084 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1085 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1086 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1087 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1088
1089 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1090
1091 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1092 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1093 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1094 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1095 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1096 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1097 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1098 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1099 struct net_device *slave);
1100 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1101 u64 *values,
1102 int num_counters,
1103 size_t *offsets);
1104 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1105 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1106 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1107 u64 length, u32 log_alignment, u16 uid,
1108 phys_addr_t *addr, u32 *obj_id);
1109 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1110 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1111
1112 #ifdef CONFIG_MLX5_CORE_IPOIB
1113 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1114 struct ib_device *ibdev,
1115 const char *name,
1116 void (*setup)(struct net_device *));
1117 #endif /* CONFIG_MLX5_CORE_IPOIB */
1118 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1119 struct ib_device *device,
1120 struct rdma_netdev_alloc_params *params);
1121
1122 struct mlx5_profile {
1123 u64 mask;
1124 u8 log_max_qp;
1125 struct {
1126 int size;
1127 int limit;
1128 } mr_cache[MAX_MR_CACHE_ENTRIES];
1129 };
1130
1131 enum {
1132 MLX5_PCI_DEV_IS_VF = 1 << 0,
1133 };
1134
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1135 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1136 {
1137 return dev->coredev_type == MLX5_COREDEV_PF;
1138 }
1139
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1140 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1141 {
1142 return dev->coredev_type == MLX5_COREDEV_VF;
1143 }
1144
mlx5_core_is_ecpf(struct mlx5_core_dev * dev)1145 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
1146 {
1147 return dev->caps.embedded_cpu;
1148 }
1149
1150 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1151 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1152 {
1153 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1154 }
1155
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1156 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1157 {
1158 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1159 }
1160
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1161 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1162 {
1163 return dev->priv.sriov.max_vfs;
1164 }
1165
mlx5_get_gid_table_len(u16 param)1166 static inline int mlx5_get_gid_table_len(u16 param)
1167 {
1168 if (param > 4) {
1169 pr_warn("gid table length is zero\n");
1170 return 0;
1171 }
1172
1173 return 8 * (1 << param);
1174 }
1175
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1176 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1177 {
1178 return !!(dev->priv.rl_table.max_size);
1179 }
1180
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1181 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1182 {
1183 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1184 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1185 }
1186
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1187 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1188 {
1189 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1190 }
1191
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1192 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1193 {
1194 return mlx5_core_is_mp_slave(dev) ||
1195 mlx5_core_is_mp_master(dev);
1196 }
1197
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1198 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1199 {
1200 if (!mlx5_core_mp_enabled(dev))
1201 return 1;
1202
1203 return MLX5_CAP_GEN(dev, native_port_num);
1204 }
1205
1206 enum {
1207 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1208 };
1209
mlx5_is_roce_enabled(struct mlx5_core_dev * dev)1210 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1211 {
1212 struct devlink *devlink = priv_to_devlink(dev);
1213 union devlink_param_value val;
1214
1215 devlink_param_driverinit_value_get(devlink,
1216 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1217 &val);
1218 return val.vbool;
1219 }
1220
1221 #endif /* MLX5_DRIVER_H */
1222