1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
4 * which contain:
5 *
6 * Author: Nicolas Pitre
7 * Created: Dec 02, 2004
8 * Copyright: MontaVista Software Inc.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/platform_device.h>
13 #include <linux/interrupt.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/io.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20
21 #include <sound/pxa2xx-lib.h>
22
23 #include <mach/irqs.h>
24 #include <mach/regs-ac97.h>
25 #include <mach/audio.h>
26
27 static DEFINE_MUTEX(car_mutex);
28 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
29 static volatile long gsr_bits;
30 static struct clk *ac97_clk;
31 static struct clk *ac97conf_clk;
32 static int reset_gpio;
33
34 extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
35
36 /*
37 * Beware PXA27x bugs:
38 *
39 * o Slot 12 read from modem space will hang controller.
40 * o CDONE, SDONE interrupt fails after any slot 12 IO.
41 *
42 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
43 * 1 jiffy timeout if interrupt never comes).
44 */
45
pxa2xx_ac97_read(int slot,unsigned short reg)46 int pxa2xx_ac97_read(int slot, unsigned short reg)
47 {
48 int val = -ENODEV;
49 volatile u32 *reg_addr;
50
51 if (slot > 0)
52 return -ENODEV;
53
54 mutex_lock(&car_mutex);
55
56 /* set up primary or secondary codec space */
57 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
58 reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
59 else
60 reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
61 reg_addr += (reg >> 1);
62
63 /* start read access across the ac97 link */
64 GSR = GSR_CDONE | GSR_SDONE;
65 gsr_bits = 0;
66 val = (*reg_addr & 0xffff);
67 if (reg == AC97_GPIO_STATUS)
68 goto out;
69 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
70 !((GSR | gsr_bits) & GSR_SDONE)) {
71 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
72 __func__, reg, GSR | gsr_bits);
73 val = -ETIMEDOUT;
74 goto out;
75 }
76
77 /* valid data now */
78 GSR = GSR_CDONE | GSR_SDONE;
79 gsr_bits = 0;
80 val = (*reg_addr & 0xffff);
81 /* but we've just started another cycle... */
82 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
83
84 out: mutex_unlock(&car_mutex);
85 return val;
86 }
87 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
88
pxa2xx_ac97_write(int slot,unsigned short reg,unsigned short val)89 int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
90 {
91 volatile u32 *reg_addr;
92 int ret = 0;
93
94 mutex_lock(&car_mutex);
95
96 /* set up primary or secondary codec space */
97 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
98 reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
99 else
100 reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
101 reg_addr += (reg >> 1);
102
103 GSR = GSR_CDONE | GSR_SDONE;
104 gsr_bits = 0;
105 *reg_addr = val;
106 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
107 !((GSR | gsr_bits) & GSR_CDONE)) {
108 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
109 __func__, reg, GSR | gsr_bits);
110 ret = -EIO;
111 }
112
113 mutex_unlock(&car_mutex);
114 return ret;
115 }
116 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
117
118 #ifdef CONFIG_PXA25x
pxa_ac97_warm_pxa25x(void)119 static inline void pxa_ac97_warm_pxa25x(void)
120 {
121 gsr_bits = 0;
122
123 GCR |= GCR_WARM_RST;
124 }
125
pxa_ac97_cold_pxa25x(void)126 static inline void pxa_ac97_cold_pxa25x(void)
127 {
128 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
129 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
130
131 gsr_bits = 0;
132
133 GCR = GCR_COLD_RST;
134 }
135 #endif
136
137 #ifdef CONFIG_PXA27x
pxa_ac97_warm_pxa27x(void)138 static inline void pxa_ac97_warm_pxa27x(void)
139 {
140 gsr_bits = 0;
141
142 /* warm reset broken on Bulverde, so manually keep AC97 reset high */
143 pxa27x_configure_ac97reset(reset_gpio, true);
144 udelay(10);
145 GCR |= GCR_WARM_RST;
146 pxa27x_configure_ac97reset(reset_gpio, false);
147 udelay(500);
148 }
149
pxa_ac97_cold_pxa27x(void)150 static inline void pxa_ac97_cold_pxa27x(void)
151 {
152 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
153 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
154
155 gsr_bits = 0;
156
157 /* PXA27x Developers Manual section 13.5.2.2.1 */
158 clk_prepare_enable(ac97conf_clk);
159 udelay(5);
160 clk_disable_unprepare(ac97conf_clk);
161 GCR = GCR_COLD_RST | GCR_WARM_RST;
162 }
163 #endif
164
165 #ifdef CONFIG_PXA3xx
pxa_ac97_warm_pxa3xx(void)166 static inline void pxa_ac97_warm_pxa3xx(void)
167 {
168 gsr_bits = 0;
169
170 /* Can't use interrupts */
171 GCR |= GCR_WARM_RST;
172 }
173
pxa_ac97_cold_pxa3xx(void)174 static inline void pxa_ac97_cold_pxa3xx(void)
175 {
176 /* Hold CLKBPB for 100us */
177 GCR = 0;
178 GCR = GCR_CLKBPB;
179 udelay(100);
180 GCR = 0;
181
182 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
183 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
184
185 gsr_bits = 0;
186
187 /* Can't use interrupts on PXA3xx */
188 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
189
190 GCR = GCR_WARM_RST | GCR_COLD_RST;
191 }
192 #endif
193
pxa2xx_ac97_try_warm_reset(void)194 bool pxa2xx_ac97_try_warm_reset(void)
195 {
196 unsigned long gsr;
197 unsigned int timeout = 100;
198
199 #ifdef CONFIG_PXA25x
200 if (cpu_is_pxa25x())
201 pxa_ac97_warm_pxa25x();
202 else
203 #endif
204 #ifdef CONFIG_PXA27x
205 if (cpu_is_pxa27x())
206 pxa_ac97_warm_pxa27x();
207 else
208 #endif
209 #ifdef CONFIG_PXA3xx
210 if (cpu_is_pxa3xx())
211 pxa_ac97_warm_pxa3xx();
212 else
213 #endif
214 snd_BUG();
215
216 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
217 mdelay(1);
218
219 gsr = GSR | gsr_bits;
220 if (!(gsr & (GSR_PCR | GSR_SCR))) {
221 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
222 __func__, gsr);
223
224 return false;
225 }
226
227 return true;
228 }
229 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
230
pxa2xx_ac97_try_cold_reset(void)231 bool pxa2xx_ac97_try_cold_reset(void)
232 {
233 unsigned long gsr;
234 unsigned int timeout = 1000;
235
236 #ifdef CONFIG_PXA25x
237 if (cpu_is_pxa25x())
238 pxa_ac97_cold_pxa25x();
239 else
240 #endif
241 #ifdef CONFIG_PXA27x
242 if (cpu_is_pxa27x())
243 pxa_ac97_cold_pxa27x();
244 else
245 #endif
246 #ifdef CONFIG_PXA3xx
247 if (cpu_is_pxa3xx())
248 pxa_ac97_cold_pxa3xx();
249 else
250 #endif
251 snd_BUG();
252
253 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
254 mdelay(1);
255
256 gsr = GSR | gsr_bits;
257 if (!(gsr & (GSR_PCR | GSR_SCR))) {
258 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
259 __func__, gsr);
260
261 return false;
262 }
263
264 return true;
265 }
266 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
267
268
pxa2xx_ac97_finish_reset(void)269 void pxa2xx_ac97_finish_reset(void)
270 {
271 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
272 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
273 }
274 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
275
pxa2xx_ac97_irq(int irq,void * dev_id)276 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
277 {
278 long status;
279
280 status = GSR;
281 if (status) {
282 GSR = status;
283 gsr_bits |= status;
284 wake_up(&gsr_wq);
285
286 /* Although we don't use those we still need to clear them
287 since they tend to spuriously trigger when MMC is used
288 (hardware bug? go figure)... */
289 if (cpu_is_pxa27x()) {
290 MISR = MISR_EOC;
291 PISR = PISR_EOC;
292 MCSR = MCSR_EOC;
293 }
294
295 return IRQ_HANDLED;
296 }
297
298 return IRQ_NONE;
299 }
300
301 #ifdef CONFIG_PM
pxa2xx_ac97_hw_suspend(void)302 int pxa2xx_ac97_hw_suspend(void)
303 {
304 GCR |= GCR_ACLINK_OFF;
305 clk_disable_unprepare(ac97_clk);
306 return 0;
307 }
308 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
309
pxa2xx_ac97_hw_resume(void)310 int pxa2xx_ac97_hw_resume(void)
311 {
312 clk_prepare_enable(ac97_clk);
313 return 0;
314 }
315 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
316 #endif
317
pxa2xx_ac97_hw_probe(struct platform_device * dev)318 int pxa2xx_ac97_hw_probe(struct platform_device *dev)
319 {
320 int ret;
321 pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
322
323 if (pdata) {
324 switch (pdata->reset_gpio) {
325 case 95:
326 case 113:
327 reset_gpio = pdata->reset_gpio;
328 break;
329 case 0:
330 reset_gpio = 113;
331 break;
332 case -1:
333 break;
334 default:
335 dev_err(&dev->dev, "Invalid reset GPIO %d\n",
336 pdata->reset_gpio);
337 }
338 } else if (!pdata && dev->dev.of_node) {
339 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
340 if (!pdata)
341 return -ENOMEM;
342 pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
343 "reset-gpios", 0);
344 if (pdata->reset_gpio == -ENOENT)
345 pdata->reset_gpio = -1;
346 else if (pdata->reset_gpio < 0)
347 return pdata->reset_gpio;
348 reset_gpio = pdata->reset_gpio;
349 } else {
350 if (cpu_is_pxa27x())
351 reset_gpio = 113;
352 }
353
354 if (cpu_is_pxa27x()) {
355 /*
356 * This gpio is needed for a work-around to a bug in the ac97
357 * controller during warm reset. The direction and level is set
358 * here so that it is an output driven high when switching from
359 * AC97_nRESET alt function to generic gpio.
360 */
361 ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
362 "pxa27x ac97 reset");
363 if (ret < 0) {
364 pr_err("%s: gpio_request_one() failed: %d\n",
365 __func__, ret);
366 goto err_conf;
367 }
368 pxa27x_configure_ac97reset(reset_gpio, false);
369
370 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
371 if (IS_ERR(ac97conf_clk)) {
372 ret = PTR_ERR(ac97conf_clk);
373 ac97conf_clk = NULL;
374 goto err_conf;
375 }
376 }
377
378 ac97_clk = clk_get(&dev->dev, "AC97CLK");
379 if (IS_ERR(ac97_clk)) {
380 ret = PTR_ERR(ac97_clk);
381 ac97_clk = NULL;
382 goto err_clk;
383 }
384
385 ret = clk_prepare_enable(ac97_clk);
386 if (ret)
387 goto err_clk2;
388
389 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
390 if (ret < 0)
391 goto err_irq;
392
393 return 0;
394
395 err_irq:
396 GCR |= GCR_ACLINK_OFF;
397 err_clk2:
398 clk_put(ac97_clk);
399 ac97_clk = NULL;
400 err_clk:
401 if (ac97conf_clk) {
402 clk_put(ac97conf_clk);
403 ac97conf_clk = NULL;
404 }
405 err_conf:
406 return ret;
407 }
408 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
409
pxa2xx_ac97_hw_remove(struct platform_device * dev)410 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
411 {
412 if (cpu_is_pxa27x())
413 gpio_free(reset_gpio);
414 GCR |= GCR_ACLINK_OFF;
415 free_irq(IRQ_AC97, NULL);
416 if (ac97conf_clk) {
417 clk_put(ac97conf_clk);
418 ac97conf_clk = NULL;
419 }
420 clk_disable_unprepare(ac97_clk);
421 clk_put(ac97_clk);
422 ac97_clk = NULL;
423 }
424 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
425
426 MODULE_AUTHOR("Nicolas Pitre");
427 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
428 MODULE_LICENSE("GPL");
429
430