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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * C-Media CMI8788 driver for C-Media's reference design and similar models
4  *
5  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
6  */
7 
8 /*
9  * CMI8788:
10  *
11  *   SPI 0 -> 1st AK4396 (front)
12  *   SPI 1 -> 2nd AK4396 (surround)
13  *   SPI 2 -> 3rd AK4396 (center/LFE)
14  *   SPI 3 -> WM8785
15  *   SPI 4 -> 4th AK4396 (back)
16  *
17  *   GPIO 0 -> DFS0 of AK5385
18  *   GPIO 1 -> DFS1 of AK5385
19  *
20  * X-Meridian models:
21  *   GPIO 4 -> enable extension S/PDIF input
22  *   GPIO 6 -> enable on-board S/PDIF input
23  *
24  * Claro models:
25  *   GPIO 6 -> S/PDIF from optical (0) or coaxial (1) input
26  *   GPIO 8 -> enable headphone amplifier
27  *
28  * CM9780:
29  *
30  *   LINE_OUT -> input of ADC
31  *
32  *   AUX_IN <- aux
33  *   CD_IN  <- CD
34  *   MIC_IN <- mic
35  *
36  *   GPO 0 -> route line-in (0) or AC97 output (1) to ADC input
37  */
38 
39 #include <linux/delay.h>
40 #include <linux/mutex.h>
41 #include <linux/pci.h>
42 #include <linux/module.h>
43 #include <sound/ac97_codec.h>
44 #include <sound/control.h>
45 #include <sound/core.h>
46 #include <sound/info.h>
47 #include <sound/initval.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/tlv.h>
51 #include "oxygen.h"
52 #include "xonar_dg.h"
53 #include "ak4396.h"
54 #include "wm8785.h"
55 
56 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
57 MODULE_DESCRIPTION("C-Media CMI8788 driver");
58 MODULE_LICENSE("GPL v2");
59 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8786}"
60 			",{C-Media,CMI8787}"
61 			",{C-Media,CMI8788}}");
62 
63 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
65 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
66 
67 module_param_array(index, int, NULL, 0444);
68 MODULE_PARM_DESC(index, "card index");
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string");
71 module_param_array(enable, bool, NULL, 0444);
72 MODULE_PARM_DESC(enable, "enable card");
73 
74 enum {
75 	MODEL_CMEDIA_REF,
76 	MODEL_MERIDIAN,
77 	MODEL_MERIDIAN_2G,
78 	MODEL_CLARO,
79 	MODEL_CLARO_HALO,
80 	MODEL_FANTASIA,
81 	MODEL_SERENADE,
82 	MODEL_2CH_OUTPUT,
83 	MODEL_HG2PCI,
84 	MODEL_XONAR_DG,
85 	MODEL_XONAR_DGX,
86 };
87 
88 static const struct pci_device_id oxygen_ids[] = {
89 	/* C-Media's reference design */
90 	{ OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF },
91 	{ OXYGEN_PCI_SUBID(0x10b0, 0x0217), .driver_data = MODEL_CMEDIA_REF },
92 	{ OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF },
93 	{ OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF },
94 	{ OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF },
95 	{ OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF },
96 	{ OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF },
97 	{ OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF },
98 	{ OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF },
99 	/* Asus Xonar DG */
100 	{ OXYGEN_PCI_SUBID(0x1043, 0x8467), .driver_data = MODEL_XONAR_DG },
101 	/* Asus Xonar DGX */
102 	{ OXYGEN_PCI_SUBID(0x1043, 0x8521), .driver_data = MODEL_XONAR_DGX },
103 	/* PCI 2.0 HD Audio */
104 	{ OXYGEN_PCI_SUBID(0x13f6, 0x8782), .driver_data = MODEL_2CH_OUTPUT },
105 	/* Kuroutoshikou CMI8787-HG2PCI */
106 	{ OXYGEN_PCI_SUBID(0x13f6, 0xffff), .driver_data = MODEL_HG2PCI },
107 	/* TempoTec HiFier Fantasia */
108 	{ OXYGEN_PCI_SUBID(0x14c3, 0x1710), .driver_data = MODEL_FANTASIA },
109 	/* TempoTec HiFier Serenade */
110 	{ OXYGEN_PCI_SUBID(0x14c3, 0x1711), .driver_data = MODEL_SERENADE },
111 	/* AuzenTech X-Meridian */
112 	{ OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN },
113 	/* AuzenTech X-Meridian 2G */
114 	{ OXYGEN_PCI_SUBID(0x5431, 0x017a), .driver_data = MODEL_MERIDIAN_2G },
115 	/* HT-Omega Claro */
116 	{ OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO },
117 	/* HT-Omega Claro halo */
118 	{ OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO },
119 	{ }
120 };
121 MODULE_DEVICE_TABLE(pci, oxygen_ids);
122 
123 
124 #define GPIO_AK5385_DFS_MASK	0x0003
125 #define GPIO_AK5385_DFS_NORMAL	0x0000
126 #define GPIO_AK5385_DFS_DOUBLE	0x0001
127 #define GPIO_AK5385_DFS_QUAD	0x0002
128 
129 #define GPIO_MERIDIAN_DIG_MASK	0x0050
130 #define GPIO_MERIDIAN_DIG_EXT	0x0010
131 #define GPIO_MERIDIAN_DIG_BOARD	0x0040
132 
133 #define GPIO_CLARO_DIG_COAX	0x0040
134 #define GPIO_CLARO_HP		0x0100
135 
136 struct generic_data {
137 	unsigned int dacs;
138 	u8 ak4396_regs[4][5];
139 	u16 wm8785_regs[3];
140 };
141 
ak4396_write(struct oxygen * chip,unsigned int codec,u8 reg,u8 value)142 static void ak4396_write(struct oxygen *chip, unsigned int codec,
143 			 u8 reg, u8 value)
144 {
145 	/* maps ALSA channel pair number to SPI output */
146 	static const u8 codec_spi_map[4] = {
147 		0, 1, 2, 4
148 	};
149 	struct generic_data *data = chip->model_data;
150 
151 	oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
152 			 OXYGEN_SPI_DATA_LENGTH_2 |
153 			 OXYGEN_SPI_CLOCK_160 |
154 			 (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
155 			 OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
156 			 AK4396_WRITE | (reg << 8) | value);
157 	data->ak4396_regs[codec][reg] = value;
158 }
159 
ak4396_write_cached(struct oxygen * chip,unsigned int codec,u8 reg,u8 value)160 static void ak4396_write_cached(struct oxygen *chip, unsigned int codec,
161 				u8 reg, u8 value)
162 {
163 	struct generic_data *data = chip->model_data;
164 
165 	if (value != data->ak4396_regs[codec][reg])
166 		ak4396_write(chip, codec, reg, value);
167 }
168 
wm8785_write(struct oxygen * chip,u8 reg,unsigned int value)169 static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
170 {
171 	struct generic_data *data = chip->model_data;
172 
173 	oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
174 			 OXYGEN_SPI_DATA_LENGTH_2 |
175 			 OXYGEN_SPI_CLOCK_160 |
176 			 (3 << OXYGEN_SPI_CODEC_SHIFT) |
177 			 OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
178 			 (reg << 9) | value);
179 	if (reg < ARRAY_SIZE(data->wm8785_regs))
180 		data->wm8785_regs[reg] = value;
181 }
182 
ak4396_registers_init(struct oxygen * chip)183 static void ak4396_registers_init(struct oxygen *chip)
184 {
185 	struct generic_data *data = chip->model_data;
186 	unsigned int i;
187 
188 	for (i = 0; i < data->dacs; ++i) {
189 		ak4396_write(chip, i, AK4396_CONTROL_1,
190 			     AK4396_DIF_24_MSB | AK4396_RSTN);
191 		ak4396_write(chip, i, AK4396_CONTROL_2,
192 			     data->ak4396_regs[0][AK4396_CONTROL_2]);
193 		ak4396_write(chip, i, AK4396_CONTROL_3,
194 			     AK4396_PCM);
195 		ak4396_write(chip, i, AK4396_LCH_ATT,
196 			     chip->dac_volume[i * 2]);
197 		ak4396_write(chip, i, AK4396_RCH_ATT,
198 			     chip->dac_volume[i * 2 + 1]);
199 	}
200 }
201 
ak4396_init(struct oxygen * chip)202 static void ak4396_init(struct oxygen *chip)
203 {
204 	struct generic_data *data = chip->model_data;
205 
206 	data->dacs = chip->model.dac_channels_pcm / 2;
207 	data->ak4396_regs[0][AK4396_CONTROL_2] =
208 		AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL;
209 	ak4396_registers_init(chip);
210 	snd_component_add(chip->card, "AK4396");
211 }
212 
ak5385_init(struct oxygen * chip)213 static void ak5385_init(struct oxygen *chip)
214 {
215 	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK);
216 	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK);
217 	snd_component_add(chip->card, "AK5385");
218 }
219 
wm8785_registers_init(struct oxygen * chip)220 static void wm8785_registers_init(struct oxygen *chip)
221 {
222 	struct generic_data *data = chip->model_data;
223 
224 	wm8785_write(chip, WM8785_R7, 0);
225 	wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]);
226 	wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
227 }
228 
wm8785_init(struct oxygen * chip)229 static void wm8785_init(struct oxygen *chip)
230 {
231 	struct generic_data *data = chip->model_data;
232 
233 	data->wm8785_regs[0] =
234 		WM8785_MCR_SLAVE | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST;
235 	data->wm8785_regs[2] = WM8785_HPFR | WM8785_HPFL;
236 	wm8785_registers_init(chip);
237 	snd_component_add(chip->card, "WM8785");
238 }
239 
generic_init(struct oxygen * chip)240 static void generic_init(struct oxygen *chip)
241 {
242 	ak4396_init(chip);
243 	wm8785_init(chip);
244 }
245 
meridian_init(struct oxygen * chip)246 static void meridian_init(struct oxygen *chip)
247 {
248 	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL,
249 			  GPIO_MERIDIAN_DIG_MASK);
250 	oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
251 			      GPIO_MERIDIAN_DIG_BOARD, GPIO_MERIDIAN_DIG_MASK);
252 	ak4396_init(chip);
253 	ak5385_init(chip);
254 }
255 
claro_enable_hp(struct oxygen * chip)256 static void claro_enable_hp(struct oxygen *chip)
257 {
258 	msleep(300);
259 	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP);
260 	oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
261 }
262 
claro_init(struct oxygen * chip)263 static void claro_init(struct oxygen *chip)
264 {
265 	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX);
266 	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX);
267 	ak4396_init(chip);
268 	wm8785_init(chip);
269 	claro_enable_hp(chip);
270 }
271 
claro_halo_init(struct oxygen * chip)272 static void claro_halo_init(struct oxygen *chip)
273 {
274 	oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_DIG_COAX);
275 	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_DIG_COAX);
276 	ak4396_init(chip);
277 	ak5385_init(chip);
278 	claro_enable_hp(chip);
279 }
280 
fantasia_init(struct oxygen * chip)281 static void fantasia_init(struct oxygen *chip)
282 {
283 	ak4396_init(chip);
284 	snd_component_add(chip->card, "CS5340");
285 }
286 
stereo_output_init(struct oxygen * chip)287 static void stereo_output_init(struct oxygen *chip)
288 {
289 	ak4396_init(chip);
290 }
291 
generic_cleanup(struct oxygen * chip)292 static void generic_cleanup(struct oxygen *chip)
293 {
294 }
295 
claro_disable_hp(struct oxygen * chip)296 static void claro_disable_hp(struct oxygen *chip)
297 {
298 	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
299 }
300 
claro_cleanup(struct oxygen * chip)301 static void claro_cleanup(struct oxygen *chip)
302 {
303 	claro_disable_hp(chip);
304 }
305 
claro_suspend(struct oxygen * chip)306 static void claro_suspend(struct oxygen *chip)
307 {
308 	claro_disable_hp(chip);
309 }
310 
generic_resume(struct oxygen * chip)311 static void generic_resume(struct oxygen *chip)
312 {
313 	ak4396_registers_init(chip);
314 	wm8785_registers_init(chip);
315 }
316 
meridian_resume(struct oxygen * chip)317 static void meridian_resume(struct oxygen *chip)
318 {
319 	ak4396_registers_init(chip);
320 }
321 
claro_resume(struct oxygen * chip)322 static void claro_resume(struct oxygen *chip)
323 {
324 	ak4396_registers_init(chip);
325 	claro_enable_hp(chip);
326 }
327 
stereo_resume(struct oxygen * chip)328 static void stereo_resume(struct oxygen *chip)
329 {
330 	ak4396_registers_init(chip);
331 }
332 
set_ak4396_params(struct oxygen * chip,struct snd_pcm_hw_params * params)333 static void set_ak4396_params(struct oxygen *chip,
334 			      struct snd_pcm_hw_params *params)
335 {
336 	struct generic_data *data = chip->model_data;
337 	unsigned int i;
338 	u8 value;
339 
340 	value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK;
341 	if (params_rate(params) <= 54000)
342 		value |= AK4396_DFS_NORMAL;
343 	else if (params_rate(params) <= 108000)
344 		value |= AK4396_DFS_DOUBLE;
345 	else
346 		value |= AK4396_DFS_QUAD;
347 
348 	msleep(1); /* wait for the new MCLK to become stable */
349 
350 	if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) {
351 		for (i = 0; i < data->dacs; ++i) {
352 			ak4396_write(chip, i, AK4396_CONTROL_1,
353 				     AK4396_DIF_24_MSB);
354 			ak4396_write(chip, i, AK4396_CONTROL_2, value);
355 			ak4396_write(chip, i, AK4396_CONTROL_1,
356 				     AK4396_DIF_24_MSB | AK4396_RSTN);
357 		}
358 	}
359 }
360 
update_ak4396_volume(struct oxygen * chip)361 static void update_ak4396_volume(struct oxygen *chip)
362 {
363 	struct generic_data *data = chip->model_data;
364 	unsigned int i;
365 
366 	for (i = 0; i < data->dacs; ++i) {
367 		ak4396_write_cached(chip, i, AK4396_LCH_ATT,
368 				    chip->dac_volume[i * 2]);
369 		ak4396_write_cached(chip, i, AK4396_RCH_ATT,
370 				    chip->dac_volume[i * 2 + 1]);
371 	}
372 }
373 
update_ak4396_mute(struct oxygen * chip)374 static void update_ak4396_mute(struct oxygen *chip)
375 {
376 	struct generic_data *data = chip->model_data;
377 	unsigned int i;
378 	u8 value;
379 
380 	value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE;
381 	if (chip->dac_mute)
382 		value |= AK4396_SMUTE;
383 	for (i = 0; i < data->dacs; ++i)
384 		ak4396_write_cached(chip, i, AK4396_CONTROL_2, value);
385 }
386 
set_wm8785_params(struct oxygen * chip,struct snd_pcm_hw_params * params)387 static void set_wm8785_params(struct oxygen *chip,
388 			      struct snd_pcm_hw_params *params)
389 {
390 	struct generic_data *data = chip->model_data;
391 	unsigned int value;
392 
393 	value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST;
394 	if (params_rate(params) <= 48000)
395 		value |= WM8785_OSR_SINGLE;
396 	else if (params_rate(params) <= 96000)
397 		value |= WM8785_OSR_DOUBLE;
398 	else
399 		value |= WM8785_OSR_QUAD;
400 	if (value != data->wm8785_regs[0]) {
401 		wm8785_write(chip, WM8785_R7, 0);
402 		wm8785_write(chip, WM8785_R0, value);
403 		wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
404 	}
405 }
406 
set_ak5385_params(struct oxygen * chip,struct snd_pcm_hw_params * params)407 static void set_ak5385_params(struct oxygen *chip,
408 			      struct snd_pcm_hw_params *params)
409 {
410 	unsigned int value;
411 
412 	if (params_rate(params) <= 54000)
413 		value = GPIO_AK5385_DFS_NORMAL;
414 	else if (params_rate(params) <= 108000)
415 		value = GPIO_AK5385_DFS_DOUBLE;
416 	else
417 		value = GPIO_AK5385_DFS_QUAD;
418 	oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
419 			      value, GPIO_AK5385_DFS_MASK);
420 }
421 
set_no_params(struct oxygen * chip,struct snd_pcm_hw_params * params)422 static void set_no_params(struct oxygen *chip, struct snd_pcm_hw_params *params)
423 {
424 }
425 
rolloff_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)426 static int rolloff_info(struct snd_kcontrol *ctl,
427 			struct snd_ctl_elem_info *info)
428 {
429 	static const char *const names[2] = {
430 		"Sharp Roll-off", "Slow Roll-off"
431 	};
432 
433 	return snd_ctl_enum_info(info, 1, 2, names);
434 }
435 
rolloff_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)436 static int rolloff_get(struct snd_kcontrol *ctl,
437 		       struct snd_ctl_elem_value *value)
438 {
439 	struct oxygen *chip = ctl->private_data;
440 	struct generic_data *data = chip->model_data;
441 
442 	value->value.enumerated.item[0] =
443 		(data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0;
444 	return 0;
445 }
446 
rolloff_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)447 static int rolloff_put(struct snd_kcontrol *ctl,
448 		       struct snd_ctl_elem_value *value)
449 {
450 	struct oxygen *chip = ctl->private_data;
451 	struct generic_data *data = chip->model_data;
452 	unsigned int i;
453 	int changed;
454 	u8 reg;
455 
456 	mutex_lock(&chip->mutex);
457 	reg = data->ak4396_regs[0][AK4396_CONTROL_2];
458 	if (value->value.enumerated.item[0])
459 		reg |= AK4396_SLOW;
460 	else
461 		reg &= ~AK4396_SLOW;
462 	changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2];
463 	if (changed) {
464 		for (i = 0; i < data->dacs; ++i)
465 			ak4396_write(chip, i, AK4396_CONTROL_2, reg);
466 	}
467 	mutex_unlock(&chip->mutex);
468 	return changed;
469 }
470 
471 static const struct snd_kcontrol_new rolloff_control = {
472 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
473 	.name = "DAC Filter Playback Enum",
474 	.info = rolloff_info,
475 	.get = rolloff_get,
476 	.put = rolloff_put,
477 };
478 
hpf_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)479 static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
480 {
481 	static const char *const names[2] = {
482 		"None", "High-pass Filter"
483 	};
484 
485 	return snd_ctl_enum_info(info, 1, 2, names);
486 }
487 
hpf_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)488 static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
489 {
490 	struct oxygen *chip = ctl->private_data;
491 	struct generic_data *data = chip->model_data;
492 
493 	value->value.enumerated.item[0] =
494 		(data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0;
495 	return 0;
496 }
497 
hpf_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)498 static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
499 {
500 	struct oxygen *chip = ctl->private_data;
501 	struct generic_data *data = chip->model_data;
502 	unsigned int reg;
503 	int changed;
504 
505 	mutex_lock(&chip->mutex);
506 	reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL);
507 	if (value->value.enumerated.item[0])
508 		reg |= WM8785_HPFR | WM8785_HPFL;
509 	changed = reg != data->wm8785_regs[WM8785_R2];
510 	if (changed)
511 		wm8785_write(chip, WM8785_R2, reg);
512 	mutex_unlock(&chip->mutex);
513 	return changed;
514 }
515 
516 static const struct snd_kcontrol_new hpf_control = {
517 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
518 	.name = "ADC Filter Capture Enum",
519 	.info = hpf_info,
520 	.get = hpf_get,
521 	.put = hpf_put,
522 };
523 
meridian_dig_source_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)524 static int meridian_dig_source_info(struct snd_kcontrol *ctl,
525 				    struct snd_ctl_elem_info *info)
526 {
527 	static const char *const names[2] = { "On-board", "Extension" };
528 
529 	return snd_ctl_enum_info(info, 1, 2, names);
530 }
531 
claro_dig_source_info(struct snd_kcontrol * ctl,struct snd_ctl_elem_info * info)532 static int claro_dig_source_info(struct snd_kcontrol *ctl,
533 				 struct snd_ctl_elem_info *info)
534 {
535 	static const char *const names[2] = { "Optical", "Coaxial" };
536 
537 	return snd_ctl_enum_info(info, 1, 2, names);
538 }
539 
meridian_dig_source_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)540 static int meridian_dig_source_get(struct snd_kcontrol *ctl,
541 				   struct snd_ctl_elem_value *value)
542 {
543 	struct oxygen *chip = ctl->private_data;
544 
545 	value->value.enumerated.item[0] =
546 		!!(oxygen_read16(chip, OXYGEN_GPIO_DATA) &
547 		   GPIO_MERIDIAN_DIG_EXT);
548 	return 0;
549 }
550 
claro_dig_source_get(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)551 static int claro_dig_source_get(struct snd_kcontrol *ctl,
552 				struct snd_ctl_elem_value *value)
553 {
554 	struct oxygen *chip = ctl->private_data;
555 
556 	value->value.enumerated.item[0] =
557 		!!(oxygen_read16(chip, OXYGEN_GPIO_DATA) &
558 		   GPIO_CLARO_DIG_COAX);
559 	return 0;
560 }
561 
meridian_dig_source_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)562 static int meridian_dig_source_put(struct snd_kcontrol *ctl,
563 				   struct snd_ctl_elem_value *value)
564 {
565 	struct oxygen *chip = ctl->private_data;
566 	u16 old_reg, new_reg;
567 	int changed;
568 
569 	mutex_lock(&chip->mutex);
570 	old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA);
571 	new_reg = old_reg & ~GPIO_MERIDIAN_DIG_MASK;
572 	if (value->value.enumerated.item[0] == 0)
573 		new_reg |= GPIO_MERIDIAN_DIG_BOARD;
574 	else
575 		new_reg |= GPIO_MERIDIAN_DIG_EXT;
576 	changed = new_reg != old_reg;
577 	if (changed)
578 		oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg);
579 	mutex_unlock(&chip->mutex);
580 	return changed;
581 }
582 
claro_dig_source_put(struct snd_kcontrol * ctl,struct snd_ctl_elem_value * value)583 static int claro_dig_source_put(struct snd_kcontrol *ctl,
584 				struct snd_ctl_elem_value *value)
585 {
586 	struct oxygen *chip = ctl->private_data;
587 	u16 old_reg, new_reg;
588 	int changed;
589 
590 	mutex_lock(&chip->mutex);
591 	old_reg = oxygen_read16(chip, OXYGEN_GPIO_DATA);
592 	new_reg = old_reg & ~GPIO_CLARO_DIG_COAX;
593 	if (value->value.enumerated.item[0])
594 		new_reg |= GPIO_CLARO_DIG_COAX;
595 	changed = new_reg != old_reg;
596 	if (changed)
597 		oxygen_write16(chip, OXYGEN_GPIO_DATA, new_reg);
598 	mutex_unlock(&chip->mutex);
599 	return changed;
600 }
601 
602 static const struct snd_kcontrol_new meridian_dig_source_control = {
603 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
604 	.name = "IEC958 Source Capture Enum",
605 	.info = meridian_dig_source_info,
606 	.get = meridian_dig_source_get,
607 	.put = meridian_dig_source_put,
608 };
609 
610 static const struct snd_kcontrol_new claro_dig_source_control = {
611 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
612 	.name = "IEC958 Source Capture Enum",
613 	.info = claro_dig_source_info,
614 	.get = claro_dig_source_get,
615 	.put = claro_dig_source_put,
616 };
617 
generic_mixer_init(struct oxygen * chip)618 static int generic_mixer_init(struct oxygen *chip)
619 {
620 	return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip));
621 }
622 
generic_wm8785_mixer_init(struct oxygen * chip)623 static int generic_wm8785_mixer_init(struct oxygen *chip)
624 {
625 	int err;
626 
627 	err = generic_mixer_init(chip);
628 	if (err < 0)
629 		return err;
630 	err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip));
631 	if (err < 0)
632 		return err;
633 	return 0;
634 }
635 
meridian_mixer_init(struct oxygen * chip)636 static int meridian_mixer_init(struct oxygen *chip)
637 {
638 	int err;
639 
640 	err = generic_mixer_init(chip);
641 	if (err < 0)
642 		return err;
643 	err = snd_ctl_add(chip->card,
644 			  snd_ctl_new1(&meridian_dig_source_control, chip));
645 	if (err < 0)
646 		return err;
647 	return 0;
648 }
649 
claro_mixer_init(struct oxygen * chip)650 static int claro_mixer_init(struct oxygen *chip)
651 {
652 	int err;
653 
654 	err = generic_wm8785_mixer_init(chip);
655 	if (err < 0)
656 		return err;
657 	err = snd_ctl_add(chip->card,
658 			  snd_ctl_new1(&claro_dig_source_control, chip));
659 	if (err < 0)
660 		return err;
661 	return 0;
662 }
663 
claro_halo_mixer_init(struct oxygen * chip)664 static int claro_halo_mixer_init(struct oxygen *chip)
665 {
666 	int err;
667 
668 	err = generic_mixer_init(chip);
669 	if (err < 0)
670 		return err;
671 	err = snd_ctl_add(chip->card,
672 			  snd_ctl_new1(&claro_dig_source_control, chip));
673 	if (err < 0)
674 		return err;
675 	return 0;
676 }
677 
dump_ak4396_registers(struct oxygen * chip,struct snd_info_buffer * buffer)678 static void dump_ak4396_registers(struct oxygen *chip,
679 				  struct snd_info_buffer *buffer)
680 {
681 	struct generic_data *data = chip->model_data;
682 	unsigned int dac, i;
683 
684 	for (dac = 0; dac < data->dacs; ++dac) {
685 		snd_iprintf(buffer, "\nAK4396 %u:", dac + 1);
686 		for (i = 0; i < 5; ++i)
687 			snd_iprintf(buffer, " %02x", data->ak4396_regs[dac][i]);
688 	}
689 	snd_iprintf(buffer, "\n");
690 }
691 
dump_wm8785_registers(struct oxygen * chip,struct snd_info_buffer * buffer)692 static void dump_wm8785_registers(struct oxygen *chip,
693 				  struct snd_info_buffer *buffer)
694 {
695 	struct generic_data *data = chip->model_data;
696 	unsigned int i;
697 
698 	snd_iprintf(buffer, "\nWM8785:");
699 	for (i = 0; i < 3; ++i)
700 		snd_iprintf(buffer, " %03x", data->wm8785_regs[i]);
701 	snd_iprintf(buffer, "\n");
702 }
703 
dump_oxygen_registers(struct oxygen * chip,struct snd_info_buffer * buffer)704 static void dump_oxygen_registers(struct oxygen *chip,
705 				  struct snd_info_buffer *buffer)
706 {
707 	dump_ak4396_registers(chip, buffer);
708 	dump_wm8785_registers(chip, buffer);
709 }
710 
711 static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
712 
713 static const struct oxygen_model model_generic = {
714 	.shortname = "C-Media CMI8788",
715 	.longname = "C-Media Oxygen HD Audio",
716 	.chip = "CMI8788",
717 	.init = generic_init,
718 	.mixer_init = generic_wm8785_mixer_init,
719 	.cleanup = generic_cleanup,
720 	.resume = generic_resume,
721 	.set_dac_params = set_ak4396_params,
722 	.set_adc_params = set_wm8785_params,
723 	.update_dac_volume = update_ak4396_volume,
724 	.update_dac_mute = update_ak4396_mute,
725 	.dump_registers = dump_oxygen_registers,
726 	.dac_tlv = ak4396_db_scale,
727 	.model_data_size = sizeof(struct generic_data),
728 	.device_config = PLAYBACK_0_TO_I2S |
729 			 PLAYBACK_1_TO_SPDIF |
730 			 PLAYBACK_2_TO_AC97_1 |
731 			 CAPTURE_0_FROM_I2S_1 |
732 			 CAPTURE_1_FROM_SPDIF |
733 			 CAPTURE_2_FROM_AC97_1 |
734 			 AC97_CD_INPUT,
735 	.dac_channels_pcm = 8,
736 	.dac_channels_mixer = 8,
737 	.dac_volume_min = 0,
738 	.dac_volume_max = 255,
739 	.function_flags = OXYGEN_FUNCTION_SPI |
740 			  OXYGEN_FUNCTION_ENABLE_SPI_4_5,
741 	.dac_mclks = OXYGEN_MCLKS(256, 128, 128),
742 	.adc_mclks = OXYGEN_MCLKS(256, 256, 128),
743 	.dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
744 	.adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
745 };
746 
get_oxygen_model(struct oxygen * chip,const struct pci_device_id * id)747 static int get_oxygen_model(struct oxygen *chip,
748 			    const struct pci_device_id *id)
749 {
750 	static const char *const names[] = {
751 		[MODEL_MERIDIAN]	= "AuzenTech X-Meridian",
752 		[MODEL_MERIDIAN_2G]	= "AuzenTech X-Meridian 2G",
753 		[MODEL_CLARO]		= "HT-Omega Claro",
754 		[MODEL_CLARO_HALO]	= "HT-Omega Claro halo",
755 		[MODEL_FANTASIA]	= "TempoTec HiFier Fantasia",
756 		[MODEL_SERENADE]	= "TempoTec HiFier Serenade",
757 		[MODEL_HG2PCI]		= "CMI8787-HG2PCI",
758 		[MODEL_XONAR_DG]        = "Xonar DG",
759 		[MODEL_XONAR_DGX]       = "Xonar DGX",
760 	};
761 
762 	chip->model = model_generic;
763 	switch (id->driver_data) {
764 	case MODEL_MERIDIAN:
765 	case MODEL_MERIDIAN_2G:
766 		chip->model.init = meridian_init;
767 		chip->model.mixer_init = meridian_mixer_init;
768 		chip->model.resume = meridian_resume;
769 		chip->model.set_adc_params = set_ak5385_params;
770 		chip->model.dump_registers = dump_ak4396_registers;
771 		chip->model.device_config = PLAYBACK_0_TO_I2S |
772 					    PLAYBACK_1_TO_SPDIF |
773 					    CAPTURE_0_FROM_I2S_2 |
774 					    CAPTURE_1_FROM_SPDIF;
775 		if (id->driver_data == MODEL_MERIDIAN)
776 			chip->model.device_config |= AC97_CD_INPUT;
777 		break;
778 	case MODEL_CLARO:
779 		chip->model.init = claro_init;
780 		chip->model.mixer_init = claro_mixer_init;
781 		chip->model.cleanup = claro_cleanup;
782 		chip->model.suspend = claro_suspend;
783 		chip->model.resume = claro_resume;
784 		break;
785 	case MODEL_CLARO_HALO:
786 		chip->model.init = claro_halo_init;
787 		chip->model.mixer_init = claro_halo_mixer_init;
788 		chip->model.cleanup = claro_cleanup;
789 		chip->model.suspend = claro_suspend;
790 		chip->model.resume = claro_resume;
791 		chip->model.set_adc_params = set_ak5385_params;
792 		chip->model.dump_registers = dump_ak4396_registers;
793 		chip->model.device_config = PLAYBACK_0_TO_I2S |
794 					    PLAYBACK_1_TO_SPDIF |
795 					    CAPTURE_0_FROM_I2S_2 |
796 					    CAPTURE_1_FROM_SPDIF;
797 		break;
798 	case MODEL_FANTASIA:
799 	case MODEL_SERENADE:
800 	case MODEL_2CH_OUTPUT:
801 	case MODEL_HG2PCI:
802 		chip->model.shortname = "C-Media CMI8787";
803 		chip->model.chip = "CMI8787";
804 		if (id->driver_data == MODEL_FANTASIA)
805 			chip->model.init = fantasia_init;
806 		else
807 			chip->model.init = stereo_output_init;
808 		chip->model.resume = stereo_resume;
809 		chip->model.mixer_init = generic_mixer_init;
810 		chip->model.set_adc_params = set_no_params;
811 		chip->model.dump_registers = dump_ak4396_registers;
812 		chip->model.device_config = PLAYBACK_0_TO_I2S |
813 					    PLAYBACK_1_TO_SPDIF;
814 		if (id->driver_data == MODEL_FANTASIA) {
815 			chip->model.device_config |= CAPTURE_0_FROM_I2S_1;
816 			chip->model.adc_mclks = OXYGEN_MCLKS(256, 128, 128);
817 		}
818 		chip->model.dac_channels_pcm = 2;
819 		chip->model.dac_channels_mixer = 2;
820 		break;
821 	case MODEL_XONAR_DG:
822 	case MODEL_XONAR_DGX:
823 		chip->model = model_xonar_dg;
824 		break;
825 	}
826 	if (id->driver_data == MODEL_MERIDIAN ||
827 	    id->driver_data == MODEL_MERIDIAN_2G ||
828 	    id->driver_data == MODEL_CLARO_HALO) {
829 		chip->model.misc_flags = OXYGEN_MISC_MIDI;
830 		chip->model.device_config |= MIDI_OUTPUT | MIDI_INPUT;
831 	}
832 	if (id->driver_data < ARRAY_SIZE(names) && names[id->driver_data])
833 		chip->model.shortname = names[id->driver_data];
834 	return 0;
835 }
836 
generic_oxygen_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)837 static int generic_oxygen_probe(struct pci_dev *pci,
838 				const struct pci_device_id *pci_id)
839 {
840 	static int dev;
841 	int err;
842 
843 	if (dev >= SNDRV_CARDS)
844 		return -ENODEV;
845 	if (!enable[dev]) {
846 		++dev;
847 		return -ENOENT;
848 	}
849 	err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE,
850 			       oxygen_ids, get_oxygen_model);
851 	if (err >= 0)
852 		++dev;
853 	return err;
854 }
855 
856 static struct pci_driver oxygen_driver = {
857 	.name = KBUILD_MODNAME,
858 	.id_table = oxygen_ids,
859 	.probe = generic_oxygen_probe,
860 	.remove = oxygen_pci_remove,
861 #ifdef CONFIG_PM_SLEEP
862 	.driver = {
863 		.pm = &oxygen_pci_pm,
864 	},
865 #endif
866 };
867 
868 module_pci_driver(oxygen_driver);
869