1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
4 //
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/time.h>
17 #include <sound/core.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
22
23 #include "fsl_sai.h"
24 #include "imx-pcm.h"
25
26 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
27 FSL_SAI_CSR_FEIE)
28
29 static const unsigned int fsl_sai_rates[] = {
30 8000, 11025, 12000, 16000, 22050,
31 24000, 32000, 44100, 48000, 64000,
32 88200, 96000, 176400, 192000
33 };
34
35 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
36 .count = ARRAY_SIZE(fsl_sai_rates),
37 .list = fsl_sai_rates,
38 };
39
40 /**
41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
42 *
43 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
44 * or Receiver's for both streams. This function is used to check if clocks of
45 * the stream's are synced by the opposite stream.
46 *
47 * @sai: SAI context
48 * @dir: stream direction
49 */
fsl_sai_dir_is_synced(struct fsl_sai * sai,int dir)50 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
51 {
52 int adir = (dir == TX) ? RX : TX;
53
54 /* current dir in async mode while opposite dir in sync mode */
55 return !sai->synchronous[dir] && sai->synchronous[adir];
56 }
57
fsl_sai_isr(int irq,void * devid)58 static irqreturn_t fsl_sai_isr(int irq, void *devid)
59 {
60 struct fsl_sai *sai = (struct fsl_sai *)devid;
61 unsigned int ofs = sai->soc_data->reg_offset;
62 struct device *dev = &sai->pdev->dev;
63 u32 flags, xcsr, mask;
64 bool irq_none = true;
65
66 /*
67 * Both IRQ status bits and IRQ mask bits are in the xCSR but
68 * different shifts. And we here create a mask only for those
69 * IRQs that we activated.
70 */
71 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
72
73 /* Tx IRQ */
74 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
75 flags = xcsr & mask;
76
77 if (flags)
78 irq_none = false;
79 else
80 goto irq_rx;
81
82 if (flags & FSL_SAI_CSR_WSF)
83 dev_dbg(dev, "isr: Start of Tx word detected\n");
84
85 if (flags & FSL_SAI_CSR_SEF)
86 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
87
88 if (flags & FSL_SAI_CSR_FEF) {
89 dev_dbg(dev, "isr: Transmit underrun detected\n");
90 /* FIFO reset for safety */
91 xcsr |= FSL_SAI_CSR_FR;
92 }
93
94 if (flags & FSL_SAI_CSR_FWF)
95 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
96
97 if (flags & FSL_SAI_CSR_FRF)
98 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
99
100 flags &= FSL_SAI_CSR_xF_W_MASK;
101 xcsr &= ~FSL_SAI_CSR_xF_MASK;
102
103 if (flags)
104 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
105
106 irq_rx:
107 /* Rx IRQ */
108 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
109 flags = xcsr & mask;
110
111 if (flags)
112 irq_none = false;
113 else
114 goto out;
115
116 if (flags & FSL_SAI_CSR_WSF)
117 dev_dbg(dev, "isr: Start of Rx word detected\n");
118
119 if (flags & FSL_SAI_CSR_SEF)
120 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
121
122 if (flags & FSL_SAI_CSR_FEF) {
123 dev_dbg(dev, "isr: Receive overflow detected\n");
124 /* FIFO reset for safety */
125 xcsr |= FSL_SAI_CSR_FR;
126 }
127
128 if (flags & FSL_SAI_CSR_FWF)
129 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
130
131 if (flags & FSL_SAI_CSR_FRF)
132 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
133
134 flags &= FSL_SAI_CSR_xF_W_MASK;
135 xcsr &= ~FSL_SAI_CSR_xF_MASK;
136
137 if (flags)
138 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
139
140 out:
141 if (irq_none)
142 return IRQ_NONE;
143 else
144 return IRQ_HANDLED;
145 }
146
fsl_sai_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)147 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
148 u32 rx_mask, int slots, int slot_width)
149 {
150 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
151
152 sai->slots = slots;
153 sai->slot_width = slot_width;
154
155 return 0;
156 }
157
fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)158 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
159 unsigned int ratio)
160 {
161 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
162
163 sai->bclk_ratio = ratio;
164
165 return 0;
166 }
167
fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int fsl_dir)168 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
169 int clk_id, unsigned int freq, int fsl_dir)
170 {
171 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
172 unsigned int ofs = sai->soc_data->reg_offset;
173 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
174 u32 val_cr2 = 0;
175
176 switch (clk_id) {
177 case FSL_SAI_CLK_BUS:
178 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
179 break;
180 case FSL_SAI_CLK_MAST1:
181 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
182 break;
183 case FSL_SAI_CLK_MAST2:
184 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
185 break;
186 case FSL_SAI_CLK_MAST3:
187 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
188 break;
189 default:
190 return -EINVAL;
191 }
192
193 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
194 FSL_SAI_CR2_MSEL_MASK, val_cr2);
195
196 return 0;
197 }
198
fsl_sai_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)199 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
200 int clk_id, unsigned int freq, int dir)
201 {
202 int ret;
203
204 if (dir == SND_SOC_CLOCK_IN)
205 return 0;
206
207 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
208 FSL_FMT_TRANSMITTER);
209 if (ret) {
210 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
211 return ret;
212 }
213
214 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
215 FSL_FMT_RECEIVER);
216 if (ret)
217 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
218
219 return ret;
220 }
221
fsl_sai_set_dai_fmt_tr(struct snd_soc_dai * cpu_dai,unsigned int fmt,int fsl_dir)222 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
223 unsigned int fmt, int fsl_dir)
224 {
225 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
226 unsigned int ofs = sai->soc_data->reg_offset;
227 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
228 u32 val_cr2 = 0, val_cr4 = 0;
229
230 if (!sai->is_lsb_first)
231 val_cr4 |= FSL_SAI_CR4_MF;
232
233 sai->is_dsp_mode = false;
234 /* DAI mode */
235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
236 case SND_SOC_DAIFMT_I2S:
237 /*
238 * Frame low, 1clk before data, one word length for frame sync,
239 * frame sync starts one serial clock cycle earlier,
240 * that is, together with the last bit of the previous
241 * data word.
242 */
243 val_cr2 |= FSL_SAI_CR2_BCP;
244 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
245 break;
246 case SND_SOC_DAIFMT_LEFT_J:
247 /*
248 * Frame high, one word length for frame sync,
249 * frame sync asserts with the first bit of the frame.
250 */
251 val_cr2 |= FSL_SAI_CR2_BCP;
252 break;
253 case SND_SOC_DAIFMT_DSP_A:
254 /*
255 * Frame high, 1clk before data, one bit for frame sync,
256 * frame sync starts one serial clock cycle earlier,
257 * that is, together with the last bit of the previous
258 * data word.
259 */
260 val_cr2 |= FSL_SAI_CR2_BCP;
261 val_cr4 |= FSL_SAI_CR4_FSE;
262 sai->is_dsp_mode = true;
263 break;
264 case SND_SOC_DAIFMT_DSP_B:
265 /*
266 * Frame high, one bit for frame sync,
267 * frame sync asserts with the first bit of the frame.
268 */
269 val_cr2 |= FSL_SAI_CR2_BCP;
270 sai->is_dsp_mode = true;
271 break;
272 case SND_SOC_DAIFMT_RIGHT_J:
273 /* To be done */
274 default:
275 return -EINVAL;
276 }
277
278 /* DAI clock inversion */
279 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
280 case SND_SOC_DAIFMT_IB_IF:
281 /* Invert both clocks */
282 val_cr2 ^= FSL_SAI_CR2_BCP;
283 val_cr4 ^= FSL_SAI_CR4_FSP;
284 break;
285 case SND_SOC_DAIFMT_IB_NF:
286 /* Invert bit clock */
287 val_cr2 ^= FSL_SAI_CR2_BCP;
288 break;
289 case SND_SOC_DAIFMT_NB_IF:
290 /* Invert frame clock */
291 val_cr4 ^= FSL_SAI_CR4_FSP;
292 break;
293 case SND_SOC_DAIFMT_NB_NF:
294 /* Nothing to do for both normal cases */
295 break;
296 default:
297 return -EINVAL;
298 }
299
300 /* DAI clock master masks */
301 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
302 case SND_SOC_DAIFMT_CBS_CFS:
303 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
304 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
305 sai->is_slave_mode = false;
306 break;
307 case SND_SOC_DAIFMT_CBM_CFM:
308 sai->is_slave_mode = true;
309 break;
310 case SND_SOC_DAIFMT_CBS_CFM:
311 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
312 sai->is_slave_mode = false;
313 break;
314 case SND_SOC_DAIFMT_CBM_CFS:
315 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
316 sai->is_slave_mode = true;
317 break;
318 default:
319 return -EINVAL;
320 }
321
322 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
323 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
324 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
325 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
326 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
327
328 return 0;
329 }
330
fsl_sai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)331 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
332 {
333 int ret;
334
335 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
336 if (ret) {
337 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
338 return ret;
339 }
340
341 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
342 if (ret)
343 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
344
345 return ret;
346 }
347
fsl_sai_set_bclk(struct snd_soc_dai * dai,bool tx,u32 freq)348 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
349 {
350 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
351 unsigned int ofs = sai->soc_data->reg_offset;
352 unsigned long clk_rate;
353 u32 savediv = 0, ratio, savesub = freq;
354 int adir = tx ? RX : TX;
355 int dir = tx ? TX : RX;
356 u32 id;
357 int ret = 0;
358
359 /* Don't apply to slave mode */
360 if (sai->is_slave_mode)
361 return 0;
362
363 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
364 clk_rate = clk_get_rate(sai->mclk_clk[id]);
365 if (!clk_rate)
366 continue;
367
368 ratio = clk_rate / freq;
369
370 ret = clk_rate - ratio * freq;
371
372 /*
373 * Drop the source that can not be
374 * divided into the required rate.
375 */
376 if (ret != 0 && clk_rate / ret < 1000)
377 continue;
378
379 dev_dbg(dai->dev,
380 "ratio %d for freq %dHz based on clock %ldHz\n",
381 ratio, freq, clk_rate);
382
383 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
384 ratio /= 2;
385 else
386 continue;
387
388 if (ret < savesub) {
389 savediv = ratio;
390 sai->mclk_id[tx] = id;
391 savesub = ret;
392 }
393
394 if (ret == 0)
395 break;
396 }
397
398 if (savediv == 0) {
399 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
400 tx ? 'T' : 'R', freq);
401 return -EINVAL;
402 }
403
404 /*
405 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
406 * set TCR2 register for playback.
407 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
408 * and capture.
409 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
410 * and capture.
411 * 4) For Tx and Rx are both Synchronous with another SAI, we just
412 * ignore it.
413 */
414 if (fsl_sai_dir_is_synced(sai, adir)) {
415 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
416 FSL_SAI_CR2_MSEL_MASK,
417 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
418 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
419 FSL_SAI_CR2_DIV_MASK, savediv - 1);
420 } else if (!sai->synchronous[dir]) {
421 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
422 FSL_SAI_CR2_MSEL_MASK,
423 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
424 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
425 FSL_SAI_CR2_DIV_MASK, savediv - 1);
426 }
427
428 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
429 sai->mclk_id[tx], savediv, savesub);
430
431 return 0;
432 }
433
fsl_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)434 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
435 struct snd_pcm_hw_params *params,
436 struct snd_soc_dai *cpu_dai)
437 {
438 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
439 unsigned int ofs = sai->soc_data->reg_offset;
440 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
441 unsigned int channels = params_channels(params);
442 u32 word_width = params_width(params);
443 u32 val_cr4 = 0, val_cr5 = 0;
444 u32 slots = (channels == 1) ? 2 : channels;
445 u32 slot_width = word_width;
446 int adir = tx ? RX : TX;
447 u32 pins;
448 int ret;
449
450 if (sai->slots)
451 slots = sai->slots;
452
453 if (sai->slot_width)
454 slot_width = sai->slot_width;
455
456 pins = DIV_ROUND_UP(channels, slots);
457
458 if (!sai->is_slave_mode) {
459 if (sai->bclk_ratio)
460 ret = fsl_sai_set_bclk(cpu_dai, tx,
461 sai->bclk_ratio *
462 params_rate(params));
463 else
464 ret = fsl_sai_set_bclk(cpu_dai, tx,
465 slots * slot_width *
466 params_rate(params));
467 if (ret)
468 return ret;
469
470 /* Do not enable the clock if it is already enabled */
471 if (!(sai->mclk_streams & BIT(substream->stream))) {
472 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
473 if (ret)
474 return ret;
475
476 sai->mclk_streams |= BIT(substream->stream);
477 }
478 }
479
480 if (!sai->is_dsp_mode)
481 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
482
483 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
484 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
485
486 if (sai->is_lsb_first)
487 val_cr5 |= FSL_SAI_CR5_FBT(0);
488 else
489 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
490
491 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
492
493 /* Set to output mode to avoid tri-stated data pins */
494 if (tx)
495 val_cr4 |= FSL_SAI_CR4_CHMOD;
496
497 /*
498 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
499 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
500 * RCR5(TCR5) for playback(capture), or there will be sync error.
501 */
502
503 if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) {
504 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
505 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
506 FSL_SAI_CR4_CHMOD_MASK,
507 val_cr4);
508 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
509 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
510 FSL_SAI_CR5_FBT_MASK, val_cr5);
511 }
512
513 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
514 FSL_SAI_CR3_TRCE_MASK,
515 FSL_SAI_CR3_TRCE((1 << pins) - 1));
516 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
517 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
518 FSL_SAI_CR4_CHMOD_MASK,
519 val_cr4);
520 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
521 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
522 FSL_SAI_CR5_FBT_MASK, val_cr5);
523 regmap_write(sai->regmap, FSL_SAI_xMR(tx),
524 ~0UL - ((1 << min(channels, slots)) - 1));
525
526 return 0;
527 }
528
fsl_sai_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)529 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
530 struct snd_soc_dai *cpu_dai)
531 {
532 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
533 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
534 unsigned int ofs = sai->soc_data->reg_offset;
535
536 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
537 FSL_SAI_CR3_TRCE_MASK, 0);
538
539 if (!sai->is_slave_mode &&
540 sai->mclk_streams & BIT(substream->stream)) {
541 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
542 sai->mclk_streams &= ~BIT(substream->stream);
543 }
544
545 return 0;
546 }
547
fsl_sai_config_disable(struct fsl_sai * sai,int dir)548 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
549 {
550 unsigned int ofs = sai->soc_data->reg_offset;
551 bool tx = dir == TX;
552 u32 xcsr, count = 100;
553
554 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
555 FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
556
557 /* TERE will remain set till the end of current frame */
558 do {
559 udelay(10);
560 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
561 } while (--count && xcsr & FSL_SAI_CSR_TERE);
562
563 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
564 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
565
566 /*
567 * For sai master mode, after several open/close sai,
568 * there will be no frame clock, and can't recover
569 * anymore. Add software reset to fix this issue.
570 * This is a hardware bug, and will be fix in the
571 * next sai version.
572 */
573 if (!sai->is_slave_mode) {
574 /* Software Reset */
575 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
576 /* Clear SR bit to finish the reset */
577 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
578 }
579 }
580
fsl_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)581 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
582 struct snd_soc_dai *cpu_dai)
583 {
584 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
585 unsigned int ofs = sai->soc_data->reg_offset;
586
587 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
588 int adir = tx ? RX : TX;
589 int dir = tx ? TX : RX;
590 u32 xcsr;
591
592 /*
593 * Asynchronous mode: Clear SYNC for both Tx and Rx.
594 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
595 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
596 */
597 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
598 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
599 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
600 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
601
602 /*
603 * It is recommended that the transmitter is the last enabled
604 * and the first disabled.
605 */
606 switch (cmd) {
607 case SNDRV_PCM_TRIGGER_START:
608 case SNDRV_PCM_TRIGGER_RESUME:
609 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
610 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
611 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
612
613 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
614 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
615 /*
616 * Enable the opposite direction for synchronous mode
617 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
618 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
619 *
620 * RM recommends to enable RE after TE for case 1 and to enable
621 * TE after RE for case 2, but we here may not always guarantee
622 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
623 * TE after RE, which is against what RM recommends but should
624 * be safe to do, judging by years of testing results.
625 */
626 if (fsl_sai_dir_is_synced(sai, adir))
627 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
628 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
629
630 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
631 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
632 break;
633 case SNDRV_PCM_TRIGGER_STOP:
634 case SNDRV_PCM_TRIGGER_SUSPEND:
635 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
636 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
637 FSL_SAI_CSR_FRDE, 0);
638 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
639 FSL_SAI_CSR_xIE_MASK, 0);
640
641 /* Check if the opposite FRDE is also disabled */
642 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
643
644 /*
645 * If opposite stream provides clocks for synchronous mode and
646 * it is inactive, disable it before disabling the current one
647 */
648 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
649 fsl_sai_config_disable(sai, adir);
650
651 /*
652 * Disable current stream if either of:
653 * 1. current stream doesn't provide clocks for synchronous mode
654 * 2. current stream provides clocks for synchronous mode but no
655 * more stream is active.
656 */
657 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
658 fsl_sai_config_disable(sai, dir);
659
660 break;
661 default:
662 return -EINVAL;
663 }
664
665 return 0;
666 }
667
fsl_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)668 static int fsl_sai_startup(struct snd_pcm_substream *substream,
669 struct snd_soc_dai *cpu_dai)
670 {
671 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
672 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
673 int ret;
674
675 /*
676 * EDMA controller needs period size to be a multiple of
677 * tx/rx maxburst
678 */
679 if (sai->soc_data->use_edma)
680 snd_pcm_hw_constraint_step(substream->runtime, 0,
681 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
682 tx ? sai->dma_params_tx.maxburst :
683 sai->dma_params_rx.maxburst);
684
685 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
686 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
687
688 return ret;
689 }
690
691 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
692 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
693 .set_sysclk = fsl_sai_set_dai_sysclk,
694 .set_fmt = fsl_sai_set_dai_fmt,
695 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
696 .hw_params = fsl_sai_hw_params,
697 .hw_free = fsl_sai_hw_free,
698 .trigger = fsl_sai_trigger,
699 .startup = fsl_sai_startup,
700 };
701
fsl_sai_dai_probe(struct snd_soc_dai * cpu_dai)702 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
703 {
704 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
705 unsigned int ofs = sai->soc_data->reg_offset;
706
707 /* Software Reset for both Tx and Rx */
708 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
709 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
710 /* Clear SR bit to finish the reset */
711 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
712 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
713
714 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
715 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
716 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
717 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
718 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
719 FSL_SAI_MAXBURST_RX - 1);
720
721 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
722 &sai->dma_params_rx);
723
724 snd_soc_dai_set_drvdata(cpu_dai, sai);
725
726 return 0;
727 }
728
729 static struct snd_soc_dai_driver fsl_sai_dai_template = {
730 .probe = fsl_sai_dai_probe,
731 .playback = {
732 .stream_name = "CPU-Playback",
733 .channels_min = 1,
734 .channels_max = 32,
735 .rate_min = 8000,
736 .rate_max = 192000,
737 .rates = SNDRV_PCM_RATE_KNOT,
738 .formats = FSL_SAI_FORMATS,
739 },
740 .capture = {
741 .stream_name = "CPU-Capture",
742 .channels_min = 1,
743 .channels_max = 32,
744 .rate_min = 8000,
745 .rate_max = 192000,
746 .rates = SNDRV_PCM_RATE_KNOT,
747 .formats = FSL_SAI_FORMATS,
748 },
749 .ops = &fsl_sai_pcm_dai_ops,
750 };
751
752 static const struct snd_soc_component_driver fsl_component = {
753 .name = "fsl-sai",
754 };
755
756 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
757 {FSL_SAI_TCR1(0), 0},
758 {FSL_SAI_TCR2(0), 0},
759 {FSL_SAI_TCR3(0), 0},
760 {FSL_SAI_TCR4(0), 0},
761 {FSL_SAI_TCR5(0), 0},
762 {FSL_SAI_TDR0, 0},
763 {FSL_SAI_TDR1, 0},
764 {FSL_SAI_TDR2, 0},
765 {FSL_SAI_TDR3, 0},
766 {FSL_SAI_TDR4, 0},
767 {FSL_SAI_TDR5, 0},
768 {FSL_SAI_TDR6, 0},
769 {FSL_SAI_TDR7, 0},
770 {FSL_SAI_TMR, 0},
771 {FSL_SAI_RCR1(0), 0},
772 {FSL_SAI_RCR2(0), 0},
773 {FSL_SAI_RCR3(0), 0},
774 {FSL_SAI_RCR4(0), 0},
775 {FSL_SAI_RCR5(0), 0},
776 {FSL_SAI_RMR, 0},
777 };
778
779 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
780 {FSL_SAI_TCR1(8), 0},
781 {FSL_SAI_TCR2(8), 0},
782 {FSL_SAI_TCR3(8), 0},
783 {FSL_SAI_TCR4(8), 0},
784 {FSL_SAI_TCR5(8), 0},
785 {FSL_SAI_TDR0, 0},
786 {FSL_SAI_TDR1, 0},
787 {FSL_SAI_TDR2, 0},
788 {FSL_SAI_TDR3, 0},
789 {FSL_SAI_TDR4, 0},
790 {FSL_SAI_TDR5, 0},
791 {FSL_SAI_TDR6, 0},
792 {FSL_SAI_TDR7, 0},
793 {FSL_SAI_TMR, 0},
794 {FSL_SAI_RCR1(8), 0},
795 {FSL_SAI_RCR2(8), 0},
796 {FSL_SAI_RCR3(8), 0},
797 {FSL_SAI_RCR4(8), 0},
798 {FSL_SAI_RCR5(8), 0},
799 {FSL_SAI_RMR, 0},
800 {FSL_SAI_MCTL, 0},
801 {FSL_SAI_MDIV, 0},
802 };
803
fsl_sai_readable_reg(struct device * dev,unsigned int reg)804 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
805 {
806 struct fsl_sai *sai = dev_get_drvdata(dev);
807 unsigned int ofs = sai->soc_data->reg_offset;
808
809 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
810 return true;
811
812 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
813 return true;
814
815 switch (reg) {
816 case FSL_SAI_TFR0:
817 case FSL_SAI_TFR1:
818 case FSL_SAI_TFR2:
819 case FSL_SAI_TFR3:
820 case FSL_SAI_TFR4:
821 case FSL_SAI_TFR5:
822 case FSL_SAI_TFR6:
823 case FSL_SAI_TFR7:
824 case FSL_SAI_TMR:
825 case FSL_SAI_RDR0:
826 case FSL_SAI_RDR1:
827 case FSL_SAI_RDR2:
828 case FSL_SAI_RDR3:
829 case FSL_SAI_RDR4:
830 case FSL_SAI_RDR5:
831 case FSL_SAI_RDR6:
832 case FSL_SAI_RDR7:
833 case FSL_SAI_RFR0:
834 case FSL_SAI_RFR1:
835 case FSL_SAI_RFR2:
836 case FSL_SAI_RFR3:
837 case FSL_SAI_RFR4:
838 case FSL_SAI_RFR5:
839 case FSL_SAI_RFR6:
840 case FSL_SAI_RFR7:
841 case FSL_SAI_RMR:
842 case FSL_SAI_MCTL:
843 case FSL_SAI_MDIV:
844 case FSL_SAI_VERID:
845 case FSL_SAI_PARAM:
846 case FSL_SAI_TTCTN:
847 case FSL_SAI_RTCTN:
848 case FSL_SAI_TTCTL:
849 case FSL_SAI_TBCTN:
850 case FSL_SAI_TTCAP:
851 case FSL_SAI_RTCTL:
852 case FSL_SAI_RBCTN:
853 case FSL_SAI_RTCAP:
854 return true;
855 default:
856 return false;
857 }
858 }
859
fsl_sai_volatile_reg(struct device * dev,unsigned int reg)860 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
861 {
862 struct fsl_sai *sai = dev_get_drvdata(dev);
863 unsigned int ofs = sai->soc_data->reg_offset;
864
865 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
866 return true;
867
868 /* Set VERID and PARAM be volatile for reading value in probe */
869 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
870 return true;
871
872 switch (reg) {
873 case FSL_SAI_TFR0:
874 case FSL_SAI_TFR1:
875 case FSL_SAI_TFR2:
876 case FSL_SAI_TFR3:
877 case FSL_SAI_TFR4:
878 case FSL_SAI_TFR5:
879 case FSL_SAI_TFR6:
880 case FSL_SAI_TFR7:
881 case FSL_SAI_RFR0:
882 case FSL_SAI_RFR1:
883 case FSL_SAI_RFR2:
884 case FSL_SAI_RFR3:
885 case FSL_SAI_RFR4:
886 case FSL_SAI_RFR5:
887 case FSL_SAI_RFR6:
888 case FSL_SAI_RFR7:
889 case FSL_SAI_RDR0:
890 case FSL_SAI_RDR1:
891 case FSL_SAI_RDR2:
892 case FSL_SAI_RDR3:
893 case FSL_SAI_RDR4:
894 case FSL_SAI_RDR5:
895 case FSL_SAI_RDR6:
896 case FSL_SAI_RDR7:
897 return true;
898 default:
899 return false;
900 }
901 }
902
fsl_sai_writeable_reg(struct device * dev,unsigned int reg)903 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
904 {
905 struct fsl_sai *sai = dev_get_drvdata(dev);
906 unsigned int ofs = sai->soc_data->reg_offset;
907
908 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
909 return true;
910
911 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
912 return true;
913
914 switch (reg) {
915 case FSL_SAI_TDR0:
916 case FSL_SAI_TDR1:
917 case FSL_SAI_TDR2:
918 case FSL_SAI_TDR3:
919 case FSL_SAI_TDR4:
920 case FSL_SAI_TDR5:
921 case FSL_SAI_TDR6:
922 case FSL_SAI_TDR7:
923 case FSL_SAI_TMR:
924 case FSL_SAI_RMR:
925 case FSL_SAI_MCTL:
926 case FSL_SAI_MDIV:
927 case FSL_SAI_TTCTL:
928 case FSL_SAI_RTCTL:
929 return true;
930 default:
931 return false;
932 }
933 }
934
935 static struct regmap_config fsl_sai_regmap_config = {
936 .reg_bits = 32,
937 .reg_stride = 4,
938 .val_bits = 32,
939 .fast_io = true,
940
941 .max_register = FSL_SAI_RMR,
942 .reg_defaults = fsl_sai_reg_defaults_ofs0,
943 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
944 .readable_reg = fsl_sai_readable_reg,
945 .volatile_reg = fsl_sai_volatile_reg,
946 .writeable_reg = fsl_sai_writeable_reg,
947 .cache_type = REGCACHE_FLAT,
948 };
949
fsl_sai_check_version(struct device * dev)950 static int fsl_sai_check_version(struct device *dev)
951 {
952 struct fsl_sai *sai = dev_get_drvdata(dev);
953 unsigned char ofs = sai->soc_data->reg_offset;
954 unsigned int val;
955 int ret;
956
957 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
958 return 0;
959
960 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
961 if (ret < 0)
962 return ret;
963
964 dev_dbg(dev, "VERID: 0x%016X\n", val);
965
966 sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >>
967 FSL_SAI_VERID_MAJOR_SHIFT;
968 sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >>
969 FSL_SAI_VERID_MINOR_SHIFT;
970 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
971
972 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
973 if (ret < 0)
974 return ret;
975
976 dev_dbg(dev, "PARAM: 0x%016X\n", val);
977
978 /* Max slots per frame, power of 2 */
979 sai->param.slot_num = 1 <<
980 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
981
982 /* Words per fifo, power of 2 */
983 sai->param.fifo_depth = 1 <<
984 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
985
986 /* Number of datalines implemented */
987 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
988
989 return 0;
990 }
991
fsl_sai_probe(struct platform_device * pdev)992 static int fsl_sai_probe(struct platform_device *pdev)
993 {
994 struct device_node *np = pdev->dev.of_node;
995 struct fsl_sai *sai;
996 struct regmap *gpr;
997 struct resource *res;
998 void __iomem *base;
999 char tmp[8];
1000 int irq, ret, i;
1001 int index;
1002
1003 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1004 if (!sai)
1005 return -ENOMEM;
1006
1007 sai->pdev = pdev;
1008 sai->soc_data = of_device_get_match_data(&pdev->dev);
1009
1010 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1011
1012 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1013 base = devm_ioremap_resource(&pdev->dev, res);
1014 if (IS_ERR(base))
1015 return PTR_ERR(base);
1016
1017 if (sai->soc_data->reg_offset == 8) {
1018 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
1019 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
1020 fsl_sai_regmap_config.num_reg_defaults =
1021 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
1022 }
1023
1024 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1025 "bus", base, &fsl_sai_regmap_config);
1026
1027 /* Compatible with old DTB cases */
1028 if (IS_ERR(sai->regmap) && PTR_ERR(sai->regmap) != -EPROBE_DEFER)
1029 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1030 "sai", base, &fsl_sai_regmap_config);
1031 if (IS_ERR(sai->regmap)) {
1032 dev_err(&pdev->dev, "regmap init failed\n");
1033 return PTR_ERR(sai->regmap);
1034 }
1035
1036 /* No error out for old DTB cases but only mark the clock NULL */
1037 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
1038 if (IS_ERR(sai->bus_clk)) {
1039 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
1040 PTR_ERR(sai->bus_clk));
1041 sai->bus_clk = NULL;
1042 }
1043
1044 sai->mclk_clk[0] = sai->bus_clk;
1045 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1046 sprintf(tmp, "mclk%d", i);
1047 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
1048 if (IS_ERR(sai->mclk_clk[i])) {
1049 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
1050 i + 1, PTR_ERR(sai->mclk_clk[i]));
1051 sai->mclk_clk[i] = NULL;
1052 }
1053 }
1054
1055 irq = platform_get_irq(pdev, 0);
1056 if (irq < 0)
1057 return irq;
1058
1059 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED,
1060 np->name, sai);
1061 if (ret) {
1062 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
1063 return ret;
1064 }
1065
1066 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
1067 sizeof(fsl_sai_dai_template));
1068
1069 /* Sync Tx with Rx as default by following old DT binding */
1070 sai->synchronous[RX] = true;
1071 sai->synchronous[TX] = false;
1072 sai->cpu_dai_drv.symmetric_rates = 1;
1073 sai->cpu_dai_drv.symmetric_channels = 1;
1074 sai->cpu_dai_drv.symmetric_samplebits = 1;
1075
1076 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
1077 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
1078 /* error out if both synchronous and asynchronous are present */
1079 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
1080 return -EINVAL;
1081 }
1082
1083 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
1084 /* Sync Rx with Tx */
1085 sai->synchronous[RX] = false;
1086 sai->synchronous[TX] = true;
1087 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
1088 /* Discard all settings for asynchronous mode */
1089 sai->synchronous[RX] = false;
1090 sai->synchronous[TX] = false;
1091 sai->cpu_dai_drv.symmetric_rates = 0;
1092 sai->cpu_dai_drv.symmetric_channels = 0;
1093 sai->cpu_dai_drv.symmetric_samplebits = 0;
1094 }
1095
1096 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
1097 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1098 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1099 if (IS_ERR(gpr)) {
1100 dev_err(&pdev->dev, "cannot find iomuxc registers\n");
1101 return PTR_ERR(gpr);
1102 }
1103
1104 index = of_alias_get_id(np, "sai");
1105 if (index < 0)
1106 return index;
1107
1108 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1109 MCLK_DIR(index));
1110 }
1111
1112 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
1113 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
1114 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
1115 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
1116
1117 platform_set_drvdata(pdev, sai);
1118
1119 /* Get sai version */
1120 ret = fsl_sai_check_version(&pdev->dev);
1121 if (ret < 0)
1122 dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret);
1123
1124 /* Select MCLK direction */
1125 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
1126 sai->verid.major >= 3 && sai->verid.minor >= 1) {
1127 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1128 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
1129 }
1130
1131 pm_runtime_enable(&pdev->dev);
1132 regcache_cache_only(sai->regmap, true);
1133
1134 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
1135 &sai->cpu_dai_drv, 1);
1136 if (ret)
1137 goto err_pm_disable;
1138
1139 if (sai->soc_data->use_imx_pcm) {
1140 ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
1141 if (ret)
1142 goto err_pm_disable;
1143 } else {
1144 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1145 if (ret)
1146 goto err_pm_disable;
1147 }
1148
1149 return ret;
1150
1151 err_pm_disable:
1152 pm_runtime_disable(&pdev->dev);
1153
1154 return ret;
1155 }
1156
fsl_sai_remove(struct platform_device * pdev)1157 static int fsl_sai_remove(struct platform_device *pdev)
1158 {
1159 pm_runtime_disable(&pdev->dev);
1160
1161 return 0;
1162 }
1163
1164 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1165 .use_imx_pcm = false,
1166 .use_edma = false,
1167 .fifo_depth = 32,
1168 .reg_offset = 0,
1169 };
1170
1171 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1172 .use_imx_pcm = true,
1173 .use_edma = false,
1174 .fifo_depth = 32,
1175 .reg_offset = 0,
1176 };
1177
1178 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1179 .use_imx_pcm = true,
1180 .use_edma = false,
1181 .fifo_depth = 16,
1182 .reg_offset = 8,
1183 };
1184
1185 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1186 .use_imx_pcm = true,
1187 .use_edma = false,
1188 .fifo_depth = 128,
1189 .reg_offset = 8,
1190 };
1191
1192 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1193 .use_imx_pcm = true,
1194 .use_edma = true,
1195 .fifo_depth = 64,
1196 .reg_offset = 0,
1197 };
1198
1199 static const struct of_device_id fsl_sai_ids[] = {
1200 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1201 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1202 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1203 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1204 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1205 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1206 { /* sentinel */ }
1207 };
1208 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1209
1210 #ifdef CONFIG_PM
fsl_sai_runtime_suspend(struct device * dev)1211 static int fsl_sai_runtime_suspend(struct device *dev)
1212 {
1213 struct fsl_sai *sai = dev_get_drvdata(dev);
1214
1215 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1216 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1217
1218 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1219 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1220
1221 clk_disable_unprepare(sai->bus_clk);
1222
1223 regcache_cache_only(sai->regmap, true);
1224
1225 return 0;
1226 }
1227
fsl_sai_runtime_resume(struct device * dev)1228 static int fsl_sai_runtime_resume(struct device *dev)
1229 {
1230 struct fsl_sai *sai = dev_get_drvdata(dev);
1231 unsigned int ofs = sai->soc_data->reg_offset;
1232 int ret;
1233
1234 ret = clk_prepare_enable(sai->bus_clk);
1235 if (ret) {
1236 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1237 return ret;
1238 }
1239
1240 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1241 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1242 if (ret)
1243 goto disable_bus_clk;
1244 }
1245
1246 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1247 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1248 if (ret)
1249 goto disable_tx_clk;
1250 }
1251
1252 regcache_cache_only(sai->regmap, false);
1253 regcache_mark_dirty(sai->regmap);
1254 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1255 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1256 usleep_range(1000, 2000);
1257 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1258 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1259
1260 ret = regcache_sync(sai->regmap);
1261 if (ret)
1262 goto disable_rx_clk;
1263
1264 return 0;
1265
1266 disable_rx_clk:
1267 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1268 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1269 disable_tx_clk:
1270 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1271 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1272 disable_bus_clk:
1273 clk_disable_unprepare(sai->bus_clk);
1274
1275 return ret;
1276 }
1277 #endif /* CONFIG_PM */
1278
1279 static const struct dev_pm_ops fsl_sai_pm_ops = {
1280 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1281 fsl_sai_runtime_resume, NULL)
1282 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1283 pm_runtime_force_resume)
1284 };
1285
1286 static struct platform_driver fsl_sai_driver = {
1287 .probe = fsl_sai_probe,
1288 .remove = fsl_sai_remove,
1289 .driver = {
1290 .name = "fsl-sai",
1291 .pm = &fsl_sai_pm_ops,
1292 .of_match_table = fsl_sai_ids,
1293 },
1294 };
1295 module_platform_driver(fsl_sai_driver);
1296
1297 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1298 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1299 MODULE_ALIAS("platform:fsl-sai");
1300 MODULE_LICENSE("GPL");
1301