1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/initval.h>
21 #include <sound/soc.h>
22 #include <sound/dmaengine_pcm.h>
23
24 #include "omap-mcbsp-priv.h"
25 #include "omap-mcbsp.h"
26 #include "sdma-pcm.h"
27
28 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
29
30 enum {
31 OMAP_MCBSP_WORD_8 = 0,
32 OMAP_MCBSP_WORD_12,
33 OMAP_MCBSP_WORD_16,
34 OMAP_MCBSP_WORD_20,
35 OMAP_MCBSP_WORD_24,
36 OMAP_MCBSP_WORD_32,
37 };
38
omap_mcbsp_dump_reg(struct omap_mcbsp * mcbsp)39 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
40 {
41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2));
43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1));
44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2));
45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1));
46 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
47 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
48 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2));
49 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1));
50 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2));
51 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1));
52 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
53 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
54 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0));
55 dev_dbg(mcbsp->dev, "***********************\n");
56 }
57
omap2_mcbsp_set_clks_src(struct omap_mcbsp * mcbsp,u8 fck_src_id)58 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
59 {
60 struct clk *fck_src;
61 const char *src;
62 int r;
63
64 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
65 src = "pad_fck";
66 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
67 src = "prcm_fck";
68 else
69 return -EINVAL;
70
71 fck_src = clk_get(mcbsp->dev, src);
72 if (IS_ERR(fck_src)) {
73 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
74 return -EINVAL;
75 }
76
77 if (mcbsp->active)
78 pm_runtime_put_sync(mcbsp->dev);
79
80 r = clk_set_parent(mcbsp->fclk, fck_src);
81 if (r)
82 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
83 src);
84
85 if (mcbsp->active)
86 pm_runtime_get_sync(mcbsp->dev);
87
88 clk_put(fck_src);
89
90 return r;
91 }
92
omap_mcbsp_irq_handler(int irq,void * data)93 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
94 {
95 struct omap_mcbsp *mcbsp = data;
96 u16 irqst;
97
98 irqst = MCBSP_READ(mcbsp, IRQST);
99 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
100
101 if (irqst & RSYNCERREN)
102 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
103 if (irqst & RFSREN)
104 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
105 if (irqst & REOFEN)
106 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
107 if (irqst & RRDYEN)
108 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
109 if (irqst & RUNDFLEN)
110 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
111 if (irqst & ROVFLEN)
112 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
113
114 if (irqst & XSYNCERREN)
115 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
116 if (irqst & XFSXEN)
117 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
118 if (irqst & XEOFEN)
119 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
120 if (irqst & XRDYEN)
121 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
122 if (irqst & XUNDFLEN)
123 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
124 if (irqst & XOVFLEN)
125 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
126 if (irqst & XEMPTYEOFEN)
127 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
128
129 MCBSP_WRITE(mcbsp, IRQST, irqst);
130
131 return IRQ_HANDLED;
132 }
133
omap_mcbsp_tx_irq_handler(int irq,void * data)134 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
135 {
136 struct omap_mcbsp *mcbsp = data;
137 u16 irqst_spcr2;
138
139 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
140 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
141
142 if (irqst_spcr2 & XSYNC_ERR) {
143 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
144 irqst_spcr2);
145 /* Writing zero to XSYNC_ERR clears the IRQ */
146 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
147 }
148
149 return IRQ_HANDLED;
150 }
151
omap_mcbsp_rx_irq_handler(int irq,void * data)152 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
153 {
154 struct omap_mcbsp *mcbsp = data;
155 u16 irqst_spcr1;
156
157 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
158 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
159
160 if (irqst_spcr1 & RSYNC_ERR) {
161 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
162 irqst_spcr1);
163 /* Writing zero to RSYNC_ERR clears the IRQ */
164 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
165 }
166
167 return IRQ_HANDLED;
168 }
169
170 /*
171 * omap_mcbsp_config simply write a config to the
172 * appropriate McBSP.
173 * You either call this function or set the McBSP registers
174 * by yourself before calling omap_mcbsp_start().
175 */
omap_mcbsp_config(struct omap_mcbsp * mcbsp,const struct omap_mcbsp_reg_cfg * config)176 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
177 const struct omap_mcbsp_reg_cfg *config)
178 {
179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp->id, mcbsp->phys_base);
181
182 /* We write the given config */
183 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
184 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
185 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
186 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
187 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
188 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
189 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
190 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
191 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
192 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
193 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
194 if (mcbsp->pdata->has_ccr) {
195 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
196 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
197 }
198 /* Enable wakeup behavior */
199 if (mcbsp->pdata->has_wakeup)
200 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
201
202 /* Enable TX/RX sync error interrupts by default */
203 if (mcbsp->irq)
204 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
205 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
206 }
207
208 /**
209 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
210 * @mcbsp: omap_mcbsp struct for the McBSP instance
211 * @stream: Stream direction (playback/capture)
212 *
213 * Returns the address of mcbsp data transmit register or data receive register
214 * to be used by DMA for transferring/receiving data
215 */
omap_mcbsp_dma_reg_params(struct omap_mcbsp * mcbsp,unsigned int stream)216 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
217 unsigned int stream)
218 {
219 int data_reg;
220
221 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
222 if (mcbsp->pdata->reg_size == 2)
223 data_reg = OMAP_MCBSP_REG_DXR1;
224 else
225 data_reg = OMAP_MCBSP_REG_DXR;
226 } else {
227 if (mcbsp->pdata->reg_size == 2)
228 data_reg = OMAP_MCBSP_REG_DRR1;
229 else
230 data_reg = OMAP_MCBSP_REG_DRR;
231 }
232
233 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
234 }
235
236 /*
237 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
238 * The threshold parameter is 1 based, and it is converted (threshold - 1)
239 * for the THRSH2 register.
240 */
omap_mcbsp_set_tx_threshold(struct omap_mcbsp * mcbsp,u16 threshold)241 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
242 {
243 if (threshold && threshold <= mcbsp->max_tx_thres)
244 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
245 }
246
247 /*
248 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
249 * The threshold parameter is 1 based, and it is converted (threshold - 1)
250 * for the THRSH1 register.
251 */
omap_mcbsp_set_rx_threshold(struct omap_mcbsp * mcbsp,u16 threshold)252 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
253 {
254 if (threshold && threshold <= mcbsp->max_rx_thres)
255 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
256 }
257
258 /*
259 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
260 */
omap_mcbsp_get_tx_delay(struct omap_mcbsp * mcbsp)261 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
262 {
263 u16 buffstat;
264
265 /* Returns the number of free locations in the buffer */
266 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
267
268 /* Number of slots are different in McBSP ports */
269 return mcbsp->pdata->buffer_size - buffstat;
270 }
271
272 /*
273 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
274 * to reach the threshold value (when the DMA will be triggered to read it)
275 */
omap_mcbsp_get_rx_delay(struct omap_mcbsp * mcbsp)276 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
277 {
278 u16 buffstat, threshold;
279
280 /* Returns the number of used locations in the buffer */
281 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
282 /* RX threshold */
283 threshold = MCBSP_READ(mcbsp, THRSH1);
284
285 /* Return the number of location till we reach the threshold limit */
286 if (threshold <= buffstat)
287 return 0;
288 else
289 return threshold - buffstat;
290 }
291
omap_mcbsp_request(struct omap_mcbsp * mcbsp)292 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
293 {
294 void *reg_cache;
295 int err;
296
297 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
298 if (!reg_cache)
299 return -ENOMEM;
300
301 spin_lock(&mcbsp->lock);
302 if (!mcbsp->free) {
303 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
304 err = -EBUSY;
305 goto err_kfree;
306 }
307
308 mcbsp->free = false;
309 mcbsp->reg_cache = reg_cache;
310 spin_unlock(&mcbsp->lock);
311
312 if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
313 mcbsp->pdata->ops->request(mcbsp->id - 1);
314
315 /*
316 * Make sure that transmitter, receiver and sample-rate generator are
317 * not running before activating IRQs.
318 */
319 MCBSP_WRITE(mcbsp, SPCR1, 0);
320 MCBSP_WRITE(mcbsp, SPCR2, 0);
321
322 if (mcbsp->irq) {
323 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
324 "McBSP", (void *)mcbsp);
325 if (err != 0) {
326 dev_err(mcbsp->dev, "Unable to request IRQ\n");
327 goto err_clk_disable;
328 }
329 } else {
330 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
331 "McBSP TX", (void *)mcbsp);
332 if (err != 0) {
333 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
334 goto err_clk_disable;
335 }
336
337 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
338 "McBSP RX", (void *)mcbsp);
339 if (err != 0) {
340 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
341 goto err_free_irq;
342 }
343 }
344
345 return 0;
346 err_free_irq:
347 free_irq(mcbsp->tx_irq, (void *)mcbsp);
348 err_clk_disable:
349 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
350 mcbsp->pdata->ops->free(mcbsp->id - 1);
351
352 /* Disable wakeup behavior */
353 if (mcbsp->pdata->has_wakeup)
354 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
355
356 spin_lock(&mcbsp->lock);
357 mcbsp->free = true;
358 mcbsp->reg_cache = NULL;
359 err_kfree:
360 spin_unlock(&mcbsp->lock);
361 kfree(reg_cache);
362
363 return err;
364 }
365
omap_mcbsp_free(struct omap_mcbsp * mcbsp)366 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
367 {
368 void *reg_cache;
369
370 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
371 mcbsp->pdata->ops->free(mcbsp->id - 1);
372
373 /* Disable wakeup behavior */
374 if (mcbsp->pdata->has_wakeup)
375 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
376
377 /* Disable interrupt requests */
378 if (mcbsp->irq)
379 MCBSP_WRITE(mcbsp, IRQEN, 0);
380
381 if (mcbsp->irq) {
382 free_irq(mcbsp->irq, (void *)mcbsp);
383 } else {
384 free_irq(mcbsp->rx_irq, (void *)mcbsp);
385 free_irq(mcbsp->tx_irq, (void *)mcbsp);
386 }
387
388 reg_cache = mcbsp->reg_cache;
389
390 /*
391 * Select CLKS source from internal source unconditionally before
392 * marking the McBSP port as free.
393 * If the external clock source via MCBSP_CLKS pin has been selected the
394 * system will refuse to enter idle if the CLKS pin source is not reset
395 * back to internal source.
396 */
397 if (!mcbsp_omap1())
398 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
399
400 spin_lock(&mcbsp->lock);
401 if (mcbsp->free)
402 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
403 else
404 mcbsp->free = true;
405 mcbsp->reg_cache = NULL;
406 spin_unlock(&mcbsp->lock);
407
408 kfree(reg_cache);
409 }
410
411 /*
412 * Here we start the McBSP, by enabling transmitter, receiver or both.
413 * If no transmitter or receiver is active prior calling, then sample-rate
414 * generator and frame sync are started.
415 */
omap_mcbsp_start(struct omap_mcbsp * mcbsp,int stream)416 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
417 {
418 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
419 int rx = !tx;
420 int enable_srg = 0;
421 u16 w;
422
423 if (mcbsp->st_data)
424 omap_mcbsp_st_start(mcbsp);
425
426 /* Only enable SRG, if McBSP is master */
427 w = MCBSP_READ_CACHE(mcbsp, PCR0);
428 if (w & (FSXM | FSRM | CLKXM | CLKRM))
429 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
430 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
431
432 if (enable_srg) {
433 /* Start the sample generator */
434 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
435 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
436 }
437
438 /* Enable transmitter and receiver */
439 tx &= 1;
440 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
441 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
442
443 rx &= 1;
444 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
445 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
446
447 /*
448 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
449 * REVISIT: 100us may give enough time for two CLKSRG, however
450 * due to some unknown PM related, clock gating etc. reason it
451 * is now at 500us.
452 */
453 udelay(500);
454
455 if (enable_srg) {
456 /* Start frame sync */
457 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
458 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
459 }
460
461 if (mcbsp->pdata->has_ccr) {
462 /* Release the transmitter and receiver */
463 w = MCBSP_READ_CACHE(mcbsp, XCCR);
464 w &= ~(tx ? XDISABLE : 0);
465 MCBSP_WRITE(mcbsp, XCCR, w);
466 w = MCBSP_READ_CACHE(mcbsp, RCCR);
467 w &= ~(rx ? RDISABLE : 0);
468 MCBSP_WRITE(mcbsp, RCCR, w);
469 }
470
471 /* Dump McBSP Regs */
472 omap_mcbsp_dump_reg(mcbsp);
473 }
474
omap_mcbsp_stop(struct omap_mcbsp * mcbsp,int stream)475 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
476 {
477 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
478 int rx = !tx;
479 int idle;
480 u16 w;
481
482 /* Reset transmitter */
483 tx &= 1;
484 if (mcbsp->pdata->has_ccr) {
485 w = MCBSP_READ_CACHE(mcbsp, XCCR);
486 w |= (tx ? XDISABLE : 0);
487 MCBSP_WRITE(mcbsp, XCCR, w);
488 }
489 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
490 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
491
492 /* Reset receiver */
493 rx &= 1;
494 if (mcbsp->pdata->has_ccr) {
495 w = MCBSP_READ_CACHE(mcbsp, RCCR);
496 w |= (rx ? RDISABLE : 0);
497 MCBSP_WRITE(mcbsp, RCCR, w);
498 }
499 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
500 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
501
502 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
503 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
504
505 if (idle) {
506 /* Reset the sample rate generator */
507 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
508 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
509 }
510
511 if (mcbsp->st_data)
512 omap_mcbsp_st_stop(mcbsp);
513 }
514
515 #define max_thres(m) (mcbsp->pdata->buffer_size)
516 #define valid_threshold(m, val) ((val) <= max_thres(m))
517 #define THRESHOLD_PROP_BUILDER(prop) \
518 static ssize_t prop##_show(struct device *dev, \
519 struct device_attribute *attr, char *buf) \
520 { \
521 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
522 \
523 return sprintf(buf, "%u\n", mcbsp->prop); \
524 } \
525 \
526 static ssize_t prop##_store(struct device *dev, \
527 struct device_attribute *attr, \
528 const char *buf, size_t size) \
529 { \
530 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
531 unsigned long val; \
532 int status; \
533 \
534 status = kstrtoul(buf, 0, &val); \
535 if (status) \
536 return status; \
537 \
538 if (!valid_threshold(mcbsp, val)) \
539 return -EDOM; \
540 \
541 mcbsp->prop = val; \
542 return size; \
543 } \
544 \
545 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store)
546
547 THRESHOLD_PROP_BUILDER(max_tx_thres);
548 THRESHOLD_PROP_BUILDER(max_rx_thres);
549
550 static const char * const dma_op_modes[] = {
551 "element", "threshold",
552 };
553
dma_op_mode_show(struct device * dev,struct device_attribute * attr,char * buf)554 static ssize_t dma_op_mode_show(struct device *dev,
555 struct device_attribute *attr, char *buf)
556 {
557 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
558 int dma_op_mode, i = 0;
559 ssize_t len = 0;
560 const char * const *s;
561
562 dma_op_mode = mcbsp->dma_op_mode;
563
564 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
565 if (dma_op_mode == i)
566 len += sprintf(buf + len, "[%s] ", *s);
567 else
568 len += sprintf(buf + len, "%s ", *s);
569 }
570 len += sprintf(buf + len, "\n");
571
572 return len;
573 }
574
dma_op_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)575 static ssize_t dma_op_mode_store(struct device *dev,
576 struct device_attribute *attr, const char *buf,
577 size_t size)
578 {
579 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
580 int i;
581
582 i = sysfs_match_string(dma_op_modes, buf);
583 if (i < 0)
584 return i;
585
586 spin_lock_irq(&mcbsp->lock);
587 if (!mcbsp->free) {
588 size = -EBUSY;
589 goto unlock;
590 }
591 mcbsp->dma_op_mode = i;
592
593 unlock:
594 spin_unlock_irq(&mcbsp->lock);
595
596 return size;
597 }
598
599 static DEVICE_ATTR_RW(dma_op_mode);
600
601 static const struct attribute *additional_attrs[] = {
602 &dev_attr_max_tx_thres.attr,
603 &dev_attr_max_rx_thres.attr,
604 &dev_attr_dma_op_mode.attr,
605 NULL,
606 };
607
608 static const struct attribute_group additional_attr_group = {
609 .attrs = (struct attribute **)additional_attrs,
610 };
611
612 /*
613 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
614 * 730 has only 2 McBSP, and both of them are MPU peripherals.
615 */
omap_mcbsp_init(struct platform_device * pdev)616 static int omap_mcbsp_init(struct platform_device *pdev)
617 {
618 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
619 struct resource *res;
620 int ret = 0;
621
622 spin_lock_init(&mcbsp->lock);
623 mcbsp->free = true;
624
625 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
626 if (!res)
627 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
628
629 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
630 if (IS_ERR(mcbsp->io_base))
631 return PTR_ERR(mcbsp->io_base);
632
633 mcbsp->phys_base = res->start;
634 mcbsp->reg_cache_size = resource_size(res);
635
636 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
637 if (!res)
638 mcbsp->phys_dma_base = mcbsp->phys_base;
639 else
640 mcbsp->phys_dma_base = res->start;
641
642 /*
643 * OMAP1, 2 uses two interrupt lines: TX, RX
644 * OMAP2430, OMAP3 SoC have combined IRQ line as well.
645 * OMAP4 and newer SoC only have the combined IRQ line.
646 * Use the combined IRQ if available since it gives better debugging
647 * possibilities.
648 */
649 mcbsp->irq = platform_get_irq_byname(pdev, "common");
650 if (mcbsp->irq == -ENXIO) {
651 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
652
653 if (mcbsp->tx_irq == -ENXIO) {
654 mcbsp->irq = platform_get_irq(pdev, 0);
655 mcbsp->tx_irq = 0;
656 } else {
657 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
658 mcbsp->irq = 0;
659 }
660 }
661
662 if (!pdev->dev.of_node) {
663 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
664 if (!res) {
665 dev_err(&pdev->dev, "invalid tx DMA channel\n");
666 return -ENODEV;
667 }
668 mcbsp->dma_req[0] = res->start;
669 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
670
671 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
672 if (!res) {
673 dev_err(&pdev->dev, "invalid rx DMA channel\n");
674 return -ENODEV;
675 }
676 mcbsp->dma_req[1] = res->start;
677 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
678 } else {
679 mcbsp->dma_data[0].filter_data = "tx";
680 mcbsp->dma_data[1].filter_data = "rx";
681 }
682
683 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
684 SNDRV_PCM_STREAM_PLAYBACK);
685 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
686 SNDRV_PCM_STREAM_CAPTURE);
687
688 mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
689 if (IS_ERR(mcbsp->fclk)) {
690 ret = PTR_ERR(mcbsp->fclk);
691 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
692 return ret;
693 }
694
695 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
696 if (mcbsp->pdata->buffer_size) {
697 /*
698 * Initially configure the maximum thresholds to a safe value.
699 * The McBSP FIFO usage with these values should not go under
700 * 16 locations.
701 * If the whole FIFO without safety buffer is used, than there
702 * is a possibility that the DMA will be not able to push the
703 * new data on time, causing channel shifts in runtime.
704 */
705 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
706 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
707
708 ret = sysfs_create_group(&mcbsp->dev->kobj,
709 &additional_attr_group);
710 if (ret) {
711 dev_err(mcbsp->dev,
712 "Unable to create additional controls\n");
713 return ret;
714 }
715 }
716
717 ret = omap_mcbsp_st_init(pdev);
718 if (ret)
719 goto err_st;
720
721 return 0;
722
723 err_st:
724 if (mcbsp->pdata->buffer_size)
725 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
726 return ret;
727 }
728
729 /*
730 * Stream DMA parameters. DMA request line and port address are set runtime
731 * since they are different between OMAP1 and later OMAPs
732 */
omap_mcbsp_set_threshold(struct snd_pcm_substream * substream,unsigned int packet_size)733 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
734 unsigned int packet_size)
735 {
736 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
737 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
738 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
739 int words;
740
741 /* No need to proceed further if McBSP does not have FIFO */
742 if (mcbsp->pdata->buffer_size == 0)
743 return;
744
745 /*
746 * Configure McBSP threshold based on either:
747 * packet_size, when the sDMA is in packet mode, or based on the
748 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
749 * for mono streams.
750 */
751 if (packet_size)
752 words = packet_size;
753 else
754 words = 1;
755
756 /* Configure McBSP internal buffer usage */
757 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
758 omap_mcbsp_set_tx_threshold(mcbsp, words);
759 else
760 omap_mcbsp_set_rx_threshold(mcbsp, words);
761 }
762
omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)763 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
764 struct snd_pcm_hw_rule *rule)
765 {
766 struct snd_interval *buffer_size = hw_param_interval(params,
767 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
768 struct snd_interval *channels = hw_param_interval(params,
769 SNDRV_PCM_HW_PARAM_CHANNELS);
770 struct omap_mcbsp *mcbsp = rule->private;
771 struct snd_interval frames;
772 int size;
773
774 snd_interval_any(&frames);
775 size = mcbsp->pdata->buffer_size;
776
777 frames.min = size / channels->min;
778 frames.integer = 1;
779 return snd_interval_refine(buffer_size, &frames);
780 }
781
omap_mcbsp_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)782 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
783 struct snd_soc_dai *cpu_dai)
784 {
785 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
786 int err = 0;
787
788 if (!snd_soc_dai_active(cpu_dai))
789 err = omap_mcbsp_request(mcbsp);
790
791 /*
792 * OMAP3 McBSP FIFO is word structured.
793 * McBSP2 has 1024 + 256 = 1280 word long buffer,
794 * McBSP1,3,4,5 has 128 word long buffer
795 * This means that the size of the FIFO depends on the sample format.
796 * For example on McBSP3:
797 * 16bit samples: size is 128 * 2 = 256 bytes
798 * 32bit samples: size is 128 * 4 = 512 bytes
799 * It is simpler to place constraint for buffer and period based on
800 * channels.
801 * McBSP3 as example again (16 or 32 bit samples):
802 * 1 channel (mono): size is 128 frames (128 words)
803 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
804 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
805 */
806 if (mcbsp->pdata->buffer_size) {
807 /*
808 * Rule for the buffer size. We should not allow
809 * smaller buffer than the FIFO size to avoid underruns.
810 * This applies only for the playback stream.
811 */
812 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
813 snd_pcm_hw_rule_add(substream->runtime, 0,
814 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
815 omap_mcbsp_hwrule_min_buffersize,
816 mcbsp,
817 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
818
819 /* Make sure, that the period size is always even */
820 snd_pcm_hw_constraint_step(substream->runtime, 0,
821 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
822 }
823
824 return err;
825 }
826
omap_mcbsp_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)827 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
828 struct snd_soc_dai *cpu_dai)
829 {
830 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
831 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
832 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
833 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
834
835 if (mcbsp->latency[stream2])
836 cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
837 mcbsp->latency[stream2]);
838 else if (mcbsp->latency[stream1])
839 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
840
841 mcbsp->latency[stream1] = 0;
842
843 if (!snd_soc_dai_active(cpu_dai)) {
844 omap_mcbsp_free(mcbsp);
845 mcbsp->configured = 0;
846 }
847 }
848
omap_mcbsp_dai_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)849 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
850 struct snd_soc_dai *cpu_dai)
851 {
852 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
853 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
854 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
855 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
856 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
857 int latency = mcbsp->latency[stream2];
858
859 /* Prevent omap hardware from hitting off between FIFO fills */
860 if (!latency || mcbsp->latency[stream1] < latency)
861 latency = mcbsp->latency[stream1];
862
863 if (cpu_latency_qos_request_active(pm_qos_req))
864 cpu_latency_qos_update_request(pm_qos_req, latency);
865 else if (latency)
866 cpu_latency_qos_add_request(pm_qos_req, latency);
867
868 return 0;
869 }
870
omap_mcbsp_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)871 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
872 struct snd_soc_dai *cpu_dai)
873 {
874 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
875
876 switch (cmd) {
877 case SNDRV_PCM_TRIGGER_START:
878 case SNDRV_PCM_TRIGGER_RESUME:
879 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
880 mcbsp->active++;
881 omap_mcbsp_start(mcbsp, substream->stream);
882 break;
883
884 case SNDRV_PCM_TRIGGER_STOP:
885 case SNDRV_PCM_TRIGGER_SUSPEND:
886 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
887 omap_mcbsp_stop(mcbsp, substream->stream);
888 mcbsp->active--;
889 break;
890 default:
891 return -EINVAL;
892 }
893
894 return 0;
895 }
896
omap_mcbsp_dai_delay(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)897 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
898 struct snd_pcm_substream *substream,
899 struct snd_soc_dai *dai)
900 {
901 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
902 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
903 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
904 u16 fifo_use;
905 snd_pcm_sframes_t delay;
906
907 /* No need to proceed further if McBSP does not have FIFO */
908 if (mcbsp->pdata->buffer_size == 0)
909 return 0;
910
911 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
912 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
913 else
914 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
915
916 /*
917 * Divide the used locations with the channel count to get the
918 * FIFO usage in samples (don't care about partial samples in the
919 * buffer).
920 */
921 delay = fifo_use / substream->runtime->channels;
922
923 return delay;
924 }
925
omap_mcbsp_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)926 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
927 struct snd_pcm_hw_params *params,
928 struct snd_soc_dai *cpu_dai)
929 {
930 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
931 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
932 struct snd_dmaengine_dai_dma_data *dma_data;
933 int wlen, channels, wpf;
934 int pkt_size = 0;
935 unsigned int format, div, framesize, master;
936 unsigned int buffer_size = mcbsp->pdata->buffer_size;
937
938 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
939 channels = params_channels(params);
940
941 switch (params_format(params)) {
942 case SNDRV_PCM_FORMAT_S16_LE:
943 wlen = 16;
944 break;
945 case SNDRV_PCM_FORMAT_S32_LE:
946 wlen = 32;
947 break;
948 default:
949 return -EINVAL;
950 }
951 if (buffer_size) {
952 int latency;
953
954 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
955 int period_words, max_thrsh;
956 int divider = 0;
957
958 period_words = params_period_bytes(params) / (wlen / 8);
959 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
960 max_thrsh = mcbsp->max_tx_thres;
961 else
962 max_thrsh = mcbsp->max_rx_thres;
963 /*
964 * Use sDMA packet mode if McBSP is in threshold mode:
965 * If period words less than the FIFO size the packet
966 * size is set to the number of period words, otherwise
967 * Look for the biggest threshold value which divides
968 * the period size evenly.
969 */
970 divider = period_words / max_thrsh;
971 if (period_words % max_thrsh)
972 divider++;
973 while (period_words % divider &&
974 divider < period_words)
975 divider++;
976 if (divider == period_words)
977 return -EINVAL;
978
979 pkt_size = period_words / divider;
980 } else if (channels > 1) {
981 /* Use packet mode for non mono streams */
982 pkt_size = channels;
983 }
984
985 latency = (buffer_size - pkt_size) / channels;
986 latency = latency * USEC_PER_SEC /
987 (params->rate_num / params->rate_den);
988 mcbsp->latency[substream->stream] = latency;
989
990 omap_mcbsp_set_threshold(substream, pkt_size);
991 }
992
993 dma_data->maxburst = pkt_size;
994
995 if (mcbsp->configured) {
996 /* McBSP already configured by another stream */
997 return 0;
998 }
999
1000 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
1001 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
1002 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
1003 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
1004 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1005 wpf = channels;
1006 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
1007 format == SND_SOC_DAIFMT_LEFT_J)) {
1008 /* Use dual-phase frames */
1009 regs->rcr2 |= RPHASE;
1010 regs->xcr2 |= XPHASE;
1011 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
1012 wpf--;
1013 regs->rcr2 |= RFRLEN2(wpf - 1);
1014 regs->xcr2 |= XFRLEN2(wpf - 1);
1015 }
1016
1017 regs->rcr1 |= RFRLEN1(wpf - 1);
1018 regs->xcr1 |= XFRLEN1(wpf - 1);
1019
1020 switch (params_format(params)) {
1021 case SNDRV_PCM_FORMAT_S16_LE:
1022 /* Set word lengths */
1023 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
1024 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
1025 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
1026 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
1027 break;
1028 case SNDRV_PCM_FORMAT_S32_LE:
1029 /* Set word lengths */
1030 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
1031 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
1032 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
1033 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
1034 break;
1035 default:
1036 /* Unsupported PCM format */
1037 return -EINVAL;
1038 }
1039
1040 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
1041 * by _counting_ BCLKs. Calculate frame size in BCLKs */
1042 master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
1043 if (master == SND_SOC_DAIFMT_CBS_CFS) {
1044 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
1045 framesize = (mcbsp->in_freq / div) / params_rate(params);
1046
1047 if (framesize < wlen * channels) {
1048 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
1049 "channels\n", __func__);
1050 return -EINVAL;
1051 }
1052 } else
1053 framesize = wlen * channels;
1054
1055 /* Set FS period and length in terms of bit clock periods */
1056 regs->srgr2 &= ~FPER(0xfff);
1057 regs->srgr1 &= ~FWID(0xff);
1058 switch (format) {
1059 case SND_SOC_DAIFMT_I2S:
1060 case SND_SOC_DAIFMT_LEFT_J:
1061 regs->srgr2 |= FPER(framesize - 1);
1062 regs->srgr1 |= FWID((framesize >> 1) - 1);
1063 break;
1064 case SND_SOC_DAIFMT_DSP_A:
1065 case SND_SOC_DAIFMT_DSP_B:
1066 regs->srgr2 |= FPER(framesize - 1);
1067 regs->srgr1 |= FWID(0);
1068 break;
1069 }
1070
1071 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
1072 mcbsp->wlen = wlen;
1073 mcbsp->configured = 1;
1074
1075 return 0;
1076 }
1077
1078 /*
1079 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
1080 * cache is initialized here
1081 */
omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)1082 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
1083 unsigned int fmt)
1084 {
1085 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1086 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1087 bool inv_fs = false;
1088
1089 if (mcbsp->configured)
1090 return 0;
1091
1092 mcbsp->fmt = fmt;
1093 memset(regs, 0, sizeof(*regs));
1094 /* Generic McBSP register settings */
1095 regs->spcr2 |= XINTM(3) | FREE;
1096 regs->spcr1 |= RINTM(3);
1097 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
1098 if (!mcbsp->pdata->has_ccr) {
1099 regs->rcr2 |= RFIG;
1100 regs->xcr2 |= XFIG;
1101 }
1102
1103 /* Configure XCCR/RCCR only for revisions which have ccr registers */
1104 if (mcbsp->pdata->has_ccr) {
1105 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
1106 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
1107 }
1108
1109 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1110 case SND_SOC_DAIFMT_I2S:
1111 /* 1-bit data delay */
1112 regs->rcr2 |= RDATDLY(1);
1113 regs->xcr2 |= XDATDLY(1);
1114 break;
1115 case SND_SOC_DAIFMT_LEFT_J:
1116 /* 0-bit data delay */
1117 regs->rcr2 |= RDATDLY(0);
1118 regs->xcr2 |= XDATDLY(0);
1119 regs->spcr1 |= RJUST(2);
1120 /* Invert FS polarity configuration */
1121 inv_fs = true;
1122 break;
1123 case SND_SOC_DAIFMT_DSP_A:
1124 /* 1-bit data delay */
1125 regs->rcr2 |= RDATDLY(1);
1126 regs->xcr2 |= XDATDLY(1);
1127 /* Invert FS polarity configuration */
1128 inv_fs = true;
1129 break;
1130 case SND_SOC_DAIFMT_DSP_B:
1131 /* 0-bit data delay */
1132 regs->rcr2 |= RDATDLY(0);
1133 regs->xcr2 |= XDATDLY(0);
1134 /* Invert FS polarity configuration */
1135 inv_fs = true;
1136 break;
1137 default:
1138 /* Unsupported data format */
1139 return -EINVAL;
1140 }
1141
1142 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1143 case SND_SOC_DAIFMT_CBS_CFS:
1144 /* McBSP master. Set FS and bit clocks as outputs */
1145 regs->pcr0 |= FSXM | FSRM |
1146 CLKXM | CLKRM;
1147 /* Sample rate generator drives the FS */
1148 regs->srgr2 |= FSGM;
1149 break;
1150 case SND_SOC_DAIFMT_CBM_CFS:
1151 /* McBSP slave. FS clock as output */
1152 regs->srgr2 |= FSGM;
1153 regs->pcr0 |= FSXM | FSRM;
1154 break;
1155 case SND_SOC_DAIFMT_CBM_CFM:
1156 /* McBSP slave */
1157 break;
1158 default:
1159 /* Unsupported master/slave configuration */
1160 return -EINVAL;
1161 }
1162
1163 /* Set bit clock (CLKX/CLKR) and FS polarities */
1164 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1165 case SND_SOC_DAIFMT_NB_NF:
1166 /*
1167 * Normal BCLK + FS.
1168 * FS active low. TX data driven on falling edge of bit clock
1169 * and RX data sampled on rising edge of bit clock.
1170 */
1171 regs->pcr0 |= FSXP | FSRP |
1172 CLKXP | CLKRP;
1173 break;
1174 case SND_SOC_DAIFMT_NB_IF:
1175 regs->pcr0 |= CLKXP | CLKRP;
1176 break;
1177 case SND_SOC_DAIFMT_IB_NF:
1178 regs->pcr0 |= FSXP | FSRP;
1179 break;
1180 case SND_SOC_DAIFMT_IB_IF:
1181 break;
1182 default:
1183 return -EINVAL;
1184 }
1185 if (inv_fs)
1186 regs->pcr0 ^= FSXP | FSRP;
1187
1188 return 0;
1189 }
1190
omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)1191 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
1192 int div_id, int div)
1193 {
1194 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1195 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1196
1197 if (div_id != OMAP_MCBSP_CLKGDV)
1198 return -ENODEV;
1199
1200 mcbsp->clk_div = div;
1201 regs->srgr1 &= ~CLKGDV(0xff);
1202 regs->srgr1 |= CLKGDV(div - 1);
1203
1204 return 0;
1205 }
1206
omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)1207 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
1208 int clk_id, unsigned int freq,
1209 int dir)
1210 {
1211 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
1212 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
1213 int err = 0;
1214
1215 if (mcbsp->active) {
1216 if (freq == mcbsp->in_freq)
1217 return 0;
1218 else
1219 return -EBUSY;
1220 }
1221
1222 mcbsp->in_freq = freq;
1223 regs->srgr2 &= ~CLKSM;
1224 regs->pcr0 &= ~SCLKME;
1225
1226 switch (clk_id) {
1227 case OMAP_MCBSP_SYSCLK_CLK:
1228 regs->srgr2 |= CLKSM;
1229 break;
1230 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
1231 if (mcbsp_omap1()) {
1232 err = -EINVAL;
1233 break;
1234 }
1235 err = omap2_mcbsp_set_clks_src(mcbsp,
1236 MCBSP_CLKS_PRCM_SRC);
1237 break;
1238 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
1239 if (mcbsp_omap1()) {
1240 err = 0;
1241 break;
1242 }
1243 err = omap2_mcbsp_set_clks_src(mcbsp,
1244 MCBSP_CLKS_PAD_SRC);
1245 break;
1246
1247 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
1248 regs->srgr2 |= CLKSM;
1249 regs->pcr0 |= SCLKME;
1250 /*
1251 * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
1252 * disable output on those pins. This enables to inject the
1253 * reference clock through CLKX/CLKR. For this to work
1254 * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
1255 */
1256 regs->pcr0 &= ~CLKXM;
1257 break;
1258 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
1259 regs->pcr0 |= SCLKME;
1260 /* Disable ouput on CLKR pin in master mode */
1261 regs->pcr0 &= ~CLKRM;
1262 break;
1263 default:
1264 err = -ENODEV;
1265 }
1266
1267 return err;
1268 }
1269
1270 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
1271 .startup = omap_mcbsp_dai_startup,
1272 .shutdown = omap_mcbsp_dai_shutdown,
1273 .prepare = omap_mcbsp_dai_prepare,
1274 .trigger = omap_mcbsp_dai_trigger,
1275 .delay = omap_mcbsp_dai_delay,
1276 .hw_params = omap_mcbsp_dai_hw_params,
1277 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
1278 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
1279 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
1280 };
1281
omap_mcbsp_probe(struct snd_soc_dai * dai)1282 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
1283 {
1284 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1285
1286 pm_runtime_enable(mcbsp->dev);
1287
1288 snd_soc_dai_init_dma_data(dai,
1289 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
1290 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
1291
1292 return 0;
1293 }
1294
omap_mcbsp_remove(struct snd_soc_dai * dai)1295 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
1296 {
1297 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
1298
1299 pm_runtime_disable(mcbsp->dev);
1300
1301 return 0;
1302 }
1303
1304 static struct snd_soc_dai_driver omap_mcbsp_dai = {
1305 .probe = omap_mcbsp_probe,
1306 .remove = omap_mcbsp_remove,
1307 .playback = {
1308 .channels_min = 1,
1309 .channels_max = 16,
1310 .rates = OMAP_MCBSP_RATES,
1311 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1312 },
1313 .capture = {
1314 .channels_min = 1,
1315 .channels_max = 16,
1316 .rates = OMAP_MCBSP_RATES,
1317 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1318 },
1319 .ops = &mcbsp_dai_ops,
1320 };
1321
1322 static const struct snd_soc_component_driver omap_mcbsp_component = {
1323 .name = "omap-mcbsp",
1324 };
1325
1326 static struct omap_mcbsp_platform_data omap2420_pdata = {
1327 .reg_step = 4,
1328 .reg_size = 2,
1329 };
1330
1331 static struct omap_mcbsp_platform_data omap2430_pdata = {
1332 .reg_step = 4,
1333 .reg_size = 4,
1334 .has_ccr = true,
1335 };
1336
1337 static struct omap_mcbsp_platform_data omap3_pdata = {
1338 .reg_step = 4,
1339 .reg_size = 4,
1340 .has_ccr = true,
1341 .has_wakeup = true,
1342 };
1343
1344 static struct omap_mcbsp_platform_data omap4_pdata = {
1345 .reg_step = 4,
1346 .reg_size = 4,
1347 .has_ccr = true,
1348 .has_wakeup = true,
1349 };
1350
1351 static const struct of_device_id omap_mcbsp_of_match[] = {
1352 {
1353 .compatible = "ti,omap2420-mcbsp",
1354 .data = &omap2420_pdata,
1355 },
1356 {
1357 .compatible = "ti,omap2430-mcbsp",
1358 .data = &omap2430_pdata,
1359 },
1360 {
1361 .compatible = "ti,omap3-mcbsp",
1362 .data = &omap3_pdata,
1363 },
1364 {
1365 .compatible = "ti,omap4-mcbsp",
1366 .data = &omap4_pdata,
1367 },
1368 { },
1369 };
1370 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
1371
asoc_mcbsp_probe(struct platform_device * pdev)1372 static int asoc_mcbsp_probe(struct platform_device *pdev)
1373 {
1374 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
1375 struct omap_mcbsp *mcbsp;
1376 const struct of_device_id *match;
1377 int ret;
1378
1379 match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
1380 if (match) {
1381 struct device_node *node = pdev->dev.of_node;
1382 struct omap_mcbsp_platform_data *pdata_quirk = pdata;
1383 int buffer_size;
1384
1385 pdata = devm_kzalloc(&pdev->dev,
1386 sizeof(struct omap_mcbsp_platform_data),
1387 GFP_KERNEL);
1388 if (!pdata)
1389 return -ENOMEM;
1390
1391 memcpy(pdata, match->data, sizeof(*pdata));
1392 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
1393 pdata->buffer_size = buffer_size;
1394 if (pdata_quirk)
1395 pdata->force_ick_on = pdata_quirk->force_ick_on;
1396 } else if (!pdata) {
1397 dev_err(&pdev->dev, "missing platform data.\n");
1398 return -EINVAL;
1399 }
1400 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
1401 if (!mcbsp)
1402 return -ENOMEM;
1403
1404 mcbsp->id = pdev->id;
1405 mcbsp->pdata = pdata;
1406 mcbsp->dev = &pdev->dev;
1407 platform_set_drvdata(pdev, mcbsp);
1408
1409 ret = omap_mcbsp_init(pdev);
1410 if (ret)
1411 return ret;
1412
1413 if (mcbsp->pdata->reg_size == 2) {
1414 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1415 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1416 }
1417
1418 ret = devm_snd_soc_register_component(&pdev->dev,
1419 &omap_mcbsp_component,
1420 &omap_mcbsp_dai, 1);
1421 if (ret)
1422 return ret;
1423
1424 return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
1425 }
1426
asoc_mcbsp_remove(struct platform_device * pdev)1427 static int asoc_mcbsp_remove(struct platform_device *pdev)
1428 {
1429 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1430
1431 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
1432 mcbsp->pdata->ops->free(mcbsp->id);
1433
1434 if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
1435 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
1436
1437 if (mcbsp->pdata->buffer_size)
1438 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1439
1440 omap_mcbsp_st_cleanup(pdev);
1441
1442 return 0;
1443 }
1444
1445 static struct platform_driver asoc_mcbsp_driver = {
1446 .driver = {
1447 .name = "omap-mcbsp",
1448 .of_match_table = omap_mcbsp_of_match,
1449 },
1450
1451 .probe = asoc_mcbsp_probe,
1452 .remove = asoc_mcbsp_remove,
1453 };
1454
1455 module_platform_driver(asoc_mcbsp_driver);
1456
1457 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
1458 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
1459 MODULE_LICENSE("GPL");
1460 MODULE_ALIAS("platform:omap-mcbsp");
1461