• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1[
2    {
3        "ArchStdEvent": "L1D_CACHE_RD"
4    },
5    {
6        "ArchStdEvent": "L1D_CACHE_WR"
7    },
8    {
9        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
10    },
11    {
12        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
13    },
14    {
15        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
16    },
17    {
18        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
19    },
20    {
21        "ArchStdEvent": "L1D_CACHE_INVAL"
22    },
23    {
24        "ArchStdEvent": "L1D_TLB_REFILL_RD"
25    },
26    {
27        "ArchStdEvent": "L1D_TLB_REFILL_WR"
28    },
29    {
30        "ArchStdEvent": "L2D_CACHE_RD"
31    },
32    {
33        "ArchStdEvent": "L2D_CACHE_WR"
34    },
35    {
36        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
37    },
38    {
39        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
40    },
41    {
42        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
43    },
44    {
45        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
46    },
47    {
48        "ArchStdEvent": "L2D_CACHE_INVAL"
49    },
50    {
51        "ArchStdEvent": "BUS_ACCESS_RD"
52    },
53    {
54        "ArchStdEvent": "BUS_ACCESS_WR"
55    },
56    {
57        "ArchStdEvent": "BUS_ACCESS_SHARED"
58    },
59    {
60        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED"
61    },
62    {
63        "ArchStdEvent": "BUS_ACCESS_NORMAL"
64    },
65    {
66        "ArchStdEvent": "BUS_ACCESS_PERIPH"
67    },
68    {
69        "ArchStdEvent": "MEM_ACCESS_RD"
70    },
71    {
72        "ArchStdEvent": "MEM_ACCESS_WR"
73    },
74    {
75        "ArchStdEvent": "UNALIGNED_LD_SPEC"
76    },
77    {
78        "ArchStdEvent": "UNALIGNED_ST_SPEC"
79    },
80    {
81        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
82    },
83    {
84        "ArchStdEvent": "LDREX_SPEC"
85    },
86    {
87        "ArchStdEvent": "STREX_PASS_SPEC"
88    },
89    {
90        "ArchStdEvent": "STREX_FAIL_SPEC"
91    },
92    {
93        "ArchStdEvent": "LD_SPEC"
94    },
95    {
96        "ArchStdEvent": "ST_SPEC"
97    },
98    {
99        "ArchStdEvent": "LDST_SPEC"
100    },
101    {
102        "ArchStdEvent": "DP_SPEC"
103    },
104    {
105        "ArchStdEvent": "ASE_SPEC"
106    },
107    {
108        "ArchStdEvent": "VFP_SPEC"
109    },
110    {
111        "ArchStdEvent": "PC_WRITE_SPEC"
112    },
113    {
114        "ArchStdEvent": "CRYPTO_SPEC"
115    },
116    {
117        "ArchStdEvent": "BR_IMMED_SPEC"
118    },
119    {
120        "ArchStdEvent": "BR_RETURN_SPEC"
121    },
122    {
123        "ArchStdEvent": "BR_INDIRECT_SPEC"
124    },
125    {
126        "ArchStdEvent": "ISB_SPEC"
127    },
128    {
129        "ArchStdEvent": "DSB_SPEC"
130    },
131    {
132        "ArchStdEvent": "DMB_SPEC"
133    },
134    {
135        "ArchStdEvent": "EXC_UNDEF"
136    },
137    {
138        "ArchStdEvent": "EXC_SVC"
139    },
140    {
141        "ArchStdEvent": "EXC_PABORT"
142    },
143    {
144        "ArchStdEvent": "EXC_DABORT"
145    },
146    {
147        "ArchStdEvent": "EXC_IRQ"
148    },
149    {
150        "ArchStdEvent": "EXC_FIQ"
151    },
152    {
153        "ArchStdEvent": "EXC_SMC"
154    },
155    {
156        "ArchStdEvent": "EXC_HVC"
157    },
158    {
159        "ArchStdEvent": "EXC_TRAP_PABORT"
160    },
161    {
162        "ArchStdEvent": "EXC_TRAP_DABORT"
163    },
164    {
165        "ArchStdEvent": "EXC_TRAP_OTHER"
166    },
167    {
168        "ArchStdEvent": "EXC_TRAP_IRQ"
169    },
170    {
171        "ArchStdEvent": "EXC_TRAP_FIQ"
172    },
173    {
174        "ArchStdEvent": "RC_LD_SPEC"
175    },
176    {
177        "ArchStdEvent": "RC_ST_SPEC"
178    }
179]
180