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Searched refs:MAX_PHY_REG_ADDRESS (Results 1 – 11 of 11) sorted by relevance

/drivers/net/ethernet/intel/e1000e/
Dphy.h95 (((reg) & MAX_PHY_REG_ADDRESS) |\
97 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
101 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
103 ~MAX_PHY_REG_ADDRESS)))
Dphy.c123 if (offset > MAX_PHY_REG_ADDRESS) { in e1000e_read_phy_reg_mdic()
186 if (offset > MAX_PHY_REG_ADDRESS) { in e1000e_write_phy_reg_mdic()
254 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_read_phy_reg_m88()
279 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_write_phy_reg_m88()
336 MAX_PHY_REG_ADDRESS & offset, in __e1000e_read_phy_reg_igp()
402 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & in __e1000e_write_phy_reg_igp()
2377 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_write_phy_reg_bm()
2435 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_read_phy_reg_bm()
2479 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_read_phy_reg_bm2()
2522 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_write_phy_reg_bm2()
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D80003es2lan.c352 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { in e1000_read_phy_reg_gg82563_80003es2lan()
386 MAX_PHY_REG_ADDRESS & offset, in e1000_read_phy_reg_gg82563_80003es2lan()
392 MAX_PHY_REG_ADDRESS & offset, in e1000_read_phy_reg_gg82563_80003es2lan()
421 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { in e1000_write_phy_reg_gg82563_80003es2lan()
455 MAX_PHY_REG_ADDRESS & in e1000_write_phy_reg_gg82563_80003es2lan()
461 MAX_PHY_REG_ADDRESS & in e1000_write_phy_reg_gg82563_80003es2lan()
Ddefines.h688 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
770 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
Dich8lan.h108 ((reg) & MAX_PHY_REG_ADDRESS))
/drivers/net/ethernet/intel/igc/
Digc_phy.c563 if (offset > MAX_PHY_REG_ADDRESS) { in igc_read_phy_reg_mdic()
619 if (offset > MAX_PHY_REG_ADDRESS) { in igc_write_phy_reg_mdic()
Digc_defines.h440 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
/drivers/net/ethernet/intel/igb/
De1000_phy.c119 if (offset > MAX_PHY_REG_ADDRESS) { in igb_read_phy_reg_mdic()
175 if (offset > MAX_PHY_REG_ADDRESS) { in igb_write_phy_reg_mdic()
401 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in igb_read_phy_reg_igp()
440 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in igb_write_phy_reg_igp()
De1000_defines.h871 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
/drivers/net/ethernet/intel/e1000/
De1000_hw.c2798 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, in e1000_read_phy_reg()
2813 if (reg_addr > MAX_PHY_REG_ADDRESS) { in e1000_read_phy_reg_ex()
2937 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, in e1000_write_phy_reg()
2951 if (reg_addr > MAX_PHY_REG_ADDRESS) { in e1000_write_phy_reg_ex()
De1000_hw.h2494 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
2916 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))