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Searched refs:MUX (Results 1 – 25 of 59) sorted by relevance

123

/drivers/pinctrl/sirf/
Dpinctrl-atlas7.c245 #define MUX(b, pad, f, dr, db, dvr, dvb) \ macro
1529 MUX(1, 119, 0, N, N, N, N),
1530 MUX(1, 120, 0, N, N, N, N),
1531 MUX(1, 121, 0, N, N, N, N),
1532 MUX(1, 122, 0, N, N, N, N),
1533 MUX(1, 123, 0, N, N, N, N),
1534 MUX(1, 124, 0, N, N, N, N),
1535 MUX(1, 125, 0, N, N, N, N),
1536 MUX(1, 126, 0, N, N, N, N),
1537 MUX(1, 127, 0, N, N, N, N),
[all …]
/drivers/clk/samsung/
Dclk-exynos5420.c470 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
471 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
472 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
473 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
475 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
476 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
477 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
478 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
479 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
481 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
[all …]
Dclk-exynos4.c422 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
423 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
424 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
429 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
430 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
431 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
432 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
434 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
435 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
440 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
[all …]
Dclk-s5pv210.c375 MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
376 MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
377 MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
378 MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
379 MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
380 MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
381 MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
383 MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
388 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
390 MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
[all …]
Dclk-exynos7.c89 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
91 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
93 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
95 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
97 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
99 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
101 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
103 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
106 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
108 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
[all …]
Dclk-exynos5260.c93 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
95 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
97 MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
202 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
205 MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
208 MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
211 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
215 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
219 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
223 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
[all …]
Dclk-exynos5250.c242 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
258 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
263 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
268 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
269 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
270 MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
271 MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
272 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
273 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
275 MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
[all …]
Dclk-exynos5410.c87 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
88 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
90 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
91 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
93 MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
94 MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
96 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
97 MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
99 MUX(0, "sclk_epll", epll_p, SRC_TOP2, 12, 1),
101 MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
[all …]
Dclk-exynos3250.c247 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
249 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
252 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
254 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
257 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
258 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
259 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
260 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
261 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
262 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
[all …]
Dclk-exynos5433.c258 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
260 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
264 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
266 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
268 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
270 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
274 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
276 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
278 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
280 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
[all …]
Dclk-s3c64xx.c126 MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
127 MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
128 MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
129 MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
130 MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
131 MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
132 MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
133 MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
134 MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
135 MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
[all …]
Dclk-s3c2412.c88 MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
89 MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
90 MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
91 MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
92 MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
93 MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
94 MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
95 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
96 MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
97 MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
Dclk-s3c2443.c71 MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
72 MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
73 MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
74 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
75 MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
76 MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
207 MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
208 MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
209 MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
288 MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
[all …]
/drivers/clk/mediatek/
Dclk-mt8167.c523 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
525 MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents,
527 MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents,
529 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
531 MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,
533 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
535 MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents,
537 MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents,
539 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
541 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
[all …]
Dclk-mt8516.c363 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
365 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
367 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
369 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
371 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
373 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
375 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
377 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
380 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
382 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
[all …]
Dclk-mt6797.c324 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
326 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
328 MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
332 MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
341 MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
345 MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
355 MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
357 MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
359 MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
361 MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
[all …]
Dclk-mt8173.c536 MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
537 MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
542 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
543 MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
593 MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
609 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
610 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
611 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
612 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
613 MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
[all …]
/drivers/clk/tegra/
Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ macro
639 …MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_…
640 …MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_…
641 …MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_…
642 …MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk…
643 …MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk…
644 …MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, t…
645 …MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_…
647 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
648 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
[all …]
/drivers/clk/zte/
Dclk-zx296718.c461 MUX(0, "dbg_mux", dbg_wclk_p, TOP_CLK_MUX0, 12, 2),
462 MUX(0, "a72_mux", a72_coreclk_p, TOP_CLK_MUX0, 8, 3),
463 MUX(0, "cpu_peri_mux", cpu_periclk_p, TOP_CLK_MUX0, 4, 3),
465 MUX(0, "sys_noc_aclk", sys_noc_alck_p, TOP_CLK_MUX1, 0, 3),
466 MUX(0, "sec_mux", sec_wclk_p, TOP_CLK_MUX2, 16, 3),
467 MUX(0, "sd1_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 12, 3),
468 MUX(0, "sd0_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 8, 3),
469 MUX(0, "emmc_mux", emmc_wclk_p, TOP_CLK_MUX2, 4, 3),
470 MUX(0, "nand_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 0, 3),
471 MUX(0, "usb_ref24m_mux", usb_ref24m_p, TOP_CLK_MUX9, 16, 1),
[all …]
/drivers/clk/pistachio/
Dclk-pistachio.c124 MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
126 MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
127 MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
128 MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
129 MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
130 MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
131 MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
132 MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
133 MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
134 MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
[all …]
/drivers/clk/rockchip/
Dclk-rk3308.c198 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
202 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
206 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
210 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
214 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
218 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
222 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
226 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
230 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
234 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
[all …]
Dclk-rk3188.c250 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
254 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
258 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
262 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
266 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
270 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
328 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
333 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
355 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
406 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
[all …]
Dclk-rk3228.c183 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
187 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
191 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
195 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
199 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
203 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
207 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
248 MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
250 MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
252 MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
[all …]
Dclk-px30.c208 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
212 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
216 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
220 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
224 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
228 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
232 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
236 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
240 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
244 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
[all …]
Dclk-rk3399.c246 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
250 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
254 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
258 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
262 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
266 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
270 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
274 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
278 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
282 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
[all …]

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