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/drivers/thermal/qcom/
Dtsens.h81 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ argument
82 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
83 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
84 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
85 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
86 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
87 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
88 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
89 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
90 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
[all …]
/drivers/staging/rtl8723bs/hal/
Dodm_interface.h18 #define _reg_all(_name) ODM_##_name argument
19 #define _reg_ic(_name, _ic) ODM_##_name##_ic argument
20 #define _bit_all(_name) BIT_##_name argument
21 #define _bit_ic(_name, _ic) BIT_##_name##_ic argument
31 #define _reg_11N(_name) ODM_REG_##_name##_11N argument
32 #define _bit_11N(_name) ODM_BIT_##_name##_11N argument
34 #define _cat(_name, _ic_type, _func) _func##_11N(_name) argument
39 #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) argument
40 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) argument
/drivers/clk/sprd/
Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
42 .hw.init = _fn(_name, _parent, \
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
62 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
[all …]
Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
80 .hw.init = _fn(_name, _parent, \
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
[all …]
Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
30 .hw.init = _fn(_name, _parent, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
55 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
Dmux.h39 #define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \ argument
46 .hw.init = _fn(_name, _parents, \
51 #define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \ argument
53 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
59 SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL, \
62 #define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \ argument
64 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
70 SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL, \
/drivers/regulator/
Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
56 [prefix ## _name] = { \
63 .id = prefix ## _name, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
69 .vsel_shift = prefix ## _vsel_reg ## _ ## _name ## VSEL,\
70 .vsel_mask = prefix ## _vsel_reg ## _ ## _name ## VSEL_M,\
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
74 [prefix ## _name] = { \
81 .id = prefix ## _name, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
[all …]
/drivers/platform/x86/
Ddcdbas.h50 #define DCDBAS_DEV_ATTR_RW(_name) \ argument
51 DEVICE_ATTR(_name,0600,_name##_show,_name##_store);
53 #define DCDBAS_DEV_ATTR_RO(_name) \ argument
54 DEVICE_ATTR(_name,0400,_name##_show,NULL);
56 #define DCDBAS_DEV_ATTR_WO(_name) \ argument
57 DEVICE_ATTR(_name,0200,NULL,_name##_store);
59 #define DCDBAS_BIN_ATTR_RW(_name) \ argument
60 struct bin_attribute bin_attr_##_name = { \
61 .attr = { .name = __stringify(_name), \
63 .read = _name##_read, \
[all …]
/drivers/clk/renesas/
Drenesas-cpg-mssr.h44 #define DEF_TYPE(_name, _id, _type...) \ argument
45 { .name = _name, .id = _id, .type = _type }
46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
47 DEF_TYPE(_name, _id, _type, .parent = _parent)
49 #define DEF_INPUT(_name, _id) \ argument
50 DEF_TYPE(_name, _id, CLK_TYPE_IN)
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
52 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
[all …]
Drcar-gen3-cpg.h34 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
35 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
37 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
42 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ argument
44 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
47 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
48 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
50 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ argument
51 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
[all …]
/drivers/clk/mvebu/
Darmada-37xx-periph.c129 #define PERIPH_GATE(_name, _bit) \ argument
130 struct clk_gate gate_##_name = { \
138 #define PERIPH_MUX(_name, _shift) \ argument
139 struct clk_mux mux_##_name = { \
148 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ argument
149 struct clk_double_div rate_##_name = { \
159 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
160 struct clk_divider rate_##_name = { \
169 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \ argument
170 struct clk_pm_cpu muxrate_##_name = { \
[all …]
/drivers/clk/zte/
Dclk.h37 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
44 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
52 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
53 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
67 .hw.init = CLK_HW_INIT(_name, \
80 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
85 .hw.init = CLK_HW_INIT(_name, \
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
106 .hw.init = CLK_HW_INIT_PARENTS(_name, \
[all …]
/drivers/gpu/drm/amd/pm/inc/
Damdgpu_pm.h63 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
64 { .dev_attr = __ATTR(_name, _mode, _show, _store), \
68 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
69 __AMDGPU_DEVICE_ATTR(_name, _mode, \
70 amdgpu_get_##_name, amdgpu_set_##_name, \
73 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
74 AMDGPU_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, \
77 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
78 __AMDGPU_DEVICE_ATTR(_name, S_IRUGO, \
79 amdgpu_get_##_name, NULL, \
/drivers/clk/pistachio/
Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
24 .name = _name, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
44 .name = _name, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
65 .name = _name, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
75 .name = _name, \
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
90 .name = _name, \
[all …]
/drivers/clk/mediatek/
Dclk-mtk.h29 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
31 .name = _name, \
47 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
49 .name = _name, \
81 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
84 .name = _name, \
101 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
103 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
111 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
[all …]
Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
/drivers/clk/sunxi-ng/
Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
96 .hw.init = CLK_HW_INIT(_name, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
111 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
123 .hw.init = CLK_HW_INIT_PARENTS(_name, \
130 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
133 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
139 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
142 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
[all …]
Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
24 .hw.init = CLK_HW_INIT(_name, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
36 .hw.init = CLK_HW_INIT_HW(_name, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
48 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
64 .hw.init = CLK_HW_INIT_HWS(_name, \
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
77 CLK_HW_INIT_PARENTS_DATA(_name, \
/drivers/s390/scsi/
Dzfcp_sysfs.c17 #define ZFCP_DEV_ATTR(_feat, _name, _mode, _show, _store) \ argument
18 struct device_attribute dev_attr_##_feat##_##_name = __ATTR(_name, _mode,\
20 #define ZFCP_DEFINE_ATTR(_feat_def, _feat, _name, _format, _value) \ argument
21 static ssize_t zfcp_sysfs_##_feat##_##_name##_show(struct device *dev, \
29 static ZFCP_DEV_ATTR(_feat, _name, S_IRUGO, \
30 zfcp_sysfs_##_feat##_##_name##_show, NULL);
32 #define ZFCP_DEFINE_ATTR_CONST(_feat, _name, _format, _value) \ argument
33 static ssize_t zfcp_sysfs_##_feat##_##_name##_show(struct device *dev, \
39 static ZFCP_DEV_ATTR(_feat, _name, S_IRUGO, \
40 zfcp_sysfs_##_feat##_##_name##_show, NULL);
[all …]
/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h133 #define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \ argument
135 .name = _name, \
145 #define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \ argument
147 .name = _name, \
157 #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
160 .name = _name, \
167 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
168 _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
170 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ argument
171 _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
[all …]
/drivers/clk/tegra/
Dclk-tegra-audio.c38 #define SYNC(_name) \ argument
40 .name = #_name,\
41 .clk_id = tegra_clk_ ## _name,\
52 #define AUDIO(_name, _offset) \ argument
54 .gate_name = #_name,\
55 .mux_name = #_name"_mux",\
57 .gate_clk_id = tegra_clk_ ## _name,\
58 .mux_clk_id = tegra_clk_ ## _name ## _mux,\
71 #define AUDIO2X(_name, _num, _offset) \ argument
73 .parent = #_name,\
[all …]
/drivers/clk/actions/
Dowl-composite.h37 #define OWL_COMP_DIV(_struct, _name, _parent, \ argument
45 .hw.init = CLK_HW_INIT_PARENTS(_name, \
52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ argument
59 .hw.init = CLK_HW_INIT(_name, \
66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \ argument
74 .hw.init = CLK_HW_INIT_PARENTS(_name, \
81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ argument
90 .hw.init = CLK_HW_INIT(_name, \
97 #define OWL_COMP_PASS(_struct, _name, _parent, \ argument
104 .hw.init = CLK_HW_INIT_PARENTS(_name, \
/drivers/cpuidle/
Dsysfs.c216 #define define_one_state_ro(_name, show) \ argument
217 static struct cpuidle_state_attr attr_##_name = __ATTR(_name, 0444, show, NULL)
219 #define define_one_state_rw(_name, show, store) \ argument
220 static struct cpuidle_state_attr attr_##_name = __ATTR(_name, 0644, show, store)
222 #define define_show_state_function(_name) \ argument
223 static ssize_t show_state_##_name(struct cpuidle_state *state, \
226 return sprintf(buf, "%u\n", state->_name);\
229 #define define_show_state_ull_function(_name) \ argument
230 static ssize_t show_state_##_name(struct cpuidle_state *state, \
234 return sprintf(buf, "%llu\n", state_usage->_name);\
[all …]
/drivers/staging/media/atomisp/include/media/
Dlm3554.h27 #define v4l2_queryctrl_entry_integer(_id, _name,\ argument
33 .name = _name, \
40 #define v4l2_queryctrl_entry_boolean(_id, _name,\ argument
45 .name = _name, \
53 #define s_ctrl_id_entry_integer(_id, _name, \ argument
58 .qc = v4l2_queryctrl_entry_integer(_id, _name,\
65 #define s_ctrl_id_entry_boolean(_id, _name, \ argument
69 .qc = v4l2_queryctrl_entry_boolean(_id, _name,\
/drivers/clk/meson/
Daxg-audio.c23 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument
29 .name = "aud_"#_name, \
37 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ argument
45 .name = "aud_"#_name, \
53 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ argument
61 .name = "aud_"#_name, \
69 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ argument
75 .name = "aud_"#_name, \
82 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ argument
97 .name = "aud_"#_name, \
[all …]

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