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Searched refs:ctrl_reg (Results 1 – 25 of 68) sorted by relevance

123

/drivers/rtc/
Drtc-pm8xxx.c80 unsigned int ctrl_reg, rtc_ctrl_reg; in pm8xxx_rtc_set_time() local
98 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); in pm8xxx_rtc_set_time()
102 if (ctrl_reg & regs->alarm_en) { in pm8xxx_rtc_set_time()
104 ctrl_reg &= ~regs->alarm_en; in pm8xxx_rtc_set_time()
105 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); in pm8xxx_rtc_set_time()
160 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_set_time()
161 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); in pm8xxx_rtc_set_time()
293 unsigned int ctrl_reg; in pm8xxx_rtc_alarm_irq_enable() local
298 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); in pm8xxx_rtc_alarm_irq_enable()
303 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_alarm_irq_enable()
[all …]
Drtc-bd70528.c64 unsigned int ctrl_reg; in bd70528_set_wake() local
66 ret = regmap_read(bd70528->regmap, BD70528_REG_WAKE_EN, &ctrl_reg); in bd70528_set_wake()
71 if (ctrl_reg & BD70528_MASK_WAKE_EN) in bd70528_set_wake()
81 ctrl_reg |= BD70528_MASK_WAKE_EN; in bd70528_set_wake()
83 ctrl_reg &= ~BD70528_MASK_WAKE_EN; in bd70528_set_wake()
86 ctrl_reg); in bd70528_set_wake()
93 unsigned int ctrl_reg; in bd70528_set_elapsed_tmr() local
108 &ctrl_reg); in bd70528_set_elapsed_tmr()
113 if (ctrl_reg & BD70528_MASK_ELAPSED_TIMER_EN) in bd70528_set_elapsed_tmr()
123 ctrl_reg |= BD70528_MASK_ELAPSED_TIMER_EN; in bd70528_set_elapsed_tmr()
[all …]
/drivers/watchdog/
Dmachzwd.c187 unsigned int ctrl_reg = 0; in zf_timer_off() local
195 ctrl_reg = zf_get_control(); in zf_timer_off()
196 ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */ in zf_timer_off()
197 ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2); in zf_timer_off()
198 zf_set_control(ctrl_reg); in zf_timer_off()
210 unsigned int ctrl_reg = 0; in zf_timer_on() local
226 ctrl_reg = zf_get_control(); in zf_timer_on()
227 ctrl_reg |= (ENABLE_WD1|zf_action); in zf_timer_on()
228 zf_set_control(ctrl_reg); in zf_timer_on()
237 unsigned int ctrl_reg = 0; in zf_ping() local
[all …]
/drivers/clk/microchip/
Dclk-core.c91 void __iomem *ctrl_reg; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
147 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; in pbclk_read_pbdiv()
174 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
185 v = readl(pb->ctrl_reg); in pbclk_set_rate()
191 writel(v, pb->ctrl_reg); in pbclk_set_rate()
196 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
226 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; in pic32_periph_clk_register()
[all …]
Dclk-core.h21 const u32 ctrl_reg; member
38 const u32 ctrl_reg; member
45 const u32 ctrl_reg; member
/drivers/bluetooth/
Dbluecard_cs.c79 unsigned char ctrl_reg; member
265 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_write_wakeup()
266 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
307 info->ctrl_reg &= ~0x03; in bluecard_write_wakeup()
308 info->ctrl_reg |= baud_reg; in bluecard_write_wakeup()
309 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
312 info->ctrl_reg &= ~REG_CONTROL_RTS; in bluecard_write_wakeup()
313 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
512 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT; in bluecard_interrupt()
513 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_interrupt()
[all …]
/drivers/pci/hotplug/
Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST), argument
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved1),
[all …]
Dshpchp.h177 struct ctrl_reg { struct
195 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), argument
196 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
197 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
198 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
199 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
200 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
201 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
202 CMD = offsetof(struct ctrl_reg, cmd),
203 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
[all …]
/drivers/net/wireless/st/cw1200/
Dbh.c178 u16 *ctrl_reg) in cw1200_bh_read_ctrl_reg() argument
183 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
186 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
196 u16 ctrl_reg; in cw1200_device_wakeup() local
213 ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg); in cw1200_device_wakeup()
220 if (ctrl_reg & ST90TDS_CONT_RDY_BIT) { in cw1200_device_wakeup()
238 uint16_t *ctrl_reg, in cw1200_bh_rx_helper() argument
252 read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2; in cw1200_bh_rx_helper()
259 read_len, *ctrl_reg); in cw1200_bh_rx_helper()
293 *ctrl_reg = __le16_to_cpu( in cw1200_bh_rx_helper()
[all …]
/drivers/spi/
Dspi-cadence.c152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT; in cdns_spi_init_hw() local
155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; in cdns_spi_init_hw()
165 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_init_hw()
177 u32 ctrl_reg; in cdns_spi_chipselect() local
179 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); in cdns_spi_chipselect()
183 ctrl_reg |= CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
186 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
188 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << in cdns_spi_chipselect()
192 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & in cdns_spi_chipselect()
196 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_chipselect()
[all …]
Dspi-jcore.c44 static int jcore_spi_wait(void __iomem *ctrl_reg) in jcore_spi_wait() argument
49 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY)) in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program() local
61 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
101 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_txrx() local
119 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
123 writel(xmit, ctrl_reg); in jcore_spi_txrx()
125 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
/drivers/clk/hisilicon/
Dclk-hix5hd2.c136 u32 ctrl_reg; member
148 void __iomem *ctrl_reg; member
174 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
176 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
178 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
203 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
205 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
218 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
221 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
236 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
[all …]
/drivers/phy/marvell/
Dphy-berlin-sata.c65 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, in phy_berlin_sata_reg_setbits() argument
71 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); in phy_berlin_sata_reg_setbits()
74 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
77 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
84 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on() local
104 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, in phy_berlin_sata_power_on()
109 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, in phy_berlin_sata_power_on()
113 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, in phy_berlin_sata_power_on()
117 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, in phy_berlin_sata_power_on()
121 regval = readl(ctrl_reg + PORT_SCR_CTL); in phy_berlin_sata_power_on()
[all …]
/drivers/clocksource/
Dtimer-cadence-ttc.c112 u32 ctrl_reg; in ttc_set_interval() local
115 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
116 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
117 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
125 ctrl_reg |= CNT_CNTRL_RESET; in ttc_set_interval()
126 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
127 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
196 u32 ctrl_reg; in ttc_shutdown() local
198 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
199 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_shutdown()
[all …]
/drivers/staging/wfx/
Dbh.c139 int ctrl_reg, piggyback; in bh_work_rx() local
144 ctrl_reg = piggyback; in bh_work_rx()
146 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0); in bh_work_rx()
148 ctrl_reg = 0; in bh_work_rx()
149 if (!(ctrl_reg & CTRL_NEXT_LEN_MASK)) in bh_work_rx()
152 len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2; in bh_work_rx()
161 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggyback); in bh_work_rx()
163 if (ctrl_reg) in bh_work_rx()
165 ctrl_reg, piggyback); in bh_work_rx()
274 prev = atomic_xchg(&wdev->hif.ctrl_reg, cur); in wfx_bh_request_rx()
/drivers/misc/ibmasm/
Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
54 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
60 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/drivers/net/ethernet/intel/ixgb/
Dixgb_hw.c49 u32 ctrl_reg; in ixgb_mac_reset() local
51 ctrl_reg = IXGB_CTRL0_RST | in ixgb_mac_reset()
62 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
69 ctrl_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_mac_reset()
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); in ixgb_mac_reset()
76 ctrl_reg = /* Enable interrupt from XFP and SerDes */ in ixgb_mac_reset()
82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); in ixgb_mac_reset()
89 return ctrl_reg; in ixgb_mac_reset()
100 u32 ctrl_reg; in ixgb_adapter_stop() local
[all …]
/drivers/input/rmi4/
Drmi_f30.c275 u8 *ctrl_reg = f30->ctrl_regs; in rmi_f30_initialize() local
300 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
303 sizeof(u8), &ctrl_reg); in rmi_f30_initialize()
307 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
310 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
315 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
319 &ctrl_reg); in rmi_f30_initialize()
325 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
331 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
336 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
[all …]
/drivers/fpga/
Dsocfpga.c337 u32 ctrl_reg; in socfpga_fpga_cfg_mode_set() local
346 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_cfg_mode_set()
347 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK; in socfpga_fpga_cfg_mode_set()
348 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK; in socfpga_fpga_cfg_mode_set()
349 ctrl_reg |= cfgmgr_modes[mode].ctrl; in socfpga_fpga_cfg_mode_set()
352 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE; in socfpga_fpga_cfg_mode_set()
353 socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); in socfpga_fpga_cfg_mode_set()
361 u32 ctrl_reg, status; in socfpga_fpga_reset() local
378 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_reset()
379 ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL; in socfpga_fpga_reset()
[all …]
/drivers/tty/serial/
Dxilinx_uartps.c498 u32 ctrl_reg; in cdns_uart_clk_notifier_cb() local
528 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
529 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; in cdns_uart_clk_notifier_cb()
530 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
555 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
556 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; in cdns_uart_clk_notifier_cb()
557 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
569 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
570 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); in cdns_uart_clk_notifier_cb()
571 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; in cdns_uart_clk_notifier_cb()
[all …]
/drivers/regulator/
Dvctrl-regulator.c326 struct regulator *ctrl_reg) in vctrl_init_vtable() argument
335 n_voltages = regulator_count_voltages(ctrl_reg); in vctrl_init_vtable()
341 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
361 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
453 struct regulator *ctrl_reg; in vctrl_probe() local
468 ctrl_reg = devm_regulator_get(&pdev->dev, "ctrl"); in vctrl_probe()
469 if (IS_ERR(ctrl_reg)) in vctrl_probe()
470 return PTR_ERR(ctrl_reg); in vctrl_probe()
480 if ((regulator_get_linear_step(ctrl_reg) == 1) || in vctrl_probe()
481 (regulator_count_voltages(ctrl_reg) == -EINVAL)) { in vctrl_probe()
[all …]
/drivers/i2c/busses/
Di2c-cadence.c559 unsigned int ctrl_reg; in cdns_i2c_mrecv() local
566 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
567 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_mrecv()
584 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_mrecv()
586 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
625 unsigned int ctrl_reg; in cdns_i2c_msend() local
633 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); in cdns_i2c_msend()
634 ctrl_reg &= ~CDNS_I2C_CR_RW; in cdns_i2c_msend()
635 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_msend()
642 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_msend()
[all …]
/drivers/media/platform/davinci/
Dvpif.h399 u32 ctrl_reg; in disable_raw_feature() local
401 ctrl_reg = VPIF_CH0_CTRL; in disable_raw_feature()
403 ctrl_reg = VPIF_CH1_CTRL; in disable_raw_feature()
406 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in disable_raw_feature()
408 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in disable_raw_feature()
413 u32 ctrl_reg; in enable_raw_feature() local
415 ctrl_reg = VPIF_CH0_CTRL; in enable_raw_feature()
417 ctrl_reg = VPIF_CH1_CTRL; in enable_raw_feature()
420 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in enable_raw_feature()
422 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in enable_raw_feature()
/drivers/hwmon/
Daspeed-pwm-tacho.c209 u32 ctrl_reg; member
220 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
229 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
238 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
247 u32 ctrl_reg; member
260 .ctrl_reg = ASPEED_PTCR_CTRL,
271 .ctrl_reg = ASPEED_PTCR_CTRL,
282 .ctrl_reg = ASPEED_PTCR_CTRL,
293 .ctrl_reg = ASPEED_PTCR_CTRL,
304 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
[all …]
/drivers/mmc/host/
Dmvsdio.c602 u32 ctrl_reg = 0; in mvsd_set_ios() local
624 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; in mvsd_set_ios()
625 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; in mvsd_set_ios()
628 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; in mvsd_set_ios()
629 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; in mvsd_set_ios()
632 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; in mvsd_set_ios()
635 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; in mvsd_set_ios()
647 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; in mvsd_set_ios()
650 host->ctrl = ctrl_reg; in mvsd_set_ios()
651 mvsd_write(MVSD_HOST_CTRL, ctrl_reg); in mvsd_set_ios()
[all …]

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