| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_vm_helper.c | 43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
57 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
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| D | dc_resource.c | 246 kfree(dc->hwseq); in dc_destroy_resource_pool()
353 dc->hwseq = create_funcs->create_hwseq(ctx); in resource_construct()
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| D | dc.c | 2840 dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config); in dc_set_power_state()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 118 struct dce_hwseq *hws = dc->hwseq; in log_mpc_crc()
665 struct dce_hwseq *hws = dc->hwseq; in undo_DEGVIDCN10_253_wa()
685 struct dce_hwseq *hws = dc->hwseq; in apply_DEGVIDCN10_253_wa()
715 struct dce_hwseq *hws = dc->hwseq; in dcn10_bios_golden_init()
761 if (!dc->hwseq->wa.false_optc_underflow) in false_optc_underflow_wa()
1049 struct dce_hwseq *hws = dc->hwseq; in dcn10_plane_atomic_disconnect()
1081 struct dce_hwseq *hws = dc->hwseq; in dcn10_plane_atomic_power_down()
1107 struct dce_hwseq *hws = dc->hwseq; in dcn10_plane_atomic_disable()
1140 struct dce_hwseq *hws = dc->hwseq; in dcn10_disable_plane()
1157 struct dce_hwseq *hws = dc->hwseq; in dcn10_init_pipes()
[all …]
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| D | dcn10_init.c | 122 dc->hwseq->funcs = dcn10_private_funcs; in dcn10_hw_sequencer_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 277 struct dce_hwseq *hws = dc->hwseq; in dcn20_init_blank()
568 struct dce_hwseq *hws = dc->hwseq; in dcn20_plane_atomic_disable()
644 struct dce_hwseq *hws = dc->hwseq; in dcn20_enable_stream_timing()
694 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) in dcn20_enable_stream_timing()
695 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); in dcn20_enable_stream_timing()
893 struct dce_hwseq *hws = dc->hwseq; in dcn20_set_input_transfer_func()
1094 dcn20_power_on_plane(dc->hwseq, pipe_ctx); in dcn20_enable_plane()
1375 struct dce_hwseq *hws = dc->hwseq; in dcn20_update_dchubp_dpp()
1573 struct dce_hwseq *hws = dc->hwseq; in dcn20_program_pipe()
1648 struct dce_hwseq *hws = dc->hwseq; in dcn20_program_front_end_for_ctx()
[all …]
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| D | dcn20_init.c | 139 dc->hwseq->funcs = dcn20_private_funcs; in dcn20_hw_sequencer_construct()
143 dc->hwseq->funcs.init_pipes = NULL; in dcn20_hw_sequencer_construct()
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| D | dcn20_resource.c | 4113 dc->hwseq->funcs.enable_power_gating_plane = NULL;
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_init.c | 139 dc->hwseq->funcs = dcn30_private_funcs; in dcn30_hw_sequencer_construct()
143 dc->hwseq->funcs.init_pipes = NULL; in dcn30_hw_sequencer_construct()
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| D | dcn30_hwseq.c | 146 struct dce_hwseq *hws = dc->hwseq; in dcn30_set_input_transfer_func()
436 struct dce_hwseq *hws = dc->hwseq; in dcn30_init_hw()
472 hws->funcs.disable_vga(dc->hwseq); in dcn30_init_hw()
630 hws->funcs.enable_power_gating_plane(dc->hwseq, true); in dcn30_init_hw()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_init.c | 145 dc->hwseq->funcs = dcn21_private_funcs; in dcn21_hw_sequencer_construct()
149 dc->hwseq->funcs.init_pipes = NULL; in dcn21_hw_sequencer_construct()
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| D | dcn21_hwseq.c | 90 struct dce_hwseq *hws = dc->hwseq; in dcn21_s0i3_golden_init_wa()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_hw_sequencer.c | 49 dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating; in dce80_hw_sequencer_construct()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 278 struct dce_hwseq *hws = dc->hwseq; in dce60_program_front_end_for_pipe()
286 dce_enable_fe_clock(dc->hwseq, mi->inst, true); in dce60_program_front_end_for_pipe()
425 dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating; in dce60_hw_sequencer_construct()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 1120 struct dce_hwseq *hws = link->dc->hwseq; in dce110_unblank_stream()
1138 struct dce_hwseq *hws = link->dc->hwseq; in dce110_blank_stream()
1407 struct dce_hwseq *hws = dc->hwseq; in apply_single_controller_ctx_to_hw()
1642 struct dce_hwseq *hws = dc->hwseq; in dce110_enable_accelerated_mode()
2103 struct dce_hwseq *hws = dc->hwseq; in dce110_apply_ctx_to_hw()
2130 dce_crtc_switch_to_clk_src(dc->hwseq, in dce110_apply_ctx_to_hw()
2248 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); in program_surface_visibility()
2444 struct dce_hwseq *hws = dc->hwseq; in init_hw()
2463 dce_clock_gating_power_up(dc->hwseq, false); in init_hw()
2549 struct dce_hwseq *hws = dc->hwseq; in dce110_program_front_end_for_pipe()
[all …]
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| D | dce110_resource.c | 1134 struct dce_hwseq *hws = dc->hwseq; in dce110_acquire_underlay()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_hw_sequencer.c | 138 dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating; in dce100_hw_sequencer_construct()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_hw_sequencer.c | 161 dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating; in dce112_hw_sequencer_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| D | dce120_clk_mgr.c | 149 if (dce121_xgmi_enabled(ctx->dc->hwseq)) in dce121_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_hw_sequencer.c | 268 dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating; in dce120_hw_sequencer_construct()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_hwseq.c | 53 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 597 struct dce_hwseq *hwseq; member
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