| /drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1266 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1267 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1288 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1289 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1303 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1317 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1318 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1340 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1363 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1364 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
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| D | clk-alpha-pll.h | 95 const struct clk_div_table *post_div_table; member
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| D | mmcc-msm8998.c | 93 .post_div_table = post_div_table_fabia_even,
126 .post_div_table = post_div_table_fabia_even,
155 .post_div_table = post_div_table_fabia_even,
184 .post_div_table = post_div_table_fabia_even,
213 .post_div_table = post_div_table_fabia_even,
242 .post_div_table = post_div_table_fabia_even,
271 .post_div_table = post_div_table_fabia_even,
300 .post_div_table = post_div_table_fabia_even,
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| D | camcc-sdm845.c | 69 .post_div_table = post_div_table_fabia_even,
97 .post_div_table = post_div_table_fabia_even,
125 .post_div_table = post_div_table_fabia_even,
153 .post_div_table = post_div_table_fabia_even,
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| D | gpucc-msm8998.c | 75 .post_div_table = post_div_table_fabia_even,
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| D | lpasscorecc-sc7180.c | 89 .post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
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| D | dispcc-sc7180.c | 62 .post_div_table = post_div_table_disp_cc_pll0_out_even,
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| D | gcc-sc7180.c | 62 .post_div_table = post_div_table_gpll0_out_even,
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| D | gcc-sdm845.c | 194 .post_div_table = post_div_table_fabia_even,
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| D | gcc-sm8250.c | 61 .post_div_table = post_div_table_gpll0_out_even,
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| D | gcc-sm8150.c | 66 .post_div_table = post_div_table_trion_even,
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| /drivers/clk/imx/ |
| D | clk-imx6sl.c | 79 static const struct clk_div_table post_div_table[] = { variable
266 …v", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
268 …v", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
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| D | clk-imx6sll.c | 59 static const struct clk_div_table post_div_table[] = { variable
176 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
180 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
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| D | clk-imx6q.c | 103 static struct clk_div_table post_div_table[] = { variable
462 post_div_table[1].div = 1; in imx6q_clocks_init()
463 post_div_table[2].div = 1; in imx6q_clocks_init()
593 …post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
598 …post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
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| D | clk-imx6ul.c | 82 static const struct clk_div_table post_div_table[] = { variable
218 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
222 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
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| D | clk-imx6sx.c | 96 static const struct clk_div_table post_div_table[] = { variable
248 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
252 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
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| D | clk-imx7d.c | 36 static const struct clk_div_table post_div_table[] = { variable
434 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
438 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
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