1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-rcg.h"
16 #include "clk-regmap-divider.h"
17 #include "common.h"
18 #include "gdsc.h"
19
20 enum {
21 P_BI_TCXO,
22 P_CHIP_SLEEP_CLK,
23 P_CORE_BI_PLL_TEST_SE,
24 P_DISP_CC_PLL0_OUT_EVEN,
25 P_DISP_CC_PLL0_OUT_MAIN,
26 P_DP_PHY_PLL_LINK_CLK,
27 P_DP_PHY_PLL_VCO_DIV_CLK,
28 P_DSI0_PHY_PLL_OUT_BYTECLK,
29 P_DSI0_PHY_PLL_OUT_DSICLK,
30 P_GPLL0_OUT_MAIN,
31 };
32
33 static const struct pll_vco fabia_vco[] = {
34 { 249600000, 2000000000, 0 },
35 };
36
37 static struct clk_alpha_pll disp_cc_pll0 = {
38 .offset = 0x0,
39 .vco_table = fabia_vco,
40 .num_vco = ARRAY_SIZE(fabia_vco),
41 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
42 .clkr = {
43 .hw.init = &(struct clk_init_data){
44 .name = "disp_cc_pll0",
45 .parent_data = &(const struct clk_parent_data){
46 .fw_name = "bi_tcxo",
47 },
48 .num_parents = 1,
49 .ops = &clk_alpha_pll_fabia_ops,
50 },
51 },
52 };
53
54 static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = {
55 { 0x0, 1 },
56 { }
57 };
58
59 static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
60 .offset = 0x0,
61 .post_div_shift = 8,
62 .post_div_table = post_div_table_disp_cc_pll0_out_even,
63 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even),
64 .width = 4,
65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
66 .clkr.hw.init = &(struct clk_init_data){
67 .name = "disp_cc_pll0_out_even",
68 .parent_data = &(const struct clk_parent_data){
69 .hw = &disp_cc_pll0.clkr.hw,
70 },
71 .num_parents = 1,
72 .flags = CLK_SET_RATE_PARENT,
73 .ops = &clk_alpha_pll_postdiv_fabia_ops,
74 },
75 };
76
77 static const struct parent_map disp_cc_parent_map_0[] = {
78 { P_BI_TCXO, 0 },
79 };
80
81 static const struct clk_parent_data disp_cc_parent_data_0[] = {
82 { .fw_name = "bi_tcxo" },
83 };
84
85 static const struct parent_map disp_cc_parent_map_1[] = {
86 { P_BI_TCXO, 0 },
87 { P_DP_PHY_PLL_LINK_CLK, 1 },
88 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
89 };
90
91 static const struct clk_parent_data disp_cc_parent_data_1[] = {
92 { .fw_name = "bi_tcxo" },
93 { .fw_name = "dp_phy_pll_link_clk" },
94 { .fw_name = "dp_phy_pll_vco_div_clk" },
95 };
96
97 static const struct parent_map disp_cc_parent_map_2[] = {
98 { P_BI_TCXO, 0 },
99 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
100 };
101
102 static const struct clk_parent_data disp_cc_parent_data_2[] = {
103 { .fw_name = "bi_tcxo" },
104 { .fw_name = "dsi0_phy_pll_out_byteclk" },
105 };
106
107 static const struct parent_map disp_cc_parent_map_3[] = {
108 { P_BI_TCXO, 0 },
109 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
110 { P_GPLL0_OUT_MAIN, 4 },
111 { P_DISP_CC_PLL0_OUT_EVEN, 5 },
112 };
113
114 static const struct clk_parent_data disp_cc_parent_data_3[] = {
115 { .fw_name = "bi_tcxo" },
116 { .hw = &disp_cc_pll0.clkr.hw },
117 { .fw_name = "gcc_disp_gpll0_clk_src" },
118 { .hw = &disp_cc_pll0_out_even.clkr.hw },
119 };
120
121 static const struct parent_map disp_cc_parent_map_4[] = {
122 { P_BI_TCXO, 0 },
123 { P_GPLL0_OUT_MAIN, 4 },
124 };
125
126 static const struct clk_parent_data disp_cc_parent_data_4[] = {
127 { .fw_name = "bi_tcxo" },
128 { .fw_name = "gcc_disp_gpll0_clk_src" },
129 };
130
131 static const struct parent_map disp_cc_parent_map_5[] = {
132 { P_BI_TCXO, 0 },
133 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
134 };
135
136 static const struct clk_parent_data disp_cc_parent_data_5[] = {
137 { .fw_name = "bi_tcxo" },
138 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
139 };
140
141 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
142 F(19200000, P_BI_TCXO, 1, 0, 0),
143 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
144 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
145 { }
146 };
147
148 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
149 .cmd_rcgr = 0x22bc,
150 .mnd_width = 0,
151 .hid_width = 5,
152 .parent_map = disp_cc_parent_map_4,
153 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
154 .clkr.hw.init = &(struct clk_init_data){
155 .name = "disp_cc_mdss_ahb_clk_src",
156 .parent_data = disp_cc_parent_data_4,
157 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
158 .flags = CLK_SET_RATE_PARENT,
159 .ops = &clk_rcg2_shared_ops,
160 },
161 };
162
163 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
164 .cmd_rcgr = 0x2110,
165 .mnd_width = 0,
166 .hid_width = 5,
167 .parent_map = disp_cc_parent_map_2,
168 .clkr.hw.init = &(struct clk_init_data){
169 .name = "disp_cc_mdss_byte0_clk_src",
170 .parent_data = disp_cc_parent_data_2,
171 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
172 .flags = CLK_SET_RATE_PARENT,
173 .ops = &clk_byte2_ops,
174 },
175 };
176
177 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
178 F(19200000, P_BI_TCXO, 1, 0, 0),
179 { }
180 };
181
182 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
183 .cmd_rcgr = 0x21dc,
184 .mnd_width = 0,
185 .hid_width = 5,
186 .parent_map = disp_cc_parent_map_0,
187 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "disp_cc_mdss_dp_aux_clk_src",
190 .parent_data = disp_cc_parent_data_0,
191 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
192 .ops = &clk_rcg2_ops,
193 },
194 };
195
196 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
197 .cmd_rcgr = 0x2194,
198 .mnd_width = 0,
199 .hid_width = 5,
200 .parent_map = disp_cc_parent_map_1,
201 .clkr.hw.init = &(struct clk_init_data){
202 .name = "disp_cc_mdss_dp_crypto_clk_src",
203 .parent_data = disp_cc_parent_data_1,
204 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
205 .ops = &clk_byte2_ops,
206 },
207 };
208
209 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
210 .cmd_rcgr = 0x2178,
211 .mnd_width = 0,
212 .hid_width = 5,
213 .parent_map = disp_cc_parent_map_1,
214 .clkr.hw.init = &(struct clk_init_data){
215 .name = "disp_cc_mdss_dp_link_clk_src",
216 .parent_data = disp_cc_parent_data_1,
217 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
218 .ops = &clk_byte2_ops,
219 },
220 };
221
222 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
223 .cmd_rcgr = 0x21ac,
224 .mnd_width = 16,
225 .hid_width = 5,
226 .parent_map = disp_cc_parent_map_1,
227 .clkr.hw.init = &(struct clk_init_data){
228 .name = "disp_cc_mdss_dp_pixel_clk_src",
229 .parent_data = disp_cc_parent_data_1,
230 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
231 .ops = &clk_dp_ops,
232 },
233 };
234
235 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
236 .cmd_rcgr = 0x2148,
237 .mnd_width = 0,
238 .hid_width = 5,
239 .parent_map = disp_cc_parent_map_2,
240 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
241 .clkr.hw.init = &(struct clk_init_data){
242 .name = "disp_cc_mdss_esc0_clk_src",
243 .parent_data = disp_cc_parent_data_2,
244 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
245 .ops = &clk_rcg2_ops,
246 },
247 };
248
249 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
250 F(19200000, P_BI_TCXO, 1, 0, 0),
251 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
252 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
253 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
254 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
255 { }
256 };
257
258 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
259 .cmd_rcgr = 0x20c8,
260 .mnd_width = 0,
261 .hid_width = 5,
262 .parent_map = disp_cc_parent_map_3,
263 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
264 .clkr.hw.init = &(struct clk_init_data){
265 .name = "disp_cc_mdss_mdp_clk_src",
266 .parent_data = disp_cc_parent_data_3,
267 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
268 .ops = &clk_rcg2_shared_ops,
269 },
270 };
271
272 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
273 .cmd_rcgr = 0x2098,
274 .mnd_width = 8,
275 .hid_width = 5,
276 .parent_map = disp_cc_parent_map_5,
277 .clkr.hw.init = &(struct clk_init_data){
278 .name = "disp_cc_mdss_pclk0_clk_src",
279 .parent_data = disp_cc_parent_data_5,
280 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
281 .flags = CLK_SET_RATE_PARENT,
282 .ops = &clk_pixel_ops,
283 },
284 };
285
286 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
287 .cmd_rcgr = 0x20e0,
288 .mnd_width = 0,
289 .hid_width = 5,
290 .parent_map = disp_cc_parent_map_3,
291 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
292 .clkr.hw.init = &(struct clk_init_data){
293 .name = "disp_cc_mdss_rot_clk_src",
294 .parent_data = disp_cc_parent_data_3,
295 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
296 .ops = &clk_rcg2_shared_ops,
297 },
298 };
299
300 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
301 .cmd_rcgr = 0x20f8,
302 .mnd_width = 0,
303 .hid_width = 5,
304 .parent_map = disp_cc_parent_map_0,
305 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
306 .clkr.hw.init = &(struct clk_init_data){
307 .name = "disp_cc_mdss_vsync_clk_src",
308 .parent_data = disp_cc_parent_data_0,
309 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
310 .ops = &clk_rcg2_shared_ops,
311 },
312 };
313
314 static struct clk_branch disp_cc_mdss_ahb_clk = {
315 .halt_reg = 0x2080,
316 .halt_check = BRANCH_HALT,
317 .clkr = {
318 .enable_reg = 0x2080,
319 .enable_mask = BIT(0),
320 .hw.init = &(struct clk_init_data){
321 .name = "disp_cc_mdss_ahb_clk",
322 .parent_data = &(const struct clk_parent_data){
323 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
324 },
325 .num_parents = 1,
326 .flags = CLK_SET_RATE_PARENT,
327 .ops = &clk_branch2_ops,
328 },
329 },
330 };
331
332 static struct clk_branch disp_cc_mdss_byte0_clk = {
333 .halt_reg = 0x2028,
334 .halt_check = BRANCH_HALT,
335 .clkr = {
336 .enable_reg = 0x2028,
337 .enable_mask = BIT(0),
338 .hw.init = &(struct clk_init_data){
339 .name = "disp_cc_mdss_byte0_clk",
340 .parent_data = &(const struct clk_parent_data){
341 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
342 },
343 .num_parents = 1,
344 .flags = CLK_SET_RATE_PARENT,
345 .ops = &clk_branch2_ops,
346 },
347 },
348 };
349
350 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
351 .reg = 0x2128,
352 .shift = 0,
353 .width = 2,
354 .clkr.hw.init = &(struct clk_init_data) {
355 .name = "disp_cc_mdss_byte0_div_clk_src",
356 .parent_data = &(const struct clk_parent_data){
357 .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw
358 },
359 .num_parents = 1,
360 .ops = &clk_regmap_div_ops,
361 },
362 };
363
364 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
365 .reg = 0x2190,
366 .shift = 0,
367 .width = 2,
368 .clkr.hw.init = &(struct clk_init_data) {
369 .name = "disp_cc_mdss_dp_link_div_clk_src",
370 .parent_data = &(const struct clk_parent_data){
371 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw
372 },
373 .num_parents = 1,
374 .ops = &clk_regmap_div_ops,
375 },
376 };
377
378 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
379 .halt_reg = 0x202c,
380 .halt_check = BRANCH_HALT,
381 .clkr = {
382 .enable_reg = 0x202c,
383 .enable_mask = BIT(0),
384 .hw.init = &(struct clk_init_data){
385 .name = "disp_cc_mdss_byte0_intf_clk",
386 .parent_data = &(const struct clk_parent_data){
387 .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
388 },
389 .num_parents = 1,
390 .flags = CLK_SET_RATE_PARENT,
391 .ops = &clk_branch2_ops,
392 },
393 },
394 };
395
396 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
397 .halt_reg = 0x2054,
398 .halt_check = BRANCH_HALT,
399 .clkr = {
400 .enable_reg = 0x2054,
401 .enable_mask = BIT(0),
402 .hw.init = &(struct clk_init_data){
403 .name = "disp_cc_mdss_dp_aux_clk",
404 .parent_data = &(const struct clk_parent_data){
405 .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
406 },
407 .num_parents = 1,
408 .flags = CLK_SET_RATE_PARENT,
409 .ops = &clk_branch2_ops,
410 },
411 },
412 };
413
414 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
415 .halt_reg = 0x2048,
416 .halt_check = BRANCH_HALT,
417 .clkr = {
418 .enable_reg = 0x2048,
419 .enable_mask = BIT(0),
420 .hw.init = &(struct clk_init_data){
421 .name = "disp_cc_mdss_dp_crypto_clk",
422 .parent_data = &(const struct clk_parent_data){
423 .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
424 },
425 .num_parents = 1,
426 .flags = CLK_SET_RATE_PARENT,
427 .ops = &clk_branch2_ops,
428 },
429 },
430 };
431
432 static struct clk_branch disp_cc_mdss_dp_link_clk = {
433 .halt_reg = 0x2040,
434 .halt_check = BRANCH_HALT,
435 .clkr = {
436 .enable_reg = 0x2040,
437 .enable_mask = BIT(0),
438 .hw.init = &(struct clk_init_data){
439 .name = "disp_cc_mdss_dp_link_clk",
440 .parent_data = &(const struct clk_parent_data){
441 .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw,
442 },
443 .num_parents = 1,
444 .flags = CLK_SET_RATE_PARENT,
445 .ops = &clk_branch2_ops,
446 },
447 },
448 };
449
450 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
451 .halt_reg = 0x2044,
452 .halt_check = BRANCH_HALT,
453 .clkr = {
454 .enable_reg = 0x2044,
455 .enable_mask = BIT(0),
456 .hw.init = &(struct clk_init_data){
457 .name = "disp_cc_mdss_dp_link_intf_clk",
458 .parent_data = &(const struct clk_parent_data){
459 .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
460 },
461 .num_parents = 1,
462 .ops = &clk_branch2_ops,
463 },
464 },
465 };
466
467 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
468 .halt_reg = 0x204c,
469 .halt_check = BRANCH_HALT,
470 .clkr = {
471 .enable_reg = 0x204c,
472 .enable_mask = BIT(0),
473 .hw.init = &(struct clk_init_data){
474 .name = "disp_cc_mdss_dp_pixel_clk",
475 .parent_data = &(const struct clk_parent_data){
476 .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
477 },
478 .num_parents = 1,
479 .flags = CLK_SET_RATE_PARENT,
480 .ops = &clk_branch2_ops,
481 },
482 },
483 };
484
485 static struct clk_branch disp_cc_mdss_esc0_clk = {
486 .halt_reg = 0x2038,
487 .halt_check = BRANCH_HALT,
488 .clkr = {
489 .enable_reg = 0x2038,
490 .enable_mask = BIT(0),
491 .hw.init = &(struct clk_init_data){
492 .name = "disp_cc_mdss_esc0_clk",
493 .parent_data = &(const struct clk_parent_data){
494 .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw,
495 },
496 .num_parents = 1,
497 .flags = CLK_SET_RATE_PARENT,
498 .ops = &clk_branch2_ops,
499 },
500 },
501 };
502
503 static struct clk_branch disp_cc_mdss_mdp_clk = {
504 .halt_reg = 0x200c,
505 .halt_check = BRANCH_HALT,
506 .clkr = {
507 .enable_reg = 0x200c,
508 .enable_mask = BIT(0),
509 .hw.init = &(struct clk_init_data){
510 .name = "disp_cc_mdss_mdp_clk",
511 .parent_data = &(const struct clk_parent_data){
512 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
513 },
514 .num_parents = 1,
515 .flags = CLK_SET_RATE_PARENT,
516 .ops = &clk_branch2_ops,
517 },
518 },
519 };
520
521 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
522 .halt_reg = 0x201c,
523 .halt_check = BRANCH_VOTED,
524 .clkr = {
525 .enable_reg = 0x201c,
526 .enable_mask = BIT(0),
527 .hw.init = &(struct clk_init_data){
528 .name = "disp_cc_mdss_mdp_lut_clk",
529 .parent_data = &(const struct clk_parent_data){
530 .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw,
531 },
532 .num_parents = 1,
533 .ops = &clk_branch2_ops,
534 },
535 },
536 };
537
538 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
539 .halt_reg = 0x4004,
540 .halt_check = BRANCH_VOTED,
541 .clkr = {
542 .enable_reg = 0x4004,
543 .enable_mask = BIT(0),
544 .hw.init = &(struct clk_init_data){
545 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
546 .parent_data = &(const struct clk_parent_data){
547 .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
548 },
549 .num_parents = 1,
550 .flags = CLK_SET_RATE_PARENT,
551 .ops = &clk_branch2_ops,
552 },
553 },
554 };
555
556 static struct clk_branch disp_cc_mdss_pclk0_clk = {
557 .halt_reg = 0x2004,
558 .halt_check = BRANCH_HALT,
559 .clkr = {
560 .enable_reg = 0x2004,
561 .enable_mask = BIT(0),
562 .hw.init = &(struct clk_init_data){
563 .name = "disp_cc_mdss_pclk0_clk",
564 .parent_data = &(const struct clk_parent_data){
565 .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw,
566 },
567 .num_parents = 1,
568 .flags = CLK_SET_RATE_PARENT,
569 .ops = &clk_branch2_ops,
570 },
571 },
572 };
573
574 static struct clk_branch disp_cc_mdss_rot_clk = {
575 .halt_reg = 0x2014,
576 .halt_check = BRANCH_HALT,
577 .clkr = {
578 .enable_reg = 0x2014,
579 .enable_mask = BIT(0),
580 .hw.init = &(struct clk_init_data){
581 .name = "disp_cc_mdss_rot_clk",
582 .parent_data = &(const struct clk_parent_data){
583 .hw = &disp_cc_mdss_rot_clk_src.clkr.hw,
584 },
585 .num_parents = 1,
586 .flags = CLK_SET_RATE_PARENT,
587 .ops = &clk_branch2_ops,
588 },
589 },
590 };
591
592 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
593 .halt_reg = 0x4008,
594 .halt_check = BRANCH_HALT,
595 .clkr = {
596 .enable_reg = 0x4008,
597 .enable_mask = BIT(0),
598 .hw.init = &(struct clk_init_data){
599 .name = "disp_cc_mdss_rscc_vsync_clk",
600 .parent_data = &(const struct clk_parent_data){
601 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
602 },
603 .num_parents = 1,
604 .flags = CLK_SET_RATE_PARENT,
605 .ops = &clk_branch2_ops,
606 },
607 },
608 };
609
610 static struct clk_branch disp_cc_mdss_vsync_clk = {
611 .halt_reg = 0x2024,
612 .halt_check = BRANCH_HALT,
613 .clkr = {
614 .enable_reg = 0x2024,
615 .enable_mask = BIT(0),
616 .hw.init = &(struct clk_init_data){
617 .name = "disp_cc_mdss_vsync_clk",
618 .parent_data = &(const struct clk_parent_data){
619 .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw,
620 },
621 .num_parents = 1,
622 .flags = CLK_SET_RATE_PARENT,
623 .ops = &clk_branch2_ops,
624 },
625 },
626 };
627
628 static struct gdsc mdss_gdsc = {
629 .gdscr = 0x3000,
630 .pd = {
631 .name = "mdss_gdsc",
632 },
633 .pwrsts = PWRSTS_OFF_ON,
634 .flags = HW_CTRL,
635 };
636
637 static struct gdsc *disp_cc_sc7180_gdscs[] = {
638 [MDSS_GDSC] = &mdss_gdsc,
639 };
640
641 static struct clk_regmap *disp_cc_sc7180_clocks[] = {
642 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
643 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
644 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
645 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
646 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
647 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
648 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
649 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
650 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
651 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
652 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
653 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
654 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
655 &disp_cc_mdss_dp_link_div_clk_src.clkr,
656 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
657 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
658 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
659 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
660 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
661 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
662 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
663 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
664 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
665 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
666 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
667 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
668 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
669 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
670 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
671 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
672 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
673 [DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr,
674 };
675
676 static const struct regmap_config disp_cc_sc7180_regmap_config = {
677 .reg_bits = 32,
678 .reg_stride = 4,
679 .val_bits = 32,
680 .max_register = 0x10000,
681 .fast_io = true,
682 };
683
684 static const struct qcom_cc_desc disp_cc_sc7180_desc = {
685 .config = &disp_cc_sc7180_regmap_config,
686 .clks = disp_cc_sc7180_clocks,
687 .num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
688 .gdscs = disp_cc_sc7180_gdscs,
689 .num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
690 };
691
692 static const struct of_device_id disp_cc_sc7180_match_table[] = {
693 { .compatible = "qcom,sc7180-dispcc" },
694 { }
695 };
696 MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table);
697
disp_cc_sc7180_probe(struct platform_device * pdev)698 static int disp_cc_sc7180_probe(struct platform_device *pdev)
699 {
700 struct regmap *regmap;
701 struct alpha_pll_config disp_cc_pll_config = {};
702
703 regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc);
704 if (IS_ERR(regmap))
705 return PTR_ERR(regmap);
706
707 /* 1380MHz configuration */
708 disp_cc_pll_config.l = 0x47;
709 disp_cc_pll_config.alpha = 0xe000;
710 disp_cc_pll_config.user_ctl_val = 0x00000001;
711 disp_cc_pll_config.user_ctl_hi_val = 0x00004805;
712
713 clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
714
715 return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
716 }
717
718 static struct platform_driver disp_cc_sc7180_driver = {
719 .probe = disp_cc_sc7180_probe,
720 .driver = {
721 .name = "sc7180-dispcc",
722 .of_match_table = disp_cc_sc7180_match_table,
723 },
724 };
725
disp_cc_sc7180_init(void)726 static int __init disp_cc_sc7180_init(void)
727 {
728 return platform_driver_register(&disp_cc_sc7180_driver);
729 }
730 subsys_initcall(disp_cc_sc7180_init);
731
disp_cc_sc7180_exit(void)732 static void __exit disp_cc_sc7180_exit(void)
733 {
734 platform_driver_unregister(&disp_cc_sc7180_driver);
735 }
736 module_exit(disp_cc_sc7180_exit);
737
738 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver");
739 MODULE_LICENSE("GPL v2");
740