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/drivers/reset/
DMakefile6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
10 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
11 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
12 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
13 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
14 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
15 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
[all …]
DKconfig11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
22 This option enables support for the external reset functions for
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
42 This enables the reset controller driver for Marvell Berlin SoCs.
45 tristate "Broadcom STB reset controller"
49 This enables the reset controller driver for Broadcom STB SoCs using
53 bool "Broadcom STB RESCAL reset controller"
[all …]
/drivers/power/reset/
Dat91-reset.c70 struct at91_reset *reset = container_of(this, struct at91_reset, nb); in at91_reset() local
93 : "r" (reset->ramc_base[0]), in at91_reset()
94 "r" (reset->ramc_base[1]), in at91_reset()
95 "r" (reset->rstc_base), in at91_reset()
98 "r" (reset->args), in at91_reset()
99 "r" (reset->ramc_lpr) in at91_reset()
187 struct at91_reset *reset; in at91_reset_probe() local
191 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); in at91_reset_probe()
192 if (!reset) in at91_reset_probe()
195 reset->rstc_base = of_iomap(pdev->dev.of_node, 0); in at91_reset_probe()
[all …]
DMakefile4 obj-$(CONFIG_POWER_RESET_AT91_RESET) += at91-reset.o
6 obj-$(CONFIG_POWER_RESET_AXXIA) += axxia-reset.o
7 obj-$(CONFIG_POWER_RESET_BRCMKONA) += brcm-kona-reset.o
18 obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
27 obj-$(CONFIG_POWER_RESET_KEYSTONE) += keystone-reset.o
30 obj-$(CONFIG_POWER_RESET_RMOBILE) += rmobile-reset.o
/drivers/soc/ti/
Domap_prm.c407 static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id) in _is_valid_reset() argument
409 if (reset->mask & BIT(id)) in _is_valid_reset()
415 static int omap_reset_get_st_bit(struct omap_reset_data *reset, in omap_reset_get_st_bit() argument
418 const struct omap_rst_map *map = reset->prm->data->rstmap; in omap_reset_get_st_bit()
433 struct omap_reset_data *reset = to_omap_reset_data(rcdev); in omap_reset_status() local
435 int st_bit = omap_reset_get_st_bit(reset, id); in omap_reset_status()
436 bool has_rstst = reset->prm->data->rstst || in omap_reset_status()
437 (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); in omap_reset_status()
444 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_status()
452 v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); in omap_reset_status()
[all …]
/drivers/clk/sunxi-ng/
Dccu_common.c85 struct ccu_reset *reset; in sunxi_ccu_probe() local
118 reset = kzalloc(sizeof(*reset), GFP_KERNEL); in sunxi_ccu_probe()
119 if (!reset) { in sunxi_ccu_probe()
124 reset->rcdev.of_node = node; in sunxi_ccu_probe()
125 reset->rcdev.ops = &ccu_reset_ops; in sunxi_ccu_probe()
126 reset->rcdev.owner = THIS_MODULE; in sunxi_ccu_probe()
127 reset->rcdev.nr_resets = desc->num_resets; in sunxi_ccu_probe()
128 reset->base = reg; in sunxi_ccu_probe()
129 reset->lock = &ccu_lock; in sunxi_ccu_probe()
130 reset->reset_map = desc->resets; in sunxi_ccu_probe()
[all …]
/drivers/clk/actions/
Dowl-reset.c17 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_assert() local
18 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_assert()
20 return regmap_update_bits(reset->regmap, map->reg, map->bit, 0); in owl_reset_assert()
26 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_deassert() local
27 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_deassert()
29 return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit); in owl_reset_deassert()
45 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_status() local
46 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_status()
50 ret = regmap_read(reset->regmap, map->reg, &reg); in owl_reset_status()
64 .reset = owl_reset_reset,
/drivers/gpu/drm/i915/gt/
Dintel_reset.c638 reset_func reset; in __intel_gt_reset() local
642 reset = intel_get_gpu_reset(gt); in __intel_gt_reset()
643 if (!reset) in __intel_gt_reset()
654 ret = reset(gt, engine_mask, retry); in __intel_gt_reset()
664 if (!gt->i915->params.reset) in intel_has_gpu_reset()
672 if (gt->i915->params.reset < 2) in intel_has_reset_engine()
707 if (engine->reset.prepare) in reset_prepare_engine()
708 engine->reset.prepare(engine); in reset_prepare_engine()
788 if (engine->reset.finish) in reset_finish_engine()
789 engine->reset.finish(engine); in reset_finish_engine()
[all …]
/drivers/gpu/drm/i915/selftests/
Digt_reset.c19 pr_debug("%s: current gpu_error=%08lx\n", __func__, gt->reset.flags); in igt_global_reset_lock()
21 while (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) in igt_global_reset_lock()
22 wait_event(gt->reset.queue, in igt_global_reset_lock()
23 !test_bit(I915_RESET_BACKOFF, &gt->reset.flags)); in igt_global_reset_lock()
27 &gt->reset.flags)) in igt_global_reset_lock()
28 wait_on_bit(&gt->reset.flags, I915_RESET_ENGINE + id, in igt_global_reset_lock()
39 clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags); in igt_global_reset_unlock()
41 clear_bit(I915_RESET_BACKOFF, &gt->reset.flags); in igt_global_reset_unlock()
42 wake_up_all(&gt->reset.queue); in igt_global_reset_unlock()
/drivers/clk/bcm/
Dclk-bcm2711-dvp.c18 struct reset_simple_data reset; member
49 dvp->reset.rcdev.owner = THIS_MODULE; in clk_dvp_probe()
50 dvp->reset.rcdev.nr_resets = NR_RESETS; in clk_dvp_probe()
51 dvp->reset.rcdev.ops = &reset_simple_ops; in clk_dvp_probe()
52 dvp->reset.rcdev.of_node = pdev->dev.of_node; in clk_dvp_probe()
53 dvp->reset.membase = base + DVP_HT_RPI_SW_INIT; in clk_dvp_probe()
54 spin_lock_init(&dvp->reset.lock); in clk_dvp_probe()
56 ret = devm_reset_controller_register(&pdev->dev, &dvp->reset.rcdev); in clk_dvp_probe()
65 &dvp->reset.lock); in clk_dvp_probe()
74 &dvp->reset.lock); in clk_dvp_probe()
/drivers/watchdog/
Dmena21_wdt.c44 int reset = 0; in a21_wdt_get_bootstatus() local
46 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0; in a21_wdt_get_bootstatus()
47 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0; in a21_wdt_get_bootstatus()
48 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0; in a21_wdt_get_bootstatus()
50 return reset; in a21_wdt_get_bootstatus()
132 unsigned int reset = 0; in a21_wdt_probe() local
179 reset = a21_wdt_get_bootstatus(drv); in a21_wdt_probe()
180 if (reset == 2) in a21_wdt_probe()
182 else if (reset == 4) in a21_wdt_probe()
184 else if (reset == 5) in a21_wdt_probe()
[all …]
/drivers/phy/qualcomm/
Dphy-ath79-usb.c14 struct reset_control *reset; member
32 err = reset_control_deassert(priv->reset); in ath79_usb_phy_power_on()
44 err = reset_control_assert(priv->reset); in ath79_usb_phy_power_off()
51 reset_control_deassert(priv->reset); in ath79_usb_phy_power_off()
72 priv->reset = devm_reset_control_get(&pdev->dev, "phy"); in ath79_usb_phy_probe()
73 if (IS_ERR(priv->reset)) in ath79_usb_phy_probe()
74 return PTR_ERR(priv->reset); in ath79_usb_phy_probe()
Dphy-qcom-usb-hs.c36 struct reset_control *reset; member
150 if (uphy->reset) { in qcom_usb_hs_phy_power_on()
151 ret = reset_control_reset(uphy->reset); in qcom_usb_hs_phy_power_on()
207 struct reset_control *reset; in qcom_usb_hs_phy_probe() local
247 uphy->reset = reset = devm_reset_control_get(&ulpi->dev, "por"); in qcom_usb_hs_phy_probe()
248 if (IS_ERR(reset)) { in qcom_usb_hs_phy_probe()
249 if (PTR_ERR(reset) == -EPROBE_DEFER) in qcom_usb_hs_phy_probe()
250 return PTR_ERR(reset); in qcom_usb_hs_phy_probe()
251 uphy->reset = NULL; in qcom_usb_hs_phy_probe()
/drivers/clk/meson/
Dmeson-aoclk.c26 container_of(rcdev, struct meson_aoclk_reset_controller, reset); in meson_aoclk_do_reset()
29 BIT(rstc->data->reset[id])); in meson_aoclk_do_reset()
33 .reset = meson_aoclk_do_reset,
64 rstc->reset.ops = &meson_aoclk_reset_ops; in meson_aoclkc_probe()
65 rstc->reset.nr_resets = data->num_reset; in meson_aoclkc_probe()
66 rstc->reset.of_node = dev->of_node; in meson_aoclkc_probe()
67 ret = devm_reset_controller_register(dev, &rstc->reset); in meson_aoclkc_probe()
/drivers/phy/amlogic/
Dphy-meson-axg-pcie.c31 struct reset_control *reset; member
79 return reset_control_reset(priv->reset); in phy_axg_pcie_init()
91 return reset_control_reset(priv->reset); in phy_axg_pcie_exit()
103 ret = reset_control_assert(priv->reset); in phy_axg_pcie_reset()
108 ret = reset_control_deassert(priv->reset); in phy_axg_pcie_reset()
122 .reset = phy_axg_pcie_reset,
158 priv->reset = devm_reset_control_array_get(dev, false, false); in phy_axg_pcie_probe()
159 if (IS_ERR(priv->reset)) in phy_axg_pcie_probe()
160 return PTR_ERR(priv->reset); in phy_axg_pcie_probe()
/drivers/phy/allwinner/
Dphy-sun9i-usb.c38 struct reset_control *reset; member
79 ret = reset_control_deassert(phy->reset); in sun9i_usb_phy_init()
101 reset_control_assert(phy->reset); in sun9i_usb_phy_exit()
140 phy->reset = devm_reset_control_get(dev, "hsic"); in sun9i_usb_phy_probe()
141 if (IS_ERR(phy->reset)) { in sun9i_usb_phy_probe()
143 return PTR_ERR(phy->reset); in sun9i_usb_phy_probe()
152 phy->reset = devm_reset_control_get(dev, "phy"); in sun9i_usb_phy_probe()
153 if (IS_ERR(phy->reset)) { in sun9i_usb_phy_probe()
155 return PTR_ERR(phy->reset); in sun9i_usb_phy_probe()
/drivers/gpu/drm/sun4i/
Dsun6i_drc.c19 struct reset_control *reset; member
33 drc->reset = devm_reset_control_get(dev, NULL); in sun6i_drc_bind()
34 if (IS_ERR(drc->reset)) { in sun6i_drc_bind()
36 return PTR_ERR(drc->reset); in sun6i_drc_bind()
39 ret = reset_control_deassert(drc->reset); in sun6i_drc_bind()
73 reset_control_assert(drc->reset); in sun6i_drc_bind()
85 reset_control_assert(drc->reset); in sun6i_drc_unbind()
/drivers/vfio/platform/
Dvfio_platform_private.h105 #define module_vfio_reset_handler(compat, reset) \ argument
107 static int __init reset ## _module_init(void) \
109 vfio_platform_register_reset(compat, reset); \
112 static void __exit reset ## _module_exit(void) \
114 vfio_platform_unregister_reset(compat, reset); \
116 module_init(reset ## _module_init); \
117 module_exit(reset ## _module_exit)
/drivers/vfio/platform/reset/
DKconfig3 tristate "VFIO support for calxeda xgmac reset"
6 Enables the VFIO platform driver to handle reset for Calxeda xgmac
11 tristate "VFIO support for AMD XGBE reset"
14 Enables the VFIO platform driver to handle reset for AMD XGBE
19 tristate "VFIO support for Broadcom FlexRM reset"
23 Enables the VFIO platform driver to handle reset for Broadcom FlexRM
/drivers/clk/mmp/
Dpwr-island.c21 u32 reset; member
46 if (pm_domain->reset || pm_domain->clock_enable) { in mmp_pm_domain_power_on()
49 val &= ~pm_domain->reset; in mmp_pm_domain_power_on()
55 val |= pm_domain->reset; in mmp_pm_domain_power_on()
93 u32 power_on, u32 reset, u32 clock_enable, in mmp_pm_domain_register() argument
104 pm_domain->reset = reset; in mmp_pm_domain_register()
/drivers/net/ethernet/mellanox/mlx4/
Dreset.c44 void __iomem *reset; in mlx4_reset() local
92 reset = ioremap(pci_resource_start(dev->persist->pdev, 0) + in mlx4_reset()
95 if (!reset) { in mlx4_reset()
104 sem = readl(reset + MLX4_SEM_OFFSET); in mlx4_reset()
114 iounmap(reset); in mlx4_reset()
119 writel(MLX4_RESET_VALUE, reset + MLX4_RESET_OFFSET); in mlx4_reset()
120 iounmap(reset); in mlx4_reset()
/drivers/clk/qcom/
Dcommon.c21 struct qcom_reset_controller reset; member
244 struct qcom_reset_controller *reset; in qcom_cc_really_probe() local
256 reset = &cc->reset; in qcom_cc_really_probe()
257 reset->rcdev.of_node = dev->of_node; in qcom_cc_really_probe()
258 reset->rcdev.ops = &qcom_reset_ops; in qcom_cc_really_probe()
259 reset->rcdev.owner = dev->driver->owner; in qcom_cc_really_probe()
260 reset->rcdev.nr_resets = desc->num_resets; in qcom_cc_really_probe()
261 reset->regmap = regmap; in qcom_cc_really_probe()
262 reset->reset_map = desc->resets; in qcom_cc_really_probe()
264 ret = devm_reset_controller_register(dev, &reset->rcdev); in qcom_cc_really_probe()
[all …]
/drivers/ata/
Dpata_palmld.c35 struct gpio_desc *reset; member
74 lda->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); in palmld_pata_probe()
75 if (IS_ERR(lda->reset)) { in palmld_pata_probe()
77 return PTR_ERR(lda->reset); in palmld_pata_probe()
81 gpiod_set_value(lda->reset, 1); in palmld_pata_probe()
83 gpiod_set_value(lda->reset, 0); in palmld_pata_probe()
/drivers/input/keyboard/
Dsunkbd.c69 volatile s8 reset; member
83 if (sunkbd->reset <= -1) { in sunkbd_interrupt()
88 sunkbd->reset = data; in sunkbd_interrupt()
104 sunkbd->reset = -1; in sunkbd_interrupt()
181 sunkbd->reset = -2; in sunkbd_initialize()
183 wait_event_interruptible_timeout(sunkbd->wait, sunkbd->reset >= 0, HZ); in sunkbd_initialize()
184 if (sunkbd->reset < 0) in sunkbd_initialize()
187 sunkbd->type = sunkbd->reset; in sunkbd_initialize()
238 sunkbd->reset >= 0 || !sunkbd->enabled, in sunkbd_reinit()
241 if (sunkbd->reset >= 0 && sunkbd->enabled) in sunkbd_reinit()
/drivers/staging/mt7621-pci/
Dmediatek,mt7621-pci.txt18 - resets: Must contain an entry for each entry in reset-names.
19 See ../reset/reset.txt for details.
20 - reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
26 - reset-gpios: GPIO specs for the reset pins.
72 reset-names = "pcie0", "pcie1", "pcie2";
76 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,

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