• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1# SPDX-License-Identifier: GPL-2.0-only
2config ARCH_HAS_RESET_CONTROLLER
3	bool
4
5menuconfig RESET_CONTROLLER
6	bool "Reset Controller Support"
7	default y if ARCH_HAS_RESET_CONTROLLER
8	help
9	  Generic Reset Controller support.
10
11	  This framework is designed to abstract reset handling of devices
12	  via GPIOs or SoC-internal reset controller modules.
13
14	  If unsure, say no.
15
16if RESET_CONTROLLER
17
18config RESET_A10SR
19	tristate "Altera Arria10 System Resource Reset"
20	depends on MFD_ALTERA_A10SR
21	help
22	  This option enables support for the external reset functions for
23	  peripheral PHYs on the Altera Arria10 System Resource Chip.
24
25config RESET_ATH79
26	bool "AR71xx Reset Driver" if COMPILE_TEST
27	default ATH79
28	help
29	  This enables the ATH79 reset controller driver that supports the
30	  AR71xx SoC reset controller.
31
32config RESET_AXS10X
33	bool "AXS10x Reset Driver" if COMPILE_TEST
34	default ARC_PLAT_AXS10X
35	help
36	  This enables the reset controller driver for AXS10x.
37
38config RESET_BERLIN
39	bool "Berlin Reset Driver" if COMPILE_TEST
40	default ARCH_BERLIN
41	help
42	  This enables the reset controller driver for Marvell Berlin SoCs.
43
44config RESET_BRCMSTB
45	tristate "Broadcom STB reset controller"
46	depends on ARCH_BRCMSTB || COMPILE_TEST
47	default ARCH_BRCMSTB
48	help
49	  This enables the reset controller driver for Broadcom STB SoCs using
50	  a SUN_TOP_CTRL_SW_INIT style controller.
51
52config RESET_BRCMSTB_RESCAL
53	bool "Broadcom STB RESCAL reset controller"
54	depends on HAS_IOMEM
55	depends on ARCH_BRCMSTB || COMPILE_TEST
56	default ARCH_BRCMSTB
57	help
58	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
59	  BCM7216.
60
61config RESET_HSDK
62	bool "Synopsys HSDK Reset Driver"
63	depends on HAS_IOMEM
64	depends on ARC_SOC_HSDK || COMPILE_TEST
65	help
66	  This enables the reset controller driver for HSDK board.
67
68config RESET_IMX7
69	tristate "i.MX7/8 Reset Driver"
70	depends on HAS_IOMEM
71	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
72	default y if SOC_IMX7D
73	select MFD_SYSCON
74	help
75	  This enables the reset controller driver for i.MX7 SoCs.
76
77config RESET_INTEL_GW
78	bool "Intel Reset Controller Driver"
79	depends on X86 || COMPILE_TEST
80	depends on OF && HAS_IOMEM
81	select REGMAP_MMIO
82	help
83	  This enables the reset controller driver for Intel Gateway SoCs.
84	  Say Y to control the reset signals provided by reset controller.
85	  Otherwise, say N.
86
87config RESET_LANTIQ
88	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
89	default SOC_TYPE_XWAY
90	help
91	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
92
93config RESET_LPC18XX
94	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
95	default ARCH_LPC18XX
96	help
97	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
98
99config RESET_MESON
100	tristate "Meson Reset Driver"
101	depends on ARCH_MESON || COMPILE_TEST
102	default ARCH_MESON
103	help
104	  This enables the reset driver for Amlogic Meson SoCs.
105
106config RESET_MESON_AUDIO_ARB
107	tristate "Meson Audio Memory Arbiter Reset Driver"
108	depends on ARCH_MESON || COMPILE_TEST
109	help
110	  This enables the reset driver for Audio Memory Arbiter of
111	  Amlogic's A113 based SoCs
112
113config RESET_NPCM
114	bool "NPCM BMC Reset Driver" if COMPILE_TEST
115	default ARCH_NPCM
116	help
117	  This enables the reset controller driver for Nuvoton NPCM
118	  BMC SoCs.
119
120config RESET_OXNAS
121	bool
122
123config RESET_PISTACHIO
124	bool "Pistachio Reset Driver" if COMPILE_TEST
125	default MACH_PISTACHIO
126	help
127	  This enables the reset driver for ImgTec Pistachio SoCs.
128
129config RESET_QCOM_AOSS
130	tristate "Qcom AOSS Reset Driver"
131	depends on ARCH_QCOM || COMPILE_TEST
132	help
133	  This enables the AOSS (always on subsystem) reset driver
134	  for Qualcomm SDM845 SoCs. Say Y if you want to control
135	  reset signals provided by AOSS for Modem, Venus, ADSP,
136	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
137
138config RESET_QCOM_PDC
139	tristate "Qualcomm PDC Reset Driver"
140	depends on ARCH_QCOM || COMPILE_TEST
141	help
142	  This enables the PDC (Power Domain Controller) reset driver
143	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
144	  to control reset signals provided by PDC for Modem, Compute,
145	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
146
147config RESET_RASPBERRYPI
148	tristate "Raspberry Pi 4 Firmware Reset Driver"
149	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
150	default USB_XHCI_PCI
151	help
152	  Raspberry Pi 4's co-processor controls some of the board's HW
153	  initialization process, but it's up to Linux to trigger it when
154	  relevant. This driver provides a reset controller capable of
155	  interfacing with RPi4's co-processor and model these firmware
156	  initialization routines as reset lines.
157
158config RESET_SCMI
159	tristate "Reset driver controlled via ARM SCMI interface"
160	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
161	default ARM_SCMI_PROTOCOL
162	help
163	  This driver provides support for reset signal/domains that are
164	  controlled by firmware that implements the SCMI interface.
165
166	  This driver uses SCMI Message Protocol to interact with the
167	  firmware controlling all the reset signals.
168
169config RESET_SIMPLE
170	bool "Simple Reset Controller Driver" if COMPILE_TEST
171	default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
172	help
173	  This enables a simple reset controller driver for reset lines that
174	  that can be asserted and deasserted by toggling bits in a contiguous,
175	  exclusive register space.
176
177	  Currently this driver supports:
178	   - Altera SoCFPGAs
179	   - ASPEED BMC SoCs
180	   - Bitmain BM1880 SoC
181	   - Realtek SoCs
182	   - RCC reset controller in STM32 MCUs
183	   - Allwinner SoCs
184	   - ZTE's zx2967 family
185
186config RESET_STM32MP157
187	bool "STM32MP157 Reset Driver" if COMPILE_TEST
188	default MACH_STM32MP157
189	help
190	  This enables the RCC reset controller driver for STM32 MPUs.
191
192config RESET_SOCFPGA
193	bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
194	default ARCH_SOCFPGA
195	select RESET_SIMPLE
196	help
197	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
198	  driver gets initialized early during platform init calls.
199
200config RESET_SUNXI
201	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
202	default ARCH_SUNXI
203	select RESET_SIMPLE
204	help
205	  This enables the reset driver for Allwinner SoCs.
206
207config RESET_TI_SCI
208	tristate "TI System Control Interface (TI-SCI) reset driver"
209	depends on TI_SCI_PROTOCOL
210	help
211	  This enables the reset driver support over TI System Control Interface
212	  available on some new TI's SoCs. If you wish to use reset resources
213	  managed by the TI System Controller, say Y here. Otherwise, say N.
214
215config RESET_TI_SYSCON
216	tristate "TI SYSCON Reset Driver"
217	depends on HAS_IOMEM
218	select MFD_SYSCON
219	help
220	  This enables the reset driver support for TI devices with
221	  memory-mapped reset registers as part of a syscon device node. If
222	  you wish to use the reset framework for such memory-mapped devices,
223	  say Y here. Otherwise, say N.
224
225config RESET_UNIPHIER
226	tristate "Reset controller driver for UniPhier SoCs"
227	depends on ARCH_UNIPHIER || COMPILE_TEST
228	depends on OF && MFD_SYSCON
229	default ARCH_UNIPHIER
230	help
231	  Support for reset controllers on UniPhier SoCs.
232	  Say Y if you want to control reset signals provided by System Control
233	  block, Media I/O block, Peripheral Block.
234
235config RESET_UNIPHIER_GLUE
236	tristate "Reset driver in glue layer for UniPhier SoCs"
237	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
238	default ARCH_UNIPHIER
239	select RESET_SIMPLE
240	help
241	  Support for peripheral core reset included in its own glue layer
242	  on UniPhier SoCs. Say Y if you want to control reset signals
243	  provided by the glue layer.
244
245config RESET_ZYNQ
246	bool "ZYNQ Reset Driver" if COMPILE_TEST
247	default ARCH_ZYNQ
248	help
249	  This enables the reset controller driver for Xilinx Zynq SoCs.
250
251source "drivers/reset/sti/Kconfig"
252source "drivers/reset/hisilicon/Kconfig"
253source "drivers/reset/tegra/Kconfig"
254
255endif
256