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Searched refs:ti_clk_get_reg_addr (Results 1 – 9 of 9) sorted by relevance

/drivers/clk/ti/
Dapll.c220 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); in of_dra7_apll_setup()
221 ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg); in of_dra7_apll_setup()
403 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); in of_omap2_apll_setup()
404 ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg); in of_omap2_apll_setup()
405 ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg); in of_omap2_apll_setup()
Ddpll.c262 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { in _register_dpll_x2()
324 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) in of_ti_dpll_setup()
333 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) in of_ti_dpll_setup()
340 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) in of_ti_dpll_setup()
343 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) in of_ti_dpll_setup()
348 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) in of_ti_dpll_setup()
Dgate.c148 if (ti_clk_get_reg_addr(node, 0, &reg)) in _of_ti_gate_clk_setup()
187 if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg)) in _of_ti_composite_gate_clk_setup()
Dmux.c197 if (ti_clk_get_reg_addr(node, 0, &reg)) in of_mux_clk_setup()
269 if (ti_clk_get_reg_addr(node, 0, &mux->reg)) in of_ti_composite_mux_clk_setup()
Dinterface.c79 if (ti_clk_get_reg_addr(node, 0, &reg)) in _of_ti_interface_clk_setup()
Dautoidle.c209 ret = ti_clk_get_reg_addr(node, 0, &clk->reg); in of_ti_clk_autoidle_setup()
Dclock.h228 int ti_clk_get_reg_addr(struct device_node *node, int index,
Dclk.c268 int ti_clk_get_reg_addr(struct device_node *node, int index, in ti_clk_get_reg_addr() function
Ddivider.c484 ret = ti_clk_get_reg_addr(node, 0, &div->reg); in ti_clk_divider_populate()