1 /*
2 * OMAP DPLL clock support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/clk/ti.h>
25 #include "clock.h"
26
27 #undef pr_fmt
28 #define pr_fmt(fmt) "%s: " fmt, __func__
29
30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
31 defined(CONFIG_SOC_DRA7XX)
32 static const struct clk_ops dpll_m4xen_ck_ops = {
33 .enable = &omap3_noncore_dpll_enable,
34 .disable = &omap3_noncore_dpll_disable,
35 .recalc_rate = &omap4_dpll_regm4xen_recalc,
36 .round_rate = &omap4_dpll_regm4xen_round_rate,
37 .set_rate = &omap3_noncore_dpll_set_rate,
38 .set_parent = &omap3_noncore_dpll_set_parent,
39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
40 .determine_rate = &omap4_dpll_regm4xen_determine_rate,
41 .get_parent = &omap2_init_dpll_parent,
42 .save_context = &omap3_core_dpll_save_context,
43 .restore_context = &omap3_core_dpll_restore_context,
44 };
45 #else
46 static const struct clk_ops dpll_m4xen_ck_ops = {};
47 #endif
48
49 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
50 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
51 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
52 static const struct clk_ops dpll_core_ck_ops = {
53 .recalc_rate = &omap3_dpll_recalc,
54 .get_parent = &omap2_init_dpll_parent,
55 };
56
57 static const struct clk_ops dpll_ck_ops = {
58 .enable = &omap3_noncore_dpll_enable,
59 .disable = &omap3_noncore_dpll_disable,
60 .recalc_rate = &omap3_dpll_recalc,
61 .round_rate = &omap2_dpll_round_rate,
62 .set_rate = &omap3_noncore_dpll_set_rate,
63 .set_parent = &omap3_noncore_dpll_set_parent,
64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
65 .determine_rate = &omap3_noncore_dpll_determine_rate,
66 .get_parent = &omap2_init_dpll_parent,
67 .save_context = &omap3_noncore_dpll_save_context,
68 .restore_context = &omap3_noncore_dpll_restore_context,
69 };
70
71 static const struct clk_ops dpll_no_gate_ck_ops = {
72 .recalc_rate = &omap3_dpll_recalc,
73 .get_parent = &omap2_init_dpll_parent,
74 .round_rate = &omap2_dpll_round_rate,
75 .set_rate = &omap3_noncore_dpll_set_rate,
76 .set_parent = &omap3_noncore_dpll_set_parent,
77 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
78 .determine_rate = &omap3_noncore_dpll_determine_rate,
79 .save_context = &omap3_noncore_dpll_save_context,
80 .restore_context = &omap3_noncore_dpll_restore_context
81 };
82 #else
83 static const struct clk_ops dpll_core_ck_ops = {};
84 static const struct clk_ops dpll_ck_ops = {};
85 static const struct clk_ops dpll_no_gate_ck_ops = {};
86 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
87 #endif
88
89 #ifdef CONFIG_ARCH_OMAP2
90 static const struct clk_ops omap2_dpll_core_ck_ops = {
91 .get_parent = &omap2_init_dpll_parent,
92 .recalc_rate = &omap2_dpllcore_recalc,
93 .round_rate = &omap2_dpll_round_rate,
94 .set_rate = &omap2_reprogram_dpllcore,
95 };
96 #else
97 static const struct clk_ops omap2_dpll_core_ck_ops = {};
98 #endif
99
100 #ifdef CONFIG_ARCH_OMAP3
101 static const struct clk_ops omap3_dpll_core_ck_ops = {
102 .get_parent = &omap2_init_dpll_parent,
103 .recalc_rate = &omap3_dpll_recalc,
104 .round_rate = &omap2_dpll_round_rate,
105 };
106 #else
107 static const struct clk_ops omap3_dpll_core_ck_ops = {};
108 #endif
109
110 #ifdef CONFIG_ARCH_OMAP3
111 static const struct clk_ops omap3_dpll_ck_ops = {
112 .enable = &omap3_noncore_dpll_enable,
113 .disable = &omap3_noncore_dpll_disable,
114 .get_parent = &omap2_init_dpll_parent,
115 .recalc_rate = &omap3_dpll_recalc,
116 .set_rate = &omap3_noncore_dpll_set_rate,
117 .set_parent = &omap3_noncore_dpll_set_parent,
118 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
119 .determine_rate = &omap3_noncore_dpll_determine_rate,
120 .round_rate = &omap2_dpll_round_rate,
121 };
122
123 static const struct clk_ops omap3_dpll5_ck_ops = {
124 .enable = &omap3_noncore_dpll_enable,
125 .disable = &omap3_noncore_dpll_disable,
126 .get_parent = &omap2_init_dpll_parent,
127 .recalc_rate = &omap3_dpll_recalc,
128 .set_rate = &omap3_dpll5_set_rate,
129 .set_parent = &omap3_noncore_dpll_set_parent,
130 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
131 .determine_rate = &omap3_noncore_dpll_determine_rate,
132 .round_rate = &omap2_dpll_round_rate,
133 };
134
135 static const struct clk_ops omap3_dpll_per_ck_ops = {
136 .enable = &omap3_noncore_dpll_enable,
137 .disable = &omap3_noncore_dpll_disable,
138 .get_parent = &omap2_init_dpll_parent,
139 .recalc_rate = &omap3_dpll_recalc,
140 .set_rate = &omap3_dpll4_set_rate,
141 .set_parent = &omap3_noncore_dpll_set_parent,
142 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
143 .determine_rate = &omap3_noncore_dpll_determine_rate,
144 .round_rate = &omap2_dpll_round_rate,
145 };
146 #endif
147
148 static const struct clk_ops dpll_x2_ck_ops = {
149 .recalc_rate = &omap3_clkoutx2_recalc,
150 };
151
152 /**
153 * _register_dpll - low level registration of a DPLL clock
154 * @hw: hardware clock definition for the clock
155 * @node: device node for the clock
156 *
157 * Finalizes DPLL registration process. In case a failure (clk-ref or
158 * clk-bypass is missing), the clock is added to retry list and
159 * the initialization is retried on later stage.
160 */
_register_dpll(void * user,struct device_node * node)161 static void __init _register_dpll(void *user,
162 struct device_node *node)
163 {
164 struct clk_hw *hw = user;
165 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
166 struct dpll_data *dd = clk_hw->dpll_data;
167 const char *name;
168 struct clk *clk;
169 const struct clk_init_data *init = hw->init;
170
171 clk = of_clk_get(node, 0);
172 if (IS_ERR(clk)) {
173 pr_debug("clk-ref missing for %pOFn, retry later\n",
174 node);
175 if (!ti_clk_retry_init(node, hw, _register_dpll))
176 return;
177
178 goto cleanup;
179 }
180
181 dd->clk_ref = __clk_get_hw(clk);
182
183 clk = of_clk_get(node, 1);
184
185 if (IS_ERR(clk)) {
186 pr_debug("clk-bypass missing for %pOFn, retry later\n",
187 node);
188 if (!ti_clk_retry_init(node, hw, _register_dpll))
189 return;
190
191 goto cleanup;
192 }
193
194 dd->clk_bypass = __clk_get_hw(clk);
195
196 /* register the clock */
197 name = ti_dt_clk_name(node);
198 clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
199
200 if (!IS_ERR(clk)) {
201 of_clk_add_provider(node, of_clk_src_simple_get, clk);
202 kfree(init->parent_names);
203 kfree(init);
204 return;
205 }
206
207 cleanup:
208 kfree(clk_hw->dpll_data);
209 kfree(init->parent_names);
210 kfree(init);
211 kfree(clk_hw);
212 }
213
214 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
215 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
216 defined(CONFIG_SOC_AM43XX)
217 /**
218 * _register_dpll_x2 - Registers a DPLLx2 clock
219 * @node: device node for this clock
220 * @ops: clk_ops for this clock
221 * @hw_ops: clk_hw_ops for this clock
222 *
223 * Initializes a DPLL x 2 clock from device tree data.
224 */
_register_dpll_x2(struct device_node * node,const struct clk_ops * ops,const struct clk_hw_omap_ops * hw_ops)225 static void _register_dpll_x2(struct device_node *node,
226 const struct clk_ops *ops,
227 const struct clk_hw_omap_ops *hw_ops)
228 {
229 struct clk *clk;
230 struct clk_init_data init = { NULL };
231 struct clk_hw_omap *clk_hw;
232 const char *name = ti_dt_clk_name(node);
233 const char *parent_name;
234
235 parent_name = of_clk_get_parent_name(node, 0);
236 if (!parent_name) {
237 pr_err("%pOFn must have parent\n", node);
238 return;
239 }
240
241 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
242 if (!clk_hw)
243 return;
244
245 clk_hw->ops = hw_ops;
246 clk_hw->hw.init = &init;
247
248 init.name = name;
249 init.ops = ops;
250 init.parent_names = &parent_name;
251 init.num_parents = 1;
252
253 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
254 defined(CONFIG_SOC_DRA7XX)
255 if (hw_ops == &clkhwops_omap4_dpllmx) {
256 int ret;
257
258 /* Check if register defined, if not, drop hw-ops */
259 ret = of_property_count_elems_of_size(node, "reg", 1);
260 if (ret <= 0) {
261 clk_hw->ops = NULL;
262 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
263 kfree(clk_hw);
264 return;
265 }
266 }
267 #endif
268
269 /* register the clock */
270 clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
271
272 if (IS_ERR(clk))
273 kfree(clk_hw);
274 else
275 of_clk_add_provider(node, of_clk_src_simple_get, clk);
276 }
277 #endif
278
279 /**
280 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
281 * @node: device node containing the DPLL info
282 * @ops: ops for the DPLL
283 * @ddt: DPLL data template to use
284 *
285 * Initializes a DPLL clock from device tree data.
286 */
of_ti_dpll_setup(struct device_node * node,const struct clk_ops * ops,const struct dpll_data * ddt)287 static void __init of_ti_dpll_setup(struct device_node *node,
288 const struct clk_ops *ops,
289 const struct dpll_data *ddt)
290 {
291 struct clk_hw_omap *clk_hw = NULL;
292 struct clk_init_data *init = NULL;
293 const char **parent_names = NULL;
294 struct dpll_data *dd = NULL;
295 u8 dpll_mode = 0;
296
297 dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
298 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
299 init = kzalloc(sizeof(*init), GFP_KERNEL);
300 if (!dd || !clk_hw || !init)
301 goto cleanup;
302
303 clk_hw->dpll_data = dd;
304 clk_hw->ops = &clkhwops_omap3_dpll;
305 clk_hw->hw.init = init;
306
307 init->name = ti_dt_clk_name(node);
308 init->ops = ops;
309
310 init->num_parents = of_clk_get_parent_count(node);
311 if (!init->num_parents) {
312 pr_err("%pOFn must have parent(s)\n", node);
313 goto cleanup;
314 }
315
316 parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
317 if (!parent_names)
318 goto cleanup;
319
320 of_clk_parent_fill(node, parent_names, init->num_parents);
321
322 init->parent_names = parent_names;
323
324 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
325 goto cleanup;
326
327 /*
328 * Special case for OMAP2 DPLL, register order is different due to
329 * missing idlest_reg, also clkhwops is different. Detected from
330 * missing idlest_mask.
331 */
332 if (!dd->idlest_mask) {
333 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
334 goto cleanup;
335 #ifdef CONFIG_ARCH_OMAP2
336 clk_hw->ops = &clkhwops_omap2xxx_dpll;
337 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
338 #endif
339 } else {
340 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
341 goto cleanup;
342
343 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
344 goto cleanup;
345 }
346
347 if (dd->autoidle_mask) {
348 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
349 goto cleanup;
350 }
351
352 if (of_property_read_bool(node, "ti,low-power-stop"))
353 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
354
355 if (of_property_read_bool(node, "ti,low-power-bypass"))
356 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
357
358 if (of_property_read_bool(node, "ti,lock"))
359 dpll_mode |= 1 << DPLL_LOCKED;
360
361 if (dpll_mode)
362 dd->modes = dpll_mode;
363
364 _register_dpll(&clk_hw->hw, node);
365 return;
366
367 cleanup:
368 kfree(dd);
369 kfree(parent_names);
370 kfree(init);
371 kfree(clk_hw);
372 }
373
374 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
375 defined(CONFIG_SOC_DRA7XX)
of_ti_omap4_dpll_x2_setup(struct device_node * node)376 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
377 {
378 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
379 }
380 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
381 of_ti_omap4_dpll_x2_setup);
382 #endif
383
384 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
of_ti_am3_dpll_x2_setup(struct device_node * node)385 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
386 {
387 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
388 }
389 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
390 of_ti_am3_dpll_x2_setup);
391 #endif
392
393 #ifdef CONFIG_ARCH_OMAP3
of_ti_omap3_dpll_setup(struct device_node * node)394 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
395 {
396 const struct dpll_data dd = {
397 .idlest_mask = 0x1,
398 .enable_mask = 0x7,
399 .autoidle_mask = 0x7,
400 .mult_mask = 0x7ff << 8,
401 .div1_mask = 0x7f,
402 .max_multiplier = 2047,
403 .max_divider = 128,
404 .min_divider = 1,
405 .freqsel_mask = 0xf0,
406 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
407 };
408
409 if ((of_machine_is_compatible("ti,omap3630") ||
410 of_machine_is_compatible("ti,omap36xx")) &&
411 of_node_name_eq(node, "dpll5_ck"))
412 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
413 else
414 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
415 }
416 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
417 of_ti_omap3_dpll_setup);
418
of_ti_omap3_core_dpll_setup(struct device_node * node)419 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
420 {
421 const struct dpll_data dd = {
422 .idlest_mask = 0x1,
423 .enable_mask = 0x7,
424 .autoidle_mask = 0x7,
425 .mult_mask = 0x7ff << 16,
426 .div1_mask = 0x7f << 8,
427 .max_multiplier = 2047,
428 .max_divider = 128,
429 .min_divider = 1,
430 .freqsel_mask = 0xf0,
431 };
432
433 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
434 }
435 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
436 of_ti_omap3_core_dpll_setup);
437
of_ti_omap3_per_dpll_setup(struct device_node * node)438 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
439 {
440 const struct dpll_data dd = {
441 .idlest_mask = 0x1 << 1,
442 .enable_mask = 0x7 << 16,
443 .autoidle_mask = 0x7 << 3,
444 .mult_mask = 0x7ff << 8,
445 .div1_mask = 0x7f,
446 .max_multiplier = 2047,
447 .max_divider = 128,
448 .min_divider = 1,
449 .freqsel_mask = 0xf00000,
450 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
451 };
452
453 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
454 }
455 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
456 of_ti_omap3_per_dpll_setup);
457
of_ti_omap3_per_jtype_dpll_setup(struct device_node * node)458 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
459 {
460 const struct dpll_data dd = {
461 .idlest_mask = 0x1 << 1,
462 .enable_mask = 0x7 << 16,
463 .autoidle_mask = 0x7 << 3,
464 .mult_mask = 0xfff << 8,
465 .div1_mask = 0x7f,
466 .max_multiplier = 4095,
467 .max_divider = 128,
468 .min_divider = 1,
469 .sddiv_mask = 0xff << 24,
470 .dco_mask = 0xe << 20,
471 .flags = DPLL_J_TYPE,
472 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
473 };
474
475 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
476 }
477 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
478 of_ti_omap3_per_jtype_dpll_setup);
479 #endif
480
of_ti_omap4_dpll_setup(struct device_node * node)481 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
482 {
483 const struct dpll_data dd = {
484 .idlest_mask = 0x1,
485 .enable_mask = 0x7,
486 .autoidle_mask = 0x7,
487 .mult_mask = 0x7ff << 8,
488 .div1_mask = 0x7f,
489 .max_multiplier = 2047,
490 .max_divider = 128,
491 .min_divider = 1,
492 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
493 };
494
495 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
496 }
497 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
498 of_ti_omap4_dpll_setup);
499
of_ti_omap5_mpu_dpll_setup(struct device_node * node)500 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
501 {
502 const struct dpll_data dd = {
503 .idlest_mask = 0x1,
504 .enable_mask = 0x7,
505 .autoidle_mask = 0x7,
506 .mult_mask = 0x7ff << 8,
507 .div1_mask = 0x7f,
508 .max_multiplier = 2047,
509 .max_divider = 128,
510 .dcc_mask = BIT(22),
511 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
512 .min_divider = 1,
513 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
514 };
515
516 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
517 }
518 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
519 of_ti_omap5_mpu_dpll_setup);
520
of_ti_omap4_core_dpll_setup(struct device_node * node)521 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
522 {
523 const struct dpll_data dd = {
524 .idlest_mask = 0x1,
525 .enable_mask = 0x7,
526 .autoidle_mask = 0x7,
527 .mult_mask = 0x7ff << 8,
528 .div1_mask = 0x7f,
529 .max_multiplier = 2047,
530 .max_divider = 128,
531 .min_divider = 1,
532 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
533 };
534
535 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
536 }
537 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
538 of_ti_omap4_core_dpll_setup);
539
540 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
541 defined(CONFIG_SOC_DRA7XX)
of_ti_omap4_m4xen_dpll_setup(struct device_node * node)542 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
543 {
544 const struct dpll_data dd = {
545 .idlest_mask = 0x1,
546 .enable_mask = 0x7,
547 .autoidle_mask = 0x7,
548 .mult_mask = 0x7ff << 8,
549 .div1_mask = 0x7f,
550 .max_multiplier = 2047,
551 .max_divider = 128,
552 .min_divider = 1,
553 .m4xen_mask = 0x800,
554 .lpmode_mask = 1 << 10,
555 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
556 };
557
558 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
559 }
560 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
561 of_ti_omap4_m4xen_dpll_setup);
562
of_ti_omap4_jtype_dpll_setup(struct device_node * node)563 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
564 {
565 const struct dpll_data dd = {
566 .idlest_mask = 0x1,
567 .enable_mask = 0x7,
568 .autoidle_mask = 0x7,
569 .mult_mask = 0xfff << 8,
570 .div1_mask = 0xff,
571 .max_multiplier = 4095,
572 .max_divider = 256,
573 .min_divider = 1,
574 .sddiv_mask = 0xff << 24,
575 .flags = DPLL_J_TYPE,
576 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
577 };
578
579 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
580 }
581 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
582 of_ti_omap4_jtype_dpll_setup);
583 #endif
584
of_ti_am3_no_gate_dpll_setup(struct device_node * node)585 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
586 {
587 const struct dpll_data dd = {
588 .idlest_mask = 0x1,
589 .enable_mask = 0x7,
590 .mult_mask = 0x7ff << 8,
591 .div1_mask = 0x7f,
592 .max_multiplier = 2047,
593 .max_divider = 128,
594 .min_divider = 1,
595 .max_rate = 1000000000,
596 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
597 };
598
599 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
600 }
601 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
602 of_ti_am3_no_gate_dpll_setup);
603
of_ti_am3_jtype_dpll_setup(struct device_node * node)604 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
605 {
606 const struct dpll_data dd = {
607 .idlest_mask = 0x1,
608 .enable_mask = 0x7,
609 .mult_mask = 0x7ff << 8,
610 .div1_mask = 0x7f,
611 .max_multiplier = 4095,
612 .max_divider = 256,
613 .min_divider = 2,
614 .flags = DPLL_J_TYPE,
615 .max_rate = 2000000000,
616 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
617 };
618
619 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
620 }
621 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
622 of_ti_am3_jtype_dpll_setup);
623
of_ti_am3_no_gate_jtype_dpll_setup(struct device_node * node)624 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
625 {
626 const struct dpll_data dd = {
627 .idlest_mask = 0x1,
628 .enable_mask = 0x7,
629 .mult_mask = 0x7ff << 8,
630 .div1_mask = 0x7f,
631 .max_multiplier = 2047,
632 .max_divider = 128,
633 .min_divider = 1,
634 .max_rate = 2000000000,
635 .flags = DPLL_J_TYPE,
636 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
637 };
638
639 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
640 }
641 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
642 "ti,am3-dpll-no-gate-j-type-clock",
643 of_ti_am3_no_gate_jtype_dpll_setup);
644
of_ti_am3_dpll_setup(struct device_node * node)645 static void __init of_ti_am3_dpll_setup(struct device_node *node)
646 {
647 const struct dpll_data dd = {
648 .idlest_mask = 0x1,
649 .enable_mask = 0x7,
650 .mult_mask = 0x7ff << 8,
651 .div1_mask = 0x7f,
652 .max_multiplier = 2047,
653 .max_divider = 128,
654 .min_divider = 1,
655 .max_rate = 1000000000,
656 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
657 };
658
659 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
660 }
661 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
662
of_ti_am3_core_dpll_setup(struct device_node * node)663 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
664 {
665 const struct dpll_data dd = {
666 .idlest_mask = 0x1,
667 .enable_mask = 0x7,
668 .mult_mask = 0x7ff << 8,
669 .div1_mask = 0x7f,
670 .max_multiplier = 2047,
671 .max_divider = 128,
672 .min_divider = 1,
673 .max_rate = 1000000000,
674 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
675 };
676
677 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
678 }
679 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
680 of_ti_am3_core_dpll_setup);
681
of_ti_omap2_core_dpll_setup(struct device_node * node)682 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
683 {
684 const struct dpll_data dd = {
685 .enable_mask = 0x3,
686 .mult_mask = 0x3ff << 12,
687 .div1_mask = 0xf << 8,
688 .max_divider = 16,
689 .min_divider = 1,
690 };
691
692 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
693 }
694 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
695 of_ti_omap2_core_dpll_setup);
696