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Searched refs:write_csr (Results 1 – 17 of 17) sorted by relevance

/drivers/infiniband/hw/hfi1/
Dfirmware.c280 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); in __read_8051_data()
282 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, in __read_8051_data()
317 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); in read_8051_data()
326 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); in read_8051_data()
349 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg); in write_8051()
354 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); in write_8051()
368 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg); in write_8051()
385 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); in write_8051()
386 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); in write_8051()
788 write_csr(dd, what + (8 * i), *ptr); in write_rsa_data()
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Dchip.c1362 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) in write_csr() function
1399 write_csr(dd, csr, value); in read_write_csr()
5724 write_csr(dd, SEND_EGRESS_ERR_INFO, info); in handle_send_egress_err_info()
6140 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6176 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6231 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_host_lcb_access()
6242 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_8051_lcb_access()
6365 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, in hreq_response()
6387 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); in handle_8051_request()
6408 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); in handle_8051_request()
[all …]
Deprom.c92 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset)); in read_page()
95 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */ in read_page()
193 write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_EP_RESET_SMASK); in eprom_init()
195 write_csr(dd, ASIC_EEP_CTL_STAT, in eprom_init()
199 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID); in eprom_init()
Dpcie.c882 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), in write_gasket_interrupt()
901 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); in arm_gasket_logic()
976 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); in write_xmt_margin()
1073 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in do_pcie_gen3_transition()
1299 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in do_pcie_gen3_transition()
1354 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); in do_pcie_gen3_transition()
1376 write_csr(dd, CCE_DC_CTRL, 0); in do_pcie_gen3_transition()
1432 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in do_pcie_gen3_transition()
Dchip.h618 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
636 write_csr(dd, offset0 + (0x100 * ctxt), value); in write_kctxt_csr()
671 write_csr(dd, offset0 + (0x1000 * ctxt), value); in write_uctxt_csr()
Dpio.c65 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK); in __cm_reset()
123 write_csr(dd, SEND_CTRL, reg); in pio_send_control()
1268 write_csr(dd, SEND_PIO_ERR_CLEAR, in pio_reset_all()
1273 write_csr(dd, SEND_PIO_INIT_CTXT, in pio_reset_all()
1346 write_csr(dd, SEND_PIO_INIT_CTXT, pio); in sc_enable()
Dqsfp.c85 write_csr(dd, target_oe, reg); in hfi1_setsda()
109 write_csr(dd, target_oe, reg); in hfi1_setscl()
Ddebugfs.c621 write_csr(dd, ASIC_CFG_SCRATCH, scratch0); in asic_flags_write()
1082 write_csr(dd, ASIC_GPIO_OUT, gpio_val); in exprom_wp_set()
1083 write_csr(dd, ASIC_GPIO_OE, gpio_val); in exprom_wp_set()
Dhfi.h2436 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); in setextled()
2438 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); in setextled()
Dmad.c1804 write_csr(dd, SEND_SC2VLT0, *val++); in set_sc2vlt_tables()
1805 write_csr(dd, SEND_SC2VLT1, *val++); in set_sc2vlt_tables()
1806 write_csr(dd, SEND_SC2VLT2, *val++); in set_sc2vlt_tables()
1807 write_csr(dd, SEND_SC2VLT3, *val++); in set_sc2vlt_tables()
3673 write_csr(dd, RCV_ERR_INFO, in pma_set_opa_errorinfo()
Dinit.c573 write_csr(dd, SEND_STATIC_RATE_CONTROL, src); in set_link_ipg()
Ddriver.c1360 write_csr(dd, DCC_CFG_LED_CNTRL, 0); in shutdown_led_override()
Dsdma.c3420 write_csr(sde->dd, in _sdma_engine_progress_schedule()
/drivers/net/ethernet/amd/
Dpcnet32.c243 void (*write_csr) (unsigned long, int, u16); member
383 .write_csr = pcnet32_wio_write_csr,
438 .write_csr = pcnet32_dwio_write_csr,
464 lp->a->write_csr(ioaddr, CSR3, val); in pcnet32_netif_start()
690 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); in pcnet32_suspend()
715 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND); in pcnet32_clr_suspend()
763 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); in pcnet32_set_link_ksettings()
776 lp->a->write_csr(ioaddr, CSR15, csr15); in pcnet32_set_link_ksettings()
889 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ in pcnet32_set_ringparam()
985 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ in pcnet32_loopback_test()
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/drivers/firewire/
Dcore.h92 void (*write_csr)(struct fw_card *card, int csr_offset, u32 value); member
Dcore-transaction.c1119 card->driver->write_csr(card, reg, be32_to_cpu(*data)); in handle_registers()
1126 card->driver->write_csr(card, CSR_STATE_CLEAR, in handle_registers()
Dohci.c3554 .write_csr = ohci_write_csr,