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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SMI (Smart Multimedia Interface) Common
9
10maintainers:
11  - Yong Wu <yong.wu@mediatek.com>
12
13description: |
14  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
15
16  MediaTek SMI have two generations of HW architecture, here is the list
17  which generation the SoCs use:
18  generation 1: mt2701 and mt7623.
19  generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
20
21  There's slight differences between the two SMI, for generation 2, the
22  register which control the iommu port is at each larb's register base. But
23  for generation 1, the register is at smi ao base(smi always on register
24  base). Besides that, the smi async clock should be prepared and enabled for
25  SMI generation 1 to transform the smi clock into emi clock domain, but that is
26  not needed for SMI generation 2.
27
28properties:
29  compatible:
30    oneOf:
31      - enum:
32          - mediatek,mt2701-smi-common
33          - mediatek,mt2712-smi-common
34          - mediatek,mt6779-smi-common
35          - mediatek,mt8167-smi-common
36          - mediatek,mt8173-smi-common
37          - mediatek,mt8183-smi-common
38
39      - description: for mt7623
40        items:
41          - const: mediatek,mt7623-smi-common
42          - const: mediatek,mt2701-smi-common
43
44  reg:
45    maxItems: 1
46
47  power-domains:
48    maxItems: 1
49
50  clocks:
51    description: |
52      apb and smi are mandatory. the async is only for generation 1 smi HW.
53      gals(global async local sync) also is optional, see below.
54    minItems: 2
55    maxItems: 4
56    items:
57      - description: apb is Advanced Peripheral Bus clock, It's the clock for
58          setting the register.
59      - description: smi is the clock for transfer data and command.
60      - description: async is asynchronous clock, it help transform the smi
61          clock into the emi clock domain.
62      - description: gals0 is the path0 clock of gals.
63      - description: gals1 is the path1 clock of gals.
64
65  clock-names:
66    minItems: 2
67    maxItems: 4
68
69required:
70  - compatible
71  - reg
72  - power-domains
73  - clocks
74  - clock-names
75
76allOf:
77  - if:  # only for gen1 HW
78      properties:
79        compatible:
80          contains:
81            enum:
82              - mediatek,mt2701-smi-common
83    then:
84      properties:
85        clocks:
86          minItems: 3
87          maxItems: 3
88        clock-names:
89          items:
90            - const: apb
91            - const: smi
92            - const: async
93
94  - if:  # for gen2 HW that have gals
95      properties:
96        compatible:
97          enum:
98            - mediatek,mt6779-smi-common
99            - mediatek,mt8183-smi-common
100
101    then:
102      properties:
103        clocks:
104          minItems: 4
105          maxItems: 4
106        clock-names:
107          items:
108            - const: apb
109            - const: smi
110            - const: gals0
111            - const: gals1
112
113    else:  # for gen2 HW that don't have gals
114      properties:
115        clocks:
116          minItems: 2
117          maxItems: 2
118        clock-names:
119          items:
120            - const: apb
121            - const: smi
122
123additionalProperties: false
124
125examples:
126  - |+
127    #include <dt-bindings/clock/mt8173-clk.h>
128    #include <dt-bindings/power/mt8173-power.h>
129
130    smi_common: smi@14022000 {
131            compatible = "mediatek,mt8173-smi-common";
132            reg = <0x14022000 0x1000>;
133            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
134            clocks = <&mmsys CLK_MM_SMI_COMMON>,
135                     <&mmsys CLK_MM_SMI_COMMON>;
136            clock-names = "apb", "smi";
137    };
138