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1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter) bindings
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: /schemas/serial.yaml#
14  - if:
15      required:
16        - aspeed,sirq-polarity-sense
17    then:
18      properties:
19        compatible:
20          const: aspeed,ast2500-vuart
21  - if:
22      properties:
23        compatible:
24          const: mrvl,mmp-uart
25    then:
26      properties:
27        reg-shift:
28          const: 2
29      required:
30        - reg-shift
31  - if:
32      not:
33        properties:
34          compatible:
35            items:
36              - enum:
37                  - ns8250
38                  - ns16450
39                  - ns16550
40                  - ns16550a
41    then:
42      anyOf:
43        - required: [ clock-frequency ]
44        - required: [ clocks ]
45
46properties:
47  compatible:
48    oneOf:
49      - const: ns8250
50      - const: ns16450
51      - const: ns16550
52      - const: ns16550a
53      - const: ns16850
54      - const: aspeed,ast2400-vuart
55      - const: aspeed,ast2500-vuart
56      - const: intel,xscale-uart
57      - const: mrvl,pxa-uart
58      - const: nuvoton,npcm750-uart
59      - const: nvidia,tegra20-uart
60      - const: nxp,lpc3220-uart
61      - items:
62          - enum:
63              - altr,16550-FIFO32
64              - altr,16550-FIFO64
65              - altr,16550-FIFO128
66              - fsl,16550-FIFO64
67              - fsl,ns16550
68              - andestech,uart16550
69              - nxp,lpc1850-uart
70              - opencores,uart16550-rtlsvn105
71              - ti,da830-uart
72          - const: ns16550a
73      - items:
74          - enum:
75              - ns16750
76              - cavium,octeon-3860-uart
77              - xlnx,xps-uart16550-2.00.b
78              - ralink,rt2880-uart
79          - enum:
80              - ns16550 # Deprecated, unless the FIFO really is broken
81              - ns16550a
82      - items:
83          - enum:
84              - ralink,mt7620a-uart
85              - ralink,rt3052-uart
86              - ralink,rt3883-uart
87          - const: ralink,rt2880-uart
88          - enum:
89              - ns16550 # Deprecated, unless the FIFO really is broken
90              - ns16550a
91      - items:
92          - enum:
93              - mediatek,mt7622-btif
94              - mediatek,mt7623-btif
95          - const: mediatek,mtk-btif
96      - items:
97          - const: mrvl,mmp-uart
98          - const: intel,xscale-uart
99      - items:
100          - enum:
101              - nvidia,tegra30-uart
102              - nvidia,tegra114-uart
103              - nvidia,tegra124-uart
104              - nvidia,tegra186-uart
105              - nvidia,tegra194-uart
106              - nvidia,tegra210-uart
107          - const: nvidia,tegra20-uart
108
109  reg:
110    maxItems: 1
111
112  interrupts:
113    maxItems: 1
114
115  clock-frequency: true
116
117  clocks:
118    maxItems: 1
119
120  resets:
121    maxItems: 1
122
123  current-speed:
124    $ref: /schemas/types.yaml#definitions/uint32
125    description: The current active speed of the UART.
126
127  reg-offset:
128    description: |
129      Offset to apply to the mapbase from the start of the registers.
130
131  reg-shift:
132    description: Quantity to shift the register offsets by.
133
134  reg-io-width:
135    description: |
136      The size (in bytes) of the IO accesses that should be performed on the
137      device. There are some systems that require 32-bit accesses to the
138      UART (e.g. TI davinci).
139
140  used-by-rtas:
141    type: boolean
142    description: |
143      Set to indicate that the port is in use by the OpenFirmware RTAS and
144      should not be registered.
145
146  no-loopback-test:
147    type: boolean
148    description: |
149      Set to indicate that the port does not implement loopback test mode.
150
151  fifo-size:
152    $ref: /schemas/types.yaml#definitions/uint32
153    description: The fifo size of the UART.
154
155  auto-flow-control:
156    type: boolean
157    description: |
158      One way to enable automatic flow control support. The driver is
159      allowed to detect support for the capability even without this
160      property.
161
162  tx-threshold:
163    $ref: /schemas/types.yaml#definitions/uint32
164    description: |
165      Specify the TX FIFO low water indication for parts with programmable
166      TX FIFO thresholds.
167
168  overrun-throttle-ms:
169    description: |
170      How long to pause uart rx when input overrun is encountered.
171
172  rts-gpios: true
173  cts-gpios: true
174  dtr-gpios: true
175  dsr-gpios: true
176  rng-gpios: true
177  dcd-gpios: true
178
179  aspeed,sirq-polarity-sense:
180    $ref: /schemas/types.yaml#/definitions/phandle-array
181    description: |
182      Phandle to aspeed,ast2500-scu compatible syscon alongside register
183      offset and bit number to identify how the SIRQ polarity should be
184      configured. One possible data source is the LPC/eSPI mode bit. Only
185      applicable to aspeed,ast2500-vuart.
186
187required:
188  - reg
189  - interrupts
190
191unevaluatedProperties: false
192
193examples:
194  - |
195    serial@80230000 {
196        compatible = "ns8250";
197        reg = <0x80230000 0x100>;
198        interrupts = <10>;
199        reg-shift = <2>;
200        clock-frequency = <48000000>;
201    };
202  - |
203    #include <dt-bindings/gpio/gpio.h>
204    serial@49042000 {
205        compatible = "andestech,uart16550", "ns16550a";
206        reg = <0x49042000 0x400>;
207        interrupts = <80>;
208        clock-frequency = <48000000>;
209        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
210        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
211        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
212        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
213        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
214        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
215    };
216  - |
217    #include <dt-bindings/clock/aspeed-clock.h>
218    serial@1e787000 {
219        compatible = "aspeed,ast2500-vuart";
220        reg = <0x1e787000 0x40>;
221        reg-shift = <2>;
222        interrupts = <8>;
223        clocks = <&syscon ASPEED_CLK_APB>;
224        no-loopback-test;
225        aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
226    };
227
228...
229