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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Manu Gautam <mgautam@codeaurora.org>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - qcom,msm8996-dwc3
17          - qcom,msm8998-dwc3
18          - qcom,sc7180-dwc3
19          - qcom,sdm845-dwc3
20          - qcom,sdx55-dwc3
21          - qcom,sm8150-dwc3
22          - qcom,sm8250-dwc3
23          - qcom,sm8350-dwc3
24      - const: qcom,dwc3
25
26  reg:
27    description: Offset and length of register set for QSCRATCH wrapper
28    maxItems: 1
29
30  "#address-cells":
31    enum: [ 1, 2 ]
32
33  "#size-cells":
34    enum: [ 1, 2 ]
35
36  ranges: true
37
38  power-domains:
39    description: specifies a phandle to PM domain provider node
40    maxItems: 1
41
42  clocks:
43    description:
44      A list of phandle and clock-specifier pairs for the clocks
45      listed in clock-names.
46    items:
47      - description: System Config NOC clock.
48      - description: Master/Core clock, has to be >= 125 MHz
49          for SS operation and >= 60MHz for HS operation.
50      - description: System bus AXI clock.
51      - description: Mock utmi clock needed for ITP/SOF generation
52          in host mode. Its frequency should be 19.2MHz.
53      - description: Sleep clock, used for wakeup when
54          USB3 core goes into low power mode (U3).
55
56  clock-names:
57    items:
58      - const: cfg_noc
59      - const: core
60      - const: iface
61      - const: mock_utmi
62      - const: sleep
63
64  assigned-clocks:
65    items:
66      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
67      - description: Phandle and clock specifoer of MASTER_CLK.
68
69  assigned-clock-rates:
70    items:
71      - description: Must be 19.2MHz (19200000).
72      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
73  resets:
74    maxItems: 1
75
76  interconnects:
77    maxItems: 2
78
79  interconnect-names:
80    items:
81      - const: usb-ddr
82      - const: apps-usb
83
84  interrupts:
85    items:
86      - description: The interrupt that is asserted
87          when a wakeup event is received on USB2 bus.
88      - description: The interrupt that is asserted
89          when a wakeup event is received on USB3 bus.
90      - description: Wakeup event on DM line.
91      - description: Wakeup event on DP line.
92
93  interrupt-names:
94    items:
95      - const: hs_phy_irq
96      - const: ss_phy_irq
97      - const: dm_hs_phy_irq
98      - const: dp_hs_phy_irq
99
100  qcom,select-utmi-as-pipe-clk:
101    description:
102      If present, disable USB3 pipe_clk requirement.
103      Used when dwc3 operates without SSPHY and only
104      HS/FS/LS modes are supported.
105    type: boolean
106
107# Required child node:
108
109patternProperties:
110  "^dwc3@[0-9a-f]+$":
111    type: object
112    description:
113      A child node must exist to represent the core DWC3 IP block
114      The content of the node is defined in dwc3.txt.
115
116required:
117  - compatible
118  - reg
119  - "#address-cells"
120  - "#size-cells"
121  - ranges
122  - power-domains
123  - clocks
124  - clock-names
125  - interrupts
126  - interrupt-names
127
128additionalProperties: false
129
130examples:
131  - |
132    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
133    #include <dt-bindings/interrupt-controller/arm-gic.h>
134    #include <dt-bindings/interrupt-controller/irq.h>
135    soc {
136        #address-cells = <2>;
137        #size-cells = <2>;
138
139        usb@a6f8800 {
140            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
141            reg = <0 0x0a6f8800 0 0x400>;
142
143            #address-cells = <2>;
144            #size-cells = <2>;
145            ranges;
146            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
147                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
148                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
149                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
150                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
151            clock-names = "cfg_noc", "core", "iface", "mock_utmi",
152                      "sleep";
153
154            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
155                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
156            assigned-clock-rates = <19200000>, <150000000>;
157
158            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
159                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
160                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
161                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
162            interrupt-names = "hs_phy_irq", "ss_phy_irq",
163                          "dm_hs_phy_irq", "dp_hs_phy_irq";
164
165            power-domains = <&gcc USB30_PRIM_GDSC>;
166
167            resets = <&gcc GCC_USB30_PRIM_BCR>;
168
169            dwc3@a600000 {
170                compatible = "snps,dwc3";
171                reg = <0 0x0a600000 0 0xcd00>;
172                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
173                iommus = <&apps_smmu 0x740 0>;
174                snps,dis_u2_susphy_quirk;
175                snps,dis_enblslpm_quirk;
176                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
177                phy-names = "usb2-phy", "usb3-phy";
178            };
179        };
180    };
181