1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASSEMBLY__ 9 #error "Only include this from assembly code" 10 #endif 11 12 #ifndef __ASM_ASSEMBLER_H 13 #define __ASM_ASSEMBLER_H 14 15 #include <asm-generic/export.h> 16 17 #include <asm/asm-offsets.h> 18 #include <asm/asm-bug.h> 19 #include <asm/alternative.h> 20 #include <asm/cpufeature.h> 21 #include <asm/cputype.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/page.h> 24 #include <asm/pgtable-hwdef.h> 25 #include <asm/ptrace.h> 26 #include <asm/thread_info.h> 27 28 /* 29 * Provide a wxN alias for each wN register so what we can paste a xN 30 * reference after a 'w' to obtain the 32-bit version. 31 */ 32 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 33 wx\n .req w\n 34 .endr 35 36 .macro save_and_disable_daif, flags 37 mrs \flags, daif 38 msr daifset, #0xf 39 .endm 40 41 .macro disable_daif 42 msr daifset, #0xf 43 .endm 44 45 .macro enable_daif 46 msr daifclr, #0xf 47 .endm 48 49 .macro restore_daif, flags:req 50 msr daif, \flags 51 .endm 52 53 /* IRQ is the lowest priority flag, unconditionally unmask the rest. */ 54 .macro enable_da_f 55 msr daifclr, #(8 | 4 | 1) 56 .endm 57 58 /* 59 * Save/restore interrupts. 60 */ 61 .macro save_and_disable_irq, flags 62 mrs \flags, daif 63 msr daifset, #2 64 .endm 65 66 .macro restore_irq, flags 67 msr daif, \flags 68 .endm 69 70 .macro enable_dbg 71 msr daifclr, #8 72 .endm 73 74 .macro disable_step_tsk, flgs, tmp 75 tbz \flgs, #TIF_SINGLESTEP, 9990f 76 mrs \tmp, mdscr_el1 77 bic \tmp, \tmp, #DBG_MDSCR_SS 78 msr mdscr_el1, \tmp 79 isb // Synchronise with enable_dbg 80 9990: 81 .endm 82 83 /* call with daif masked */ 84 .macro enable_step_tsk, flgs, tmp 85 tbz \flgs, #TIF_SINGLESTEP, 9990f 86 mrs \tmp, mdscr_el1 87 orr \tmp, \tmp, #DBG_MDSCR_SS 88 msr mdscr_el1, \tmp 89 9990: 90 .endm 91 92 /* 93 * RAS Error Synchronization barrier 94 */ 95 .macro esb 96 #ifdef CONFIG_ARM64_RAS_EXTN 97 hint #16 98 #else 99 nop 100 #endif 101 .endm 102 103 /* 104 * Value prediction barrier 105 */ 106 .macro csdb 107 hint #20 108 .endm 109 110 /* 111 * Clear Branch History instruction 112 */ 113 .macro clearbhb 114 hint #22 115 .endm 116 117 /* 118 * Speculation barrier 119 */ 120 .macro sb 121 alternative_if_not ARM64_HAS_SB 122 dsb nsh 123 isb 124 alternative_else 125 SB_BARRIER_INSN 126 nop 127 alternative_endif 128 .endm 129 130 /* 131 * NOP sequence 132 */ 133 .macro nops, num 134 .rept \num 135 nop 136 .endr 137 .endm 138 139 /* 140 * Create an exception table entry for `insn`, which will branch to `fixup` 141 * when an unhandled fault is taken. 142 */ 143 .macro _asm_extable, insn, fixup 144 .pushsection __ex_table, "a" 145 .align 3 146 .long (\insn - .), (\fixup - .) 147 .popsection 148 .endm 149 150 /* 151 * Create an exception table entry for `insn` if `fixup` is provided. Otherwise 152 * do nothing. 153 */ 154 .macro _cond_extable, insn, fixup 155 .ifnc \fixup, 156 _asm_extable \insn, \fixup 157 .endif 158 .endm 159 160 161 #define USER(l, x...) \ 162 9999: x; \ 163 _asm_extable 9999b, l 164 165 /* 166 * Register aliases. 167 */ 168 lr .req x30 // link register 169 170 /* 171 * Vector entry 172 */ 173 .macro ventry label 174 .align 7 175 b \label 176 .endm 177 178 /* 179 * Select code when configured for BE. 180 */ 181 #ifdef CONFIG_CPU_BIG_ENDIAN 182 #define CPU_BE(code...) code 183 #else 184 #define CPU_BE(code...) 185 #endif 186 187 /* 188 * Select code when configured for LE. 189 */ 190 #ifdef CONFIG_CPU_BIG_ENDIAN 191 #define CPU_LE(code...) 192 #else 193 #define CPU_LE(code...) code 194 #endif 195 196 /* 197 * Define a macro that constructs a 64-bit value by concatenating two 198 * 32-bit registers. Note that on big endian systems the order of the 199 * registers is swapped. 200 */ 201 #ifndef CONFIG_CPU_BIG_ENDIAN 202 .macro regs_to_64, rd, lbits, hbits 203 #else 204 .macro regs_to_64, rd, hbits, lbits 205 #endif 206 orr \rd, \lbits, \hbits, lsl #32 207 .endm 208 209 /* 210 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where 211 * <symbol> is within the range +/- 4 GB of the PC. 212 */ 213 /* 214 * @dst: destination register (64 bit wide) 215 * @sym: name of the symbol 216 */ 217 .macro adr_l, dst, sym 218 adrp \dst, \sym 219 add \dst, \dst, :lo12:\sym 220 .endm 221 222 /* 223 * @dst: destination register (32 or 64 bit wide) 224 * @sym: name of the symbol 225 * @tmp: optional 64-bit scratch register to be used if <dst> is a 226 * 32-bit wide register, in which case it cannot be used to hold 227 * the address 228 */ 229 .macro ldr_l, dst, sym, tmp= 230 .ifb \tmp 231 adrp \dst, \sym 232 ldr \dst, [\dst, :lo12:\sym] 233 .else 234 adrp \tmp, \sym 235 ldr \dst, [\tmp, :lo12:\sym] 236 .endif 237 .endm 238 239 /* 240 * @src: source register (32 or 64 bit wide) 241 * @sym: name of the symbol 242 * @tmp: mandatory 64-bit scratch register to calculate the address 243 * while <src> needs to be preserved. 244 */ 245 .macro str_l, src, sym, tmp 246 adrp \tmp, \sym 247 str \src, [\tmp, :lo12:\sym] 248 .endm 249 250 /* 251 * @dst: destination register 252 */ 253 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 254 .macro this_cpu_offset, dst 255 mrs \dst, tpidr_el2 256 .endm 257 #else 258 .macro this_cpu_offset, dst 259 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 260 mrs \dst, tpidr_el1 261 alternative_else 262 mrs \dst, tpidr_el2 263 alternative_endif 264 .endm 265 #endif 266 267 /* 268 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP) 269 * @sym: The name of the per-cpu variable 270 * @tmp: scratch register 271 */ 272 .macro adr_this_cpu, dst, sym, tmp 273 adrp \tmp, \sym 274 add \dst, \tmp, #:lo12:\sym 275 this_cpu_offset \tmp 276 add \dst, \dst, \tmp 277 .endm 278 279 /* 280 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id())) 281 * @sym: The name of the per-cpu variable 282 * @tmp: scratch register 283 */ 284 .macro ldr_this_cpu dst, sym, tmp 285 adr_l \dst, \sym 286 this_cpu_offset \tmp 287 ldr \dst, [\dst, \tmp] 288 .endm 289 290 /* 291 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) 292 */ 293 .macro vma_vm_mm, rd, rn 294 ldr \rd, [\rn, #VMA_VM_MM] 295 .endm 296 297 /* 298 * read_ctr - read CTR_EL0. If the system has mismatched register fields, 299 * provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val 300 */ 301 .macro read_ctr, reg 302 #ifndef __KVM_NVHE_HYPERVISOR__ 303 alternative_if_not ARM64_MISMATCHED_CACHE_TYPE 304 mrs \reg, ctr_el0 // read CTR 305 nop 306 alternative_else 307 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL 308 alternative_endif 309 #else 310 alternative_if_not ARM64_KVM_PROTECTED_MODE 311 ASM_BUG() 312 alternative_else_nop_endif 313 alternative_cb kvm_compute_final_ctr_el0 314 movz \reg, #0 315 movk \reg, #0, lsl #16 316 movk \reg, #0, lsl #32 317 movk \reg, #0, lsl #48 318 alternative_cb_end 319 #endif 320 .endm 321 322 323 /* 324 * raw_dcache_line_size - get the minimum D-cache line size on this CPU 325 * from the CTR register. 326 */ 327 .macro raw_dcache_line_size, reg, tmp 328 mrs \tmp, ctr_el0 // read CTR 329 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 330 mov \reg, #4 // bytes per word 331 lsl \reg, \reg, \tmp // actual cache line size 332 .endm 333 334 /* 335 * dcache_line_size - get the safe D-cache line size across all CPUs 336 */ 337 .macro dcache_line_size, reg, tmp 338 read_ctr \tmp 339 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 340 mov \reg, #4 // bytes per word 341 lsl \reg, \reg, \tmp // actual cache line size 342 .endm 343 344 /* 345 * raw_icache_line_size - get the minimum I-cache line size on this CPU 346 * from the CTR register. 347 */ 348 .macro raw_icache_line_size, reg, tmp 349 mrs \tmp, ctr_el0 // read CTR 350 and \tmp, \tmp, #0xf // cache line size encoding 351 mov \reg, #4 // bytes per word 352 lsl \reg, \reg, \tmp // actual cache line size 353 .endm 354 355 /* 356 * icache_line_size - get the safe I-cache line size across all CPUs 357 */ 358 .macro icache_line_size, reg, tmp 359 read_ctr \tmp 360 and \tmp, \tmp, #0xf // cache line size encoding 361 mov \reg, #4 // bytes per word 362 lsl \reg, \reg, \tmp // actual cache line size 363 .endm 364 365 /* 366 * tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map 367 */ 368 .macro tcr_set_t0sz, valreg, t0sz 369 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH 370 .endm 371 372 /* 373 * tcr_set_t1sz - update TCR.T1SZ 374 */ 375 .macro tcr_set_t1sz, valreg, t1sz 376 bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH 377 .endm 378 379 /* 380 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported 381 * ID_AA64MMFR0_EL1.PARange value 382 * 383 * tcr: register with the TCR_ELx value to be updated 384 * pos: IPS or PS bitfield position 385 * tmp{0,1}: temporary registers 386 */ 387 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1 388 mrs \tmp0, ID_AA64MMFR0_EL1 389 // Narrow PARange to fit the PS field in TCR_ELx 390 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3 391 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX 392 cmp \tmp0, \tmp1 393 csel \tmp0, \tmp1, \tmp0, hi 394 bfi \tcr, \tmp0, \pos, #3 395 .endm 396 397 .macro __dcache_op_workaround_clean_cache, op, addr 398 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE 399 dc \op, \addr 400 alternative_else 401 dc civac, \addr 402 alternative_endif 403 .endm 404 405 /* 406 * Macro to perform a data cache maintenance for the interval 407 * [start, end) 408 * 409 * op: operation passed to dc instruction 410 * domain: domain used in dsb instruciton 411 * start: starting virtual address of the region 412 * end: end virtual address of the region 413 * fixup: optional label to branch to on user fault 414 * Corrupts: start, end, tmp1, tmp2 415 */ 416 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup 417 dcache_line_size \tmp1, \tmp2 418 sub \tmp2, \tmp1, #1 419 bic \start, \start, \tmp2 420 .Ldcache_op\@: 421 .ifc \op, cvau 422 __dcache_op_workaround_clean_cache \op, \start 423 .else 424 .ifc \op, cvac 425 __dcache_op_workaround_clean_cache \op, \start 426 .else 427 .ifc \op, cvap 428 sys 3, c7, c12, 1, \start // dc cvap 429 .else 430 .ifc \op, cvadp 431 sys 3, c7, c13, 1, \start // dc cvadp 432 .else 433 dc \op, \start 434 .endif 435 .endif 436 .endif 437 .endif 438 add \start, \start, \tmp1 439 cmp \start, \end 440 b.lo .Ldcache_op\@ 441 dsb \domain 442 443 _cond_extable .Ldcache_op\@, \fixup 444 .endm 445 446 /* 447 * Macro to perform an instruction cache maintenance for the interval 448 * [start, end) 449 * 450 * start, end: virtual addresses describing the region 451 * fixup: optional label to branch to on user fault 452 * Corrupts: tmp1, tmp2 453 */ 454 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup 455 icache_line_size \tmp1, \tmp2 456 sub \tmp2, \tmp1, #1 457 bic \tmp2, \start, \tmp2 458 .Licache_op\@: 459 ic ivau, \tmp2 // invalidate I line PoU 460 add \tmp2, \tmp2, \tmp1 461 cmp \tmp2, \end 462 b.lo .Licache_op\@ 463 dsb ish 464 isb 465 466 _cond_extable .Licache_op\@, \fixup 467 .endm 468 469 /* 470 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present 471 */ 472 .macro reset_pmuserenr_el0, tmpreg 473 mrs \tmpreg, id_aa64dfr0_el1 474 sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4 475 cmp \tmpreg, #1 // Skip if no PMU present 476 b.lt 9000f 477 msr pmuserenr_el0, xzr // Disable PMU access from EL0 478 9000: 479 .endm 480 481 /* 482 * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present 483 */ 484 .macro reset_amuserenr_el0, tmpreg 485 mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1 486 ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_AMU_SHIFT, #4 487 cbz \tmpreg, .Lskip_\@ // Skip if no AMU present 488 msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0 489 .Lskip_\@: 490 .endm 491 /* 492 * copy_page - copy src to dest using temp registers t1-t8 493 */ 494 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req 495 9998: ldp \t1, \t2, [\src] 496 ldp \t3, \t4, [\src, #16] 497 ldp \t5, \t6, [\src, #32] 498 ldp \t7, \t8, [\src, #48] 499 add \src, \src, #64 500 stnp \t1, \t2, [\dest] 501 stnp \t3, \t4, [\dest, #16] 502 stnp \t5, \t6, [\dest, #32] 503 stnp \t7, \t8, [\dest, #48] 504 add \dest, \dest, #64 505 tst \src, #(PAGE_SIZE - 1) 506 b.ne 9998b 507 .endm 508 509 /* 510 * Annotate a function as being unsuitable for kprobes. 511 */ 512 #ifdef CONFIG_KPROBES 513 #define NOKPROBE(x) \ 514 .pushsection "_kprobe_blacklist", "aw"; \ 515 .quad x; \ 516 .popsection; 517 #else 518 #define NOKPROBE(x) 519 #endif 520 521 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 522 #define EXPORT_SYMBOL_NOKASAN(name) 523 #else 524 #define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name) 525 #endif 526 527 /* 528 * Emit a 64-bit absolute little endian symbol reference in a way that 529 * ensures that it will be resolved at build time, even when building a 530 * PIE binary. This requires cooperation from the linker script, which 531 * must emit the lo32/hi32 halves individually. 532 */ 533 .macro le64sym, sym 534 .long \sym\()_lo32 535 .long \sym\()_hi32 536 .endm 537 538 /* 539 * mov_q - move an immediate constant into a 64-bit register using 540 * between 2 and 4 movz/movk instructions (depending on the 541 * magnitude and sign of the operand) 542 */ 543 .macro mov_q, reg, val 544 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff) 545 movz \reg, :abs_g1_s:\val 546 .else 547 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff) 548 movz \reg, :abs_g2_s:\val 549 .else 550 movz \reg, :abs_g3:\val 551 movk \reg, :abs_g2_nc:\val 552 .endif 553 movk \reg, :abs_g1_nc:\val 554 .endif 555 movk \reg, :abs_g0_nc:\val 556 .endm 557 558 /* 559 * Return the current task_struct. 560 */ 561 .macro get_current_task, rd 562 mrs \rd, sp_el0 563 .endm 564 565 /* 566 * Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD. 567 * orr is used as it can cover the immediate value (and is idempotent). 568 * In future this may be nop'ed out when dealing with 52-bit kernel VAs. 569 * ttbr: Value of ttbr to set, modified. 570 */ 571 .macro offset_ttbr1, ttbr, tmp 572 #ifdef CONFIG_ARM64_VA_BITS_52 573 mrs_s \tmp, SYS_ID_AA64MMFR2_EL1 574 and \tmp, \tmp, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 575 cbnz \tmp, .Lskipoffs_\@ 576 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET 577 .Lskipoffs_\@ : 578 #endif 579 .endm 580 581 /* 582 * Perform the reverse of offset_ttbr1. 583 * bic is used as it can cover the immediate value and, in future, won't need 584 * to be nop'ed out when dealing with 52-bit kernel VAs. 585 */ 586 .macro restore_ttbr1, ttbr 587 #ifdef CONFIG_ARM64_VA_BITS_52 588 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET 589 #endif 590 .endm 591 592 /* 593 * Arrange a physical address in a TTBR register, taking care of 52-bit 594 * addresses. 595 * 596 * phys: physical address, preserved 597 * ttbr: returns the TTBR value 598 */ 599 .macro phys_to_ttbr, ttbr, phys 600 #ifdef CONFIG_ARM64_PA_BITS_52 601 orr \ttbr, \phys, \phys, lsr #46 602 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 603 #else 604 mov \ttbr, \phys 605 #endif 606 .endm 607 608 .macro phys_to_pte, pte, phys 609 #ifdef CONFIG_ARM64_PA_BITS_52 610 /* 611 * We assume \phys is 64K aligned and this is guaranteed by only 612 * supporting this configuration with 64K pages. 613 */ 614 orr \pte, \phys, \phys, lsr #36 615 and \pte, \pte, #PTE_ADDR_MASK 616 #else 617 mov \pte, \phys 618 #endif 619 .endm 620 621 .macro pte_to_phys, phys, pte 622 #ifdef CONFIG_ARM64_PA_BITS_52 623 ubfiz \phys, \pte, #(48 - 16 - 12), #16 624 bfxil \phys, \pte, #16, #32 625 lsl \phys, \phys, #16 626 #else 627 and \phys, \pte, #PTE_ADDR_MASK 628 #endif 629 .endm 630 631 /* 632 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU. 633 */ 634 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2 635 #ifdef CONFIG_FUJITSU_ERRATUM_010001 636 mrs \tmp1, midr_el1 637 638 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK 639 and \tmp1, \tmp1, \tmp2 640 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001 641 cmp \tmp1, \tmp2 642 b.ne 10f 643 644 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001 645 bic \tcr, \tcr, \tmp2 646 10: 647 #endif /* CONFIG_FUJITSU_ERRATUM_010001 */ 648 .endm 649 650 /** 651 * Errata workaround prior to disable MMU. Insert an ISB immediately prior 652 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0. 653 */ 654 .macro pre_disable_mmu_workaround 655 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041 656 isb 657 #endif 658 .endm 659 660 /* 661 * frame_push - Push @regcount callee saved registers to the stack, 662 * starting at x19, as well as x29/x30, and set x29 to 663 * the new value of sp. Add @extra bytes of stack space 664 * for locals. 665 */ 666 .macro frame_push, regcount:req, extra 667 __frame st, \regcount, \extra 668 .endm 669 670 /* 671 * frame_pop - Pop the callee saved registers from the stack that were 672 * pushed in the most recent call to frame_push, as well 673 * as x29/x30 and any extra stack space that may have been 674 * allocated. 675 */ 676 .macro frame_pop 677 __frame ld 678 .endm 679 680 .macro __frame_regs, reg1, reg2, op, num 681 .if .Lframe_regcount == \num 682 \op\()r \reg1, [sp, #(\num + 1) * 8] 683 .elseif .Lframe_regcount > \num 684 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8] 685 .endif 686 .endm 687 688 .macro __frame, op, regcount, extra=0 689 .ifc \op, st 690 .if (\regcount) < 0 || (\regcount) > 10 691 .error "regcount should be in the range [0 ... 10]" 692 .endif 693 .if ((\extra) % 16) != 0 694 .error "extra should be a multiple of 16 bytes" 695 .endif 696 .ifdef .Lframe_regcount 697 .if .Lframe_regcount != -1 698 .error "frame_push/frame_pop may not be nested" 699 .endif 700 .endif 701 .set .Lframe_regcount, \regcount 702 .set .Lframe_extra, \extra 703 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16 704 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]! 705 mov x29, sp 706 .endif 707 708 __frame_regs x19, x20, \op, 1 709 __frame_regs x21, x22, \op, 3 710 __frame_regs x23, x24, \op, 5 711 __frame_regs x25, x26, \op, 7 712 __frame_regs x27, x28, \op, 9 713 714 .ifc \op, ld 715 .if .Lframe_regcount == -1 716 .error "frame_push/frame_pop may not be nested" 717 .endif 718 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra 719 .set .Lframe_regcount, -1 720 .endif 721 .endm 722 723 /* 724 * Set SCTLR_ELx to the @reg value, and invalidate the local icache 725 * in the process. This is called when setting the MMU on. 726 */ 727 .macro set_sctlr, sreg, reg 728 msr \sreg, \reg 729 isb 730 /* 731 * Invalidate the local I-cache so that any instructions fetched 732 * speculatively from the PoC are discarded, since they may have 733 * been dynamically patched at the PoU. 734 */ 735 ic iallu 736 dsb nsh 737 isb 738 .endm 739 740 .macro set_sctlr_el1, reg 741 set_sctlr sctlr_el1, \reg 742 .endm 743 744 .macro set_sctlr_el2, reg 745 set_sctlr sctlr_el2, \reg 746 .endm 747 748 /* 749 * Check whether preempt/bh-disabled asm code should yield as soon as 750 * it is able. This is the case if we are currently running in task 751 * context, and either a softirq is pending, or the TIF_NEED_RESCHED 752 * flag is set and re-enabling preemption a single time would result in 753 * a preempt count of zero. (Note that the TIF_NEED_RESCHED flag is 754 * stored negated in the top word of the thread_info::preempt_count 755 * field) 756 */ 757 .macro cond_yield, lbl:req, tmp:req, tmp2:req 758 get_current_task \tmp 759 ldr \tmp, [\tmp, #TSK_TI_PREEMPT] 760 /* 761 * If we are serving a softirq, there is no point in yielding: the 762 * softirq will not be preempted no matter what we do, so we should 763 * run to completion as quickly as we can. 764 */ 765 tbnz \tmp, #SOFTIRQ_SHIFT, .Lnoyield_\@ 766 #ifdef CONFIG_PREEMPTION 767 sub \tmp, \tmp, #PREEMPT_DISABLE_OFFSET 768 cbz \tmp, \lbl 769 #endif 770 adr_l \tmp, irq_stat + IRQ_CPUSTAT_SOFTIRQ_PENDING 771 this_cpu_offset \tmp2 772 ldr w\tmp, [\tmp, \tmp2] 773 cbnz w\tmp, \lbl // yield on pending softirq in task context 774 .Lnoyield_\@: 775 .endm 776 777 /* 778 * This macro emits a program property note section identifying 779 * architecture features which require special handling, mainly for 780 * use in assembly files included in the VDSO. 781 */ 782 783 #define NT_GNU_PROPERTY_TYPE_0 5 784 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 785 786 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0) 787 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) 788 789 #ifdef CONFIG_ARM64_BTI_KERNEL 790 #define GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT \ 791 ((GNU_PROPERTY_AARCH64_FEATURE_1_BTI | \ 792 GNU_PROPERTY_AARCH64_FEATURE_1_PAC)) 793 #endif 794 795 #ifdef GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT 796 .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT 797 .pushsection .note.gnu.property, "a" 798 .align 3 799 .long 2f - 1f 800 .long 6f - 3f 801 .long NT_GNU_PROPERTY_TYPE_0 802 1: .string "GNU" 803 2: 804 .align 3 805 3: .long GNU_PROPERTY_AARCH64_FEATURE_1_AND 806 .long 5f - 4f 807 4: 808 /* 809 * This is described with an array of char in the Linux API 810 * spec but the text and all other usage (including binutils, 811 * clang and GCC) treat this as a 32 bit value so no swizzling 812 * is required for big endian. 813 */ 814 .long \feat 815 5: 816 .align 3 817 6: 818 .popsection 819 .endm 820 821 #else 822 .macro emit_aarch64_feature_1_and, feat=0 823 .endm 824 825 #endif /* GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT */ 826 827 .macro __mitigate_spectre_bhb_loop tmp 828 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 829 alternative_cb spectre_bhb_patch_loop_iter 830 mov \tmp, #32 // Patched to correct the immediate 831 alternative_cb_end 832 .Lspectre_bhb_loop\@: 833 b . + 4 834 subs \tmp, \tmp, #1 835 b.ne .Lspectre_bhb_loop\@ 836 sb 837 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 838 .endm 839 840 .macro mitigate_spectre_bhb_loop tmp 841 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 842 alternative_cb spectre_bhb_patch_loop_mitigation_enable 843 b .L_spectre_bhb_loop_done\@ // Patched to NOP 844 alternative_cb_end 845 __mitigate_spectre_bhb_loop \tmp 846 .L_spectre_bhb_loop_done\@: 847 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 848 .endm 849 850 /* Save/restores x0-x3 to the stack */ 851 .macro __mitigate_spectre_bhb_fw 852 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 853 stp x0, x1, [sp, #-16]! 854 stp x2, x3, [sp, #-16]! 855 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3 856 alternative_cb smccc_patch_fw_mitigation_conduit 857 nop // Patched to SMC/HVC #0 858 alternative_cb_end 859 ldp x2, x3, [sp], #16 860 ldp x0, x1, [sp], #16 861 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 862 .endm 863 864 .macro mitigate_spectre_bhb_clear_insn 865 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 866 alternative_cb spectre_bhb_patch_clearbhb 867 /* Patched to NOP when not supported */ 868 clearbhb 869 isb 870 alternative_cb_end 871 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 872 .endm 873 #endif /* __ASM_ASSEMBLER_H */ 874