1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Based on arch/arm/include/asm/processor.h
4 *
5 * Copyright (C) 1995-1999 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8 #ifndef __ASM_PROCESSOR_H
9 #define __ASM_PROCESSOR_H
10
11 #define KERNEL_DS UL(-1)
12 #define USER_DS ((UL(1) << VA_BITS) - 1)
13
14 /*
15 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
16 * no point in shifting all network buffers by 2 bytes just to make some IP
17 * header fields appear aligned in memory, potentially sacrificing some DMA
18 * performance on some platforms.
19 */
20 #define NET_IP_ALIGN 0
21
22 #define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
23 #define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
24
25 #define MTE_CTRL_TCF_SYNC (1UL << 16)
26 #define MTE_CTRL_TCF_ASYNC (1UL << 17)
27 #define MTE_CTRL_TCF_ASYMM (1UL << 18)
28
29 #ifndef __ASSEMBLY__
30
31 #include <linux/build_bug.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/stddef.h>
35 #include <linux/string.h>
36 #include <linux/thread_info.h>
37 #include <linux/android_vendor.h>
38
39 #include <vdso/processor.h>
40
41 #include <asm/alternative.h>
42 #include <asm/cpufeature.h>
43 #include <asm/hw_breakpoint.h>
44 #include <asm/kasan.h>
45 #include <asm/lse.h>
46 #include <asm/pgtable-hwdef.h>
47 #include <asm/pointer_auth.h>
48 #include <asm/ptrace.h>
49 #include <asm/spectre.h>
50 #include <asm/types.h>
51
52 /*
53 * TASK_SIZE - the maximum size of a user space task.
54 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
55 */
56
57 #define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
58 #define TASK_SIZE_64 (UL(1) << vabits_actual)
59
60 #ifdef CONFIG_COMPAT
61 #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
62 /*
63 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
64 * by the compat vectors page.
65 */
66 #define TASK_SIZE_32 UL(0x100000000)
67 #else
68 #define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
69 #endif /* CONFIG_ARM64_64K_PAGES */
70 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
71 TASK_SIZE_32 : TASK_SIZE_64)
72 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
73 TASK_SIZE_32 : TASK_SIZE_64)
74 #define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
75 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
76 #else
77 #define TASK_SIZE TASK_SIZE_64
78 #define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
79 #endif /* CONFIG_COMPAT */
80
81 #ifdef CONFIG_ARM64_FORCE_52BIT
82 #define STACK_TOP_MAX TASK_SIZE_64
83 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
84 #else
85 #define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
86 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
87 #endif /* CONFIG_ARM64_FORCE_52BIT */
88
89 #ifdef CONFIG_COMPAT
90 #define AARCH32_VECTORS_BASE 0xffff0000
91 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
92 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
93 #else
94 #define STACK_TOP STACK_TOP_MAX
95 #endif /* CONFIG_COMPAT */
96
97 #ifndef CONFIG_ARM64_FORCE_52BIT
98 #define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\
99 DEFAULT_MAP_WINDOW)
100
101 #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
102 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
103 base)
104 #endif /* CONFIG_ARM64_FORCE_52BIT */
105
106 extern phys_addr_t arm64_dma_phys_limit;
107 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
108
109 struct debug_info {
110 #ifdef CONFIG_HAVE_HW_BREAKPOINT
111 /* Have we suspended stepping by a debugger? */
112 int suspended_step;
113 /* Allow breakpoints and watchpoints to be disabled for this thread. */
114 int bps_disabled;
115 int wps_disabled;
116 /* Hardware breakpoints pinned to this task. */
117 struct perf_event *hbp_break[ARM_MAX_BRP];
118 struct perf_event *hbp_watch[ARM_MAX_WRP];
119 #endif
120 };
121
122 struct cpu_context {
123 unsigned long x19;
124 unsigned long x20;
125 unsigned long x21;
126 unsigned long x22;
127 unsigned long x23;
128 unsigned long x24;
129 unsigned long x25;
130 unsigned long x26;
131 unsigned long x27;
132 unsigned long x28;
133 unsigned long fp;
134 unsigned long sp;
135 unsigned long pc;
136 };
137
138 struct thread_struct {
139 struct cpu_context cpu_context; /* cpu context */
140
141 /*
142 * Whitelisted fields for hardened usercopy:
143 * Maintainers must ensure manually that this contains no
144 * implicit padding.
145 */
146 struct {
147 unsigned long tp_value; /* TLS register */
148 unsigned long tp2_value;
149 struct user_fpsimd_state fpsimd_state;
150 } uw;
151
152 /*
153 * Unused now that commit 74555f39924d ("ANDROID: vendor_hooks: FPSIMD
154 * save/restore by using vendor_hooks") is reverted, but remains to
155 * preserve the ABI in the android13-5.10 branch.
156 */
157 ANDROID_VENDOR_DATA(1);
158
159 unsigned int fpsimd_cpu;
160 void *sve_state; /* SVE registers, if any */
161 unsigned int sve_vl; /* SVE vector length */
162 unsigned int sve_vl_onexec; /* SVE vl after next exec */
163 unsigned long fault_address; /* fault info */
164 unsigned long fault_code; /* ESR_EL1 value */
165 struct debug_info debug; /* debugging */
166 #ifdef CONFIG_ARM64_PTR_AUTH
167 struct ptrauth_keys_user keys_user;
168 struct ptrauth_keys_kernel keys_kernel;
169 #endif
170 #ifdef CONFIG_ARM64_MTE
171 u64 mte_ctrl;
172 #endif
173 u64 sctlr_user;
174 };
175
176 #define SCTLR_USER_MASK \
177 (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \
178 SCTLR_EL1_TCF0_MASK)
179
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)180 static inline void arch_thread_struct_whitelist(unsigned long *offset,
181 unsigned long *size)
182 {
183 /* Verify that there is no padding among the whitelisted fields: */
184 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
185 sizeof_field(struct thread_struct, uw.tp_value) +
186 sizeof_field(struct thread_struct, uw.tp2_value) +
187 sizeof_field(struct thread_struct, uw.fpsimd_state));
188
189 *offset = offsetof(struct thread_struct, uw);
190 *size = sizeof_field(struct thread_struct, uw);
191 }
192
193 #ifdef CONFIG_COMPAT
194 #define task_user_tls(t) \
195 ({ \
196 unsigned long *__tls; \
197 if (is_compat_thread(task_thread_info(t))) \
198 __tls = &(t)->thread.uw.tp2_value; \
199 else \
200 __tls = &(t)->thread.uw.tp_value; \
201 __tls; \
202 })
203 #else
204 #define task_user_tls(t) (&(t)->thread.uw.tp_value)
205 #endif
206
207 /* Sync TPIDR_EL0 back to thread_struct for current */
208 void tls_preserve_current_state(void);
209
210 #define INIT_THREAD { \
211 .fpsimd_cpu = NR_CPUS, \
212 }
213
start_thread_common(struct pt_regs * regs,unsigned long pc)214 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
215 {
216 s32 previous_syscall = regs->syscallno;
217 memset(regs, 0, sizeof(*regs));
218 regs->syscallno = previous_syscall;
219 regs->pc = pc;
220
221 if (system_uses_irq_prio_masking())
222 regs->pmr_save = GIC_PRIO_IRQON;
223 }
224
start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)225 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
226 unsigned long sp)
227 {
228 start_thread_common(regs, pc);
229 regs->pstate = PSR_MODE_EL0t;
230 spectre_v4_enable_task_mitigation(current);
231 regs->sp = sp;
232 }
233
234 #ifdef CONFIG_COMPAT
compat_start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)235 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
236 unsigned long sp)
237 {
238 start_thread_common(regs, pc);
239 regs->pstate = PSR_AA32_MODE_USR;
240 if (pc & 1)
241 regs->pstate |= PSR_AA32_T_BIT;
242
243 #ifdef __AARCH64EB__
244 regs->pstate |= PSR_AA32_E_BIT;
245 #endif
246
247 spectre_v4_enable_task_mitigation(current);
248 regs->compat_sp = sp;
249 }
250 #endif
251
is_ttbr0_addr(unsigned long addr)252 static __always_inline bool is_ttbr0_addr(unsigned long addr)
253 {
254 /* entry assembly clears tags for TTBR0 addrs */
255 return addr < TASK_SIZE;
256 }
257
is_ttbr1_addr(unsigned long addr)258 static __always_inline bool is_ttbr1_addr(unsigned long addr)
259 {
260 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
261 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
262 }
263
264 /* Forward declaration, a strange C thing */
265 struct task_struct;
266
267 /* Free all resources held by a thread. */
268 extern void release_thread(struct task_struct *);
269
270 unsigned long get_wchan(struct task_struct *p);
271
272 void update_sctlr_el1(u64 sctlr);
273
274 /* Thread switching */
275 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
276 struct task_struct *next);
277
278 #define task_pt_regs(p) \
279 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
280
281 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
282 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
283
284 /*
285 * Prefetching support
286 */
287 #define ARCH_HAS_PREFETCH
prefetch(const void * ptr)288 static inline void prefetch(const void *ptr)
289 {
290 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
291 }
292
293 #define ARCH_HAS_PREFETCHW
prefetchw(const void * ptr)294 static inline void prefetchw(const void *ptr)
295 {
296 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
297 }
298
299 #define ARCH_HAS_SPINLOCK_PREFETCH
spin_lock_prefetch(const void * ptr)300 static inline void spin_lock_prefetch(const void *ptr)
301 {
302 asm volatile(ARM64_LSE_ATOMIC_INSN(
303 "prfm pstl1strm, %a0",
304 "nop") : : "p" (ptr));
305 }
306
307 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
308 extern void __init minsigstksz_setup(void);
309
310 /*
311 * Not at the top of the file due to a direct #include cycle between
312 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
313 * ensures that contents of processor.h are visible to fpsimd.h even if
314 * processor.h is included first.
315 *
316 * These prctl helpers are the only things in this file that require
317 * fpsimd.h. The core code expects them to be in this header.
318 */
319 #include <asm/fpsimd.h>
320
321 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
322 #define SVE_SET_VL(arg) sve_set_current_vl(arg)
323 #define SVE_GET_VL() sve_get_current_vl()
324
325 /* PR_PAC_RESET_KEYS prctl */
326 #define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
327
328 /* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */
329 #define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \
330 ptrauth_set_enabled_keys(tsk, keys, enabled)
331 #define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
332
333 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
334 /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
335 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
336 long get_tagged_addr_ctrl(struct task_struct *task);
337 #define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg)
338 #define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
339 #endif
340
341 /*
342 * For CONFIG_GCC_PLUGIN_STACKLEAK
343 *
344 * These need to be macros because otherwise we get stuck in a nightmare
345 * of header definitions for the use of task_stack_page.
346 */
347
348 #define current_top_of_stack() \
349 ({ \
350 struct stack_info _info; \
351 BUG_ON(!on_accessible_stack(current, current_stack_pointer, 1, &_info)); \
352 _info.high; \
353 })
354 #define on_thread_stack() (on_task_stack(current, current_stack_pointer, 1, NULL))
355
356 #endif /* __ASSEMBLY__ */
357 #endif /* __ASM_PROCESSOR_H */
358