1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #include <hyp/switch.h>
8 #include <hyp/sysreg-sr.h>
9
10 #include <linux/arm-smccc.h>
11 #include <linux/kvm_host.h>
12 #include <linux/types.h>
13 #include <linux/jump_label.h>
14 #include <uapi/linux/psci.h>
15
16 #include <kvm/arm_psci.h>
17
18 #include <asm/barrier.h>
19 #include <asm/cpufeature.h>
20 #include <asm/kprobes.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/kvm_hyp.h>
24 #include <asm/kvm_mmu.h>
25 #include <asm/fpsimd.h>
26 #include <asm/debug-monitors.h>
27 #include <asm/processor.h>
28
29 #include <nvhe/mem_protect.h>
30 #include <nvhe/pkvm.h>
31
32 /* Non-VHE specific context */
33 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
34 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
35 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
36
__activate_traps(struct kvm_vcpu * vcpu)37 static void __activate_traps(struct kvm_vcpu *vcpu)
38 {
39 u64 val;
40
41 ___activate_traps(vcpu);
42 __activate_traps_common(vcpu);
43
44 val = vcpu->arch.cptr_el2;
45 val |= CPTR_EL2_TTA | CPTR_EL2_TAM;
46 if (!update_fp_enabled(vcpu)) {
47 val |= CPTR_EL2_TFP | CPTR_EL2_TZ;
48 __activate_traps_fpsimd32(vcpu);
49 }
50
51 write_sysreg(val, cptr_el2);
52 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2);
53
54 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
55 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
56
57 isb();
58 /*
59 * At this stage, and thanks to the above isb(), S2 is
60 * configured and enabled. We can now restore the guest's S1
61 * configuration: SCTLR, and only then TCR.
62 */
63 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
64 isb();
65 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
66 }
67 }
68
__deactivate_traps(struct kvm_vcpu * vcpu)69 static void __deactivate_traps(struct kvm_vcpu *vcpu)
70 {
71 extern char __kvm_hyp_host_vector[];
72 u64 cptr;
73
74 ___deactivate_traps(vcpu);
75
76 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
77 u64 val;
78
79 /*
80 * Set the TCR and SCTLR registers in the exact opposite
81 * sequence as __activate_traps (first prevent walks,
82 * then force the MMU on). A generous sprinkling of isb()
83 * ensure that things happen in this exact order.
84 */
85 val = read_sysreg_el1(SYS_TCR);
86 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR);
87 isb();
88 val = read_sysreg_el1(SYS_SCTLR);
89 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR);
90 isb();
91 }
92
93 __deactivate_traps_common(vcpu);
94
95 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2);
96
97 cptr = CPTR_EL2_DEFAULT;
98 if (vcpu_has_sve(vcpu) && (vcpu->arch.flags & KVM_ARM64_FP_ENABLED))
99 cptr |= CPTR_EL2_TZ;
100
101 write_sysreg(cptr, cptr_el2);
102 write_sysreg(__kvm_hyp_host_vector, vbar_el2);
103 }
104
105 /* Save VGICv3 state on non-VHE systems */
__hyp_vgic_save_state(struct kvm_vcpu * vcpu)106 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
107 {
108 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
109 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3);
110 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
111 }
112 }
113
114 /* Restore VGICv3 state on non_VEH systems */
__hyp_vgic_restore_state(struct kvm_vcpu * vcpu)115 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
116 {
117 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
118 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
119 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3);
120 }
121 }
122
123 /*
124 * Disable host events, enable guest events
125 */
__pmu_switch_to_guest(struct kvm_cpu_context * host_ctxt)126 static bool __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
127 {
128 struct kvm_host_data *host;
129 struct kvm_pmu_events *pmu;
130
131 host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
132 pmu = &host->pmu_events;
133
134 if (pmu->events_host)
135 write_sysreg(pmu->events_host, pmcntenclr_el0);
136
137 if (pmu->events_guest)
138 write_sysreg(pmu->events_guest, pmcntenset_el0);
139
140 return (pmu->events_host || pmu->events_guest);
141 }
142
143 /*
144 * Disable guest events, enable host events
145 */
__pmu_switch_to_host(struct kvm_cpu_context * host_ctxt)146 static void __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
147 {
148 struct kvm_host_data *host;
149 struct kvm_pmu_events *pmu;
150
151 host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
152 pmu = &host->pmu_events;
153
154 if (pmu->events_guest)
155 write_sysreg(pmu->events_guest, pmcntenclr_el0);
156
157 if (pmu->events_host)
158 write_sysreg(pmu->events_host, pmcntenset_el0);
159 }
160
161 /*
162 * Handler for protected VM MSR, MRS or System instruction execution in AArch64.
163 *
164 * Returns true if the hypervisor has handled the exit, and control should go
165 * back to the guest, or false if it hasn't.
166 */
kvm_handle_pvm_sys64(struct kvm_vcpu * vcpu,u64 * exit_code)167 static bool kvm_handle_pvm_sys64(struct kvm_vcpu *vcpu, u64 *exit_code)
168 {
169 /*
170 * Make sure we handle the exit for workarounds and ptrauth
171 * before the pKVM handling, as the latter could decide to
172 * UNDEF.
173 */
174 return (kvm_hyp_handle_sysreg(vcpu, exit_code) ||
175 kvm_handle_pvm_sysreg(vcpu, exit_code));
176 }
177
178 /*
179 * Handler for protected floating-point and Advanced SIMD accesses.
180 *
181 * Returns true if the hypervisor has handled the exit, and control should go
182 * back to the guest, or false if it hasn't.
183 */
kvm_handle_pvm_fpsimd(struct kvm_vcpu * vcpu,u64 * exit_code)184 static bool kvm_handle_pvm_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
185 {
186 /* Linux guests assume support for floating-point and Advanced SIMD. */
187 BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_FP),
188 PVM_ID_AA64PFR0_ALLOW));
189 BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_ASIMD),
190 PVM_ID_AA64PFR0_ALLOW));
191
192 return kvm_hyp_handle_fpsimd(vcpu, exit_code);
193 }
194
195 static const exit_handler_fn hyp_exit_handlers[] = {
196 [0 ... ESR_ELx_EC_MAX] = NULL,
197 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
198 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg,
199 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
200 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
201 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
202 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
203 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low,
204 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth,
205 };
206
207 static const exit_handler_fn pvm_exit_handlers[] = {
208 [0 ... ESR_ELx_EC_MAX] = NULL,
209 [ESR_ELx_EC_HVC64] = kvm_handle_pvm_hvc64,
210 [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64,
211 [ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted,
212 [ESR_ELx_EC_FP_ASIMD] = kvm_handle_pvm_fpsimd,
213 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
214 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
215 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low,
216 [ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth,
217 };
218
kvm_get_exit_handler_array(struct kvm_vcpu * vcpu)219 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu)
220 {
221 if (unlikely(vcpu_is_protected(vcpu)))
222 return pvm_exit_handlers;
223
224 return hyp_exit_handlers;
225 }
226
227 /*
228 * Some guests (e.g., protected VMs) are not be allowed to run in AArch32.
229 * The ARMv8 architecture does not give the hypervisor a mechanism to prevent a
230 * guest from dropping to AArch32 EL0 if implemented by the CPU. If the
231 * hypervisor spots a guest in such a state ensure it is handled, and don't
232 * trust the host to spot or fix it. The check below is based on the one in
233 * kvm_arch_vcpu_ioctl_run().
234 *
235 * Returns false if the guest ran in AArch32 when it shouldn't have, and
236 * thus should exit to the host, or true if a the guest run loop can continue.
237 */
early_exit_filter(struct kvm_vcpu * vcpu,u64 * exit_code)238 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code)
239 {
240 if (unlikely(vcpu_is_protected(vcpu) && vcpu_mode_is_32bit(vcpu))) {
241 /*
242 * As we have caught the guest red-handed, decide that it isn't
243 * fit for purpose anymore by making the vcpu invalid. The VMM
244 * can try and fix it by re-initializing the vcpu with
245 * KVM_ARM_VCPU_INIT, however, this is likely not possible for
246 * protected VMs.
247 */
248 vcpu->arch.target = -1;
249 *exit_code &= BIT(ARM_EXIT_WITH_SERROR_BIT);
250 *exit_code |= ARM_EXCEPTION_IL;
251 }
252 }
253
254 /* Switch to the guest for legacy non-VHE systems */
__kvm_vcpu_run(struct kvm_vcpu * vcpu)255 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
256 {
257 struct kvm_cpu_context *host_ctxt;
258 struct kvm_cpu_context *guest_ctxt;
259 struct kvm_s2_mmu *mmu;
260 bool pmu_switch_needed;
261 u64 exit_code;
262
263 /*
264 * Having IRQs masked via PMR when entering the guest means the GIC
265 * will not signal the CPU of interrupts of lower priority, and the
266 * only way to get out will be via guest exceptions.
267 * Naturally, we want to avoid this.
268 */
269 if (system_uses_irq_prio_masking()) {
270 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
271 pmr_sync();
272 }
273
274 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
275 host_ctxt->__hyp_running_vcpu = vcpu;
276 guest_ctxt = &vcpu->arch.ctxt;
277
278 pmu_switch_needed = __pmu_switch_to_guest(host_ctxt);
279
280 __sysreg_save_state_nvhe(host_ctxt);
281 /*
282 * We must flush and disable the SPE buffer for nVHE, as
283 * the translation regime(EL1&0) is going to be loaded with
284 * that of the guest. And we must do this before we change the
285 * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and
286 * before we load guest Stage1.
287 */
288 __debug_save_host_buffers_nvhe(vcpu);
289
290 __kvm_adjust_pc(vcpu);
291
292 /*
293 * We must restore the 32-bit state before the sysregs, thanks
294 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
295 *
296 * Also, and in order to be able to deal with erratum #1319537 (A57)
297 * and #1319367 (A72), we must ensure that all VM-related sysreg are
298 * restored before we enable S2 translation.
299 */
300 __sysreg32_restore_state(vcpu);
301 __sysreg_restore_state_nvhe(guest_ctxt);
302
303 mmu = kern_hyp_va(vcpu->arch.hw_mmu);
304 __load_stage2(mmu, kern_hyp_va(mmu->arch));
305 __activate_traps(vcpu);
306
307 __hyp_vgic_restore_state(vcpu);
308 __timer_enable_traps(vcpu);
309
310 __debug_switch_to_guest(vcpu);
311
312 do {
313 /* Jump in the fire! */
314 exit_code = __guest_enter(vcpu);
315
316 /* And we're baaack! */
317 } while (fixup_guest_exit(vcpu, &exit_code));
318
319 __sysreg_save_state_nvhe(guest_ctxt);
320 __sysreg32_save_state(vcpu);
321 __timer_disable_traps(vcpu);
322 __hyp_vgic_save_state(vcpu);
323
324 __deactivate_traps(vcpu);
325 __load_host_stage2();
326
327 __sysreg_restore_state_nvhe(host_ctxt);
328
329 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
330 __fpsimd_save_fpexc32(vcpu);
331
332 __debug_switch_to_host(vcpu);
333 /*
334 * This must come after restoring the host sysregs, since a non-VHE
335 * system may enable SPE here and make use of the TTBRs.
336 */
337 __debug_restore_host_buffers_nvhe(vcpu);
338
339 if (pmu_switch_needed)
340 __pmu_switch_to_host(host_ctxt);
341
342 /* Returning to host will clear PSR.I, remask PMR if needed */
343 if (system_uses_irq_prio_masking())
344 gic_write_pmr(GIC_PRIO_IRQOFF);
345
346 host_ctxt->__hyp_running_vcpu = NULL;
347
348 return exit_code;
349 }
350
hyp_panic(void)351 void __noreturn hyp_panic(void)
352 {
353 u64 spsr = read_sysreg_el2(SYS_SPSR);
354 u64 elr = read_sysreg_el2(SYS_ELR);
355 u64 par = read_sysreg_par();
356 struct kvm_cpu_context *host_ctxt;
357 struct kvm_vcpu *vcpu;
358
359 host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
360 vcpu = host_ctxt->__hyp_running_vcpu;
361
362 if (vcpu) {
363 __timer_disable_traps(vcpu);
364 __deactivate_traps(vcpu);
365 __load_host_stage2();
366 __sysreg_restore_state_nvhe(host_ctxt);
367 }
368
369 __hyp_do_panic(host_ctxt, spsr, elr, par);
370 unreachable();
371 }
372
kvm_unexpected_el2_exception(void)373 asmlinkage void kvm_unexpected_el2_exception(void)
374 {
375 __kvm_unexpected_el2_exception();
376 }
377