1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/pgtable.h>
4
5 #include <linux/string.h>
6 #include <linux/bitops.h>
7 #include <linux/smp.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/thread_info.h>
11 #include <linux/init.h>
12 #include <linux/uaccess.h>
13
14 #include <asm/cpufeature.h>
15 #include <asm/msr.h>
16 #include <asm/bugs.h>
17 #include <asm/cpu.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
21 #include <asm/elf.h>
22 #include <asm/cpu_device_id.h>
23 #include <asm/cmdline.h>
24 #include <asm/traps.h>
25 #include <asm/resctrl.h>
26 #include <asm/numa.h>
27
28 #ifdef CONFIG_X86_64
29 #include <linux/topology.h>
30 #endif
31
32 #include "cpu.h"
33
34 #ifdef CONFIG_X86_LOCAL_APIC
35 #include <asm/mpspec.h>
36 #include <asm/apic.h>
37 #endif
38
39 enum split_lock_detect_state {
40 sld_off = 0,
41 sld_warn,
42 sld_fatal,
43 };
44
45 /*
46 * Default to sld_off because most systems do not support split lock detection
47 * split_lock_setup() will switch this to sld_warn on systems that support
48 * split lock detect, unless there is a command line override.
49 */
50 static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
51 static u64 msr_test_ctrl_cache __ro_after_init;
52
53 /*
54 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
55 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it
56 * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
57 */
58 static bool cpu_model_supports_sld __ro_after_init;
59
60 /*
61 * Processors which have self-snooping capability can handle conflicting
62 * memory type across CPUs by snooping its own cache. However, there exists
63 * CPU models in which having conflicting memory types still leads to
64 * unpredictable behavior, machine check errors, or hangs. Clear this
65 * feature to prevent its use on machines with known erratas.
66 */
check_memory_type_self_snoop_errata(struct cpuinfo_x86 * c)67 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
68 {
69 switch (c->x86_model) {
70 case INTEL_FAM6_CORE_YONAH:
71 case INTEL_FAM6_CORE2_MEROM:
72 case INTEL_FAM6_CORE2_MEROM_L:
73 case INTEL_FAM6_CORE2_PENRYN:
74 case INTEL_FAM6_CORE2_DUNNINGTON:
75 case INTEL_FAM6_NEHALEM:
76 case INTEL_FAM6_NEHALEM_G:
77 case INTEL_FAM6_NEHALEM_EP:
78 case INTEL_FAM6_NEHALEM_EX:
79 case INTEL_FAM6_WESTMERE:
80 case INTEL_FAM6_WESTMERE_EP:
81 case INTEL_FAM6_SANDYBRIDGE:
82 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
83 }
84 }
85
86 static bool ring3mwait_disabled __read_mostly;
87
ring3mwait_disable(char * __unused)88 static int __init ring3mwait_disable(char *__unused)
89 {
90 ring3mwait_disabled = true;
91 return 1;
92 }
93 __setup("ring3mwait=disable", ring3mwait_disable);
94
probe_xeon_phi_r3mwait(struct cpuinfo_x86 * c)95 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
96 {
97 /*
98 * Ring 3 MONITOR/MWAIT feature cannot be detected without
99 * cpu model and family comparison.
100 */
101 if (c->x86 != 6)
102 return;
103 switch (c->x86_model) {
104 case INTEL_FAM6_XEON_PHI_KNL:
105 case INTEL_FAM6_XEON_PHI_KNM:
106 break;
107 default:
108 return;
109 }
110
111 if (ring3mwait_disabled)
112 return;
113
114 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
115 this_cpu_or(msr_misc_features_shadow,
116 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
117
118 if (c == &boot_cpu_data)
119 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
120 }
121
122 /*
123 * Early microcode releases for the Spectre v2 mitigation were broken.
124 * Information taken from;
125 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
126 * - https://kb.vmware.com/s/article/52345
127 * - Microcode revisions observed in the wild
128 * - Release note from 20180108 microcode release
129 */
130 struct sku_microcode {
131 u8 model;
132 u8 stepping;
133 u32 microcode;
134 };
135 static const struct sku_microcode spectre_bad_microcodes[] = {
136 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
137 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
138 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
139 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
140 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
141 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
142 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
143 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
144 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
145 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
146 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
147 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
148 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
149 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
150 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
151 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
152 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
153 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
154 /* Observed in the wild */
155 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
156 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
157 };
158
bad_spectre_microcode(struct cpuinfo_x86 * c)159 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
160 {
161 int i;
162
163 /*
164 * We know that the hypervisor lie to us on the microcode version so
165 * we may as well hope that it is running the correct version.
166 */
167 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
168 return false;
169
170 if (c->x86 != 6)
171 return false;
172
173 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
174 if (c->x86_model == spectre_bad_microcodes[i].model &&
175 c->x86_stepping == spectre_bad_microcodes[i].stepping)
176 return (c->microcode <= spectre_bad_microcodes[i].microcode);
177 }
178 return false;
179 }
180
181 #define MSR_IA32_TME_ACTIVATE 0x982
182
183 /* Helpers to access TME_ACTIVATE MSR */
184 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
185 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
186
187 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
188 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
189
190 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
191
192 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
193 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
194
195 /* Values for mktme_status (SW only construct) */
196 #define MKTME_ENABLED 0
197 #define MKTME_DISABLED 1
198 #define MKTME_UNINITIALIZED 2
199 static int mktme_status = MKTME_UNINITIALIZED;
200
detect_tme_early(struct cpuinfo_x86 * c)201 static void detect_tme_early(struct cpuinfo_x86 *c)
202 {
203 u64 tme_activate, tme_policy, tme_crypto_algs;
204 int keyid_bits = 0, nr_keyids = 0;
205 static u64 tme_activate_cpu0 = 0;
206
207 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
208
209 if (mktme_status != MKTME_UNINITIALIZED) {
210 if (tme_activate != tme_activate_cpu0) {
211 /* Broken BIOS? */
212 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
213 pr_err_once("x86/tme: MKTME is not usable\n");
214 mktme_status = MKTME_DISABLED;
215
216 /* Proceed. We may need to exclude bits from x86_phys_bits. */
217 }
218 } else {
219 tme_activate_cpu0 = tme_activate;
220 }
221
222 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
223 pr_info_once("x86/tme: not enabled by BIOS\n");
224 mktme_status = MKTME_DISABLED;
225 return;
226 }
227
228 if (mktme_status != MKTME_UNINITIALIZED)
229 goto detect_keyid_bits;
230
231 pr_info("x86/tme: enabled by BIOS\n");
232
233 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
234 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
235 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
236
237 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
238 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
239 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
240 tme_crypto_algs);
241 mktme_status = MKTME_DISABLED;
242 }
243 detect_keyid_bits:
244 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
245 nr_keyids = (1UL << keyid_bits) - 1;
246 if (nr_keyids) {
247 pr_info_once("x86/mktme: enabled by BIOS\n");
248 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
249 } else {
250 pr_info_once("x86/mktme: disabled by BIOS\n");
251 }
252
253 if (mktme_status == MKTME_UNINITIALIZED) {
254 /* MKTME is usable */
255 mktme_status = MKTME_ENABLED;
256 }
257
258 /*
259 * KeyID bits effectively lower the number of physical address
260 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
261 */
262 c->x86_phys_bits -= keyid_bits;
263 }
264
early_init_intel(struct cpuinfo_x86 * c)265 static void early_init_intel(struct cpuinfo_x86 *c)
266 {
267 u64 misc_enable;
268
269 /* Unmask CPUID levels if masked: */
270 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
271 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
272 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
273 c->cpuid_level = cpuid_eax(0);
274 get_cpu_cap(c);
275 }
276 }
277
278 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
279 (c->x86 == 0x6 && c->x86_model >= 0x0e))
280 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
281
282 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
283 c->microcode = intel_get_microcode_revision();
284
285 /* Now if any of them are set, check the blacklist and clear the lot */
286 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
287 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
288 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
289 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
290 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
291 setup_clear_cpu_cap(X86_FEATURE_IBRS);
292 setup_clear_cpu_cap(X86_FEATURE_IBPB);
293 setup_clear_cpu_cap(X86_FEATURE_STIBP);
294 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
295 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
296 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
297 setup_clear_cpu_cap(X86_FEATURE_SSBD);
298 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
299 }
300
301 /*
302 * Atom erratum AAE44/AAF40/AAG38/AAH41:
303 *
304 * A race condition between speculative fetches and invalidating
305 * a large page. This is worked around in microcode, but we
306 * need the microcode to have already been loaded... so if it is
307 * not, recommend a BIOS update and disable large pages.
308 */
309 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
310 c->microcode < 0x20e) {
311 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
312 clear_cpu_cap(c, X86_FEATURE_PSE);
313 }
314
315 #ifdef CONFIG_X86_64
316 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
317 #else
318 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
319 if (c->x86 == 15 && c->x86_cache_alignment == 64)
320 c->x86_cache_alignment = 128;
321 #endif
322
323 /* CPUID workaround for 0F33/0F34 CPU */
324 if (c->x86 == 0xF && c->x86_model == 0x3
325 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
326 c->x86_phys_bits = 36;
327
328 /*
329 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
330 * with P/T states and does not stop in deep C-states.
331 *
332 * It is also reliable across cores and sockets. (but not across
333 * cabinets - we turn it off in that case explicitly.)
334 */
335 if (c->x86_power & (1 << 8)) {
336 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
337 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
338 }
339
340 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
341 if (c->x86 == 6) {
342 switch (c->x86_model) {
343 case INTEL_FAM6_ATOM_SALTWELL_MID:
344 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
345 case INTEL_FAM6_ATOM_SILVERMONT_MID:
346 case INTEL_FAM6_ATOM_AIRMONT_NP:
347 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
348 break;
349 default:
350 break;
351 }
352 }
353
354 /*
355 * There is a known erratum on Pentium III and Core Solo
356 * and Core Duo CPUs.
357 * " Page with PAT set to WC while associated MTRR is UC
358 * may consolidate to UC "
359 * Because of this erratum, it is better to stick with
360 * setting WC in MTRR rather than using PAT on these CPUs.
361 *
362 * Enable PAT WC only on P4, Core 2 or later CPUs.
363 */
364 if (c->x86 == 6 && c->x86_model < 15)
365 clear_cpu_cap(c, X86_FEATURE_PAT);
366
367 /*
368 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
369 * clear the fast string and enhanced fast string CPU capabilities.
370 */
371 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
372 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
373 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
374 pr_info("Disabled fast string operations\n");
375 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
376 setup_clear_cpu_cap(X86_FEATURE_ERMS);
377 }
378 }
379
380 /*
381 * Intel Quark Core DevMan_001.pdf section 6.4.11
382 * "The operating system also is required to invalidate (i.e., flush)
383 * the TLB when any changes are made to any of the page table entries.
384 * The operating system must reload CR3 to cause the TLB to be flushed"
385 *
386 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
387 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
388 * to be modified.
389 */
390 if (c->x86 == 5 && c->x86_model == 9) {
391 pr_info("Disabling PGE capability bit\n");
392 setup_clear_cpu_cap(X86_FEATURE_PGE);
393 }
394
395 if (c->cpuid_level >= 0x00000001) {
396 u32 eax, ebx, ecx, edx;
397
398 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
399 /*
400 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
401 * apicids which are reserved per package. Store the resulting
402 * shift value for the package management code.
403 */
404 if (edx & (1U << 28))
405 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
406 }
407
408 check_memory_type_self_snoop_errata(c);
409
410 /*
411 * Get the number of SMT siblings early from the extended topology
412 * leaf, if available. Otherwise try the legacy SMT detection.
413 */
414 if (detect_extended_topology_early(c) < 0)
415 detect_ht_early(c);
416
417 /*
418 * Adjust the number of physical bits early because it affects the
419 * valid bits of the MTRR mask registers.
420 */
421 if (cpu_has(c, X86_FEATURE_TME))
422 detect_tme_early(c);
423 }
424
bsp_init_intel(struct cpuinfo_x86 * c)425 static void bsp_init_intel(struct cpuinfo_x86 *c)
426 {
427 resctrl_cpu_detect(c);
428 }
429
430 #ifdef CONFIG_X86_32
431 /*
432 * Early probe support logic for ppro memory erratum #50
433 *
434 * This is called before we do cpu ident work
435 */
436
ppro_with_ram_bug(void)437 int ppro_with_ram_bug(void)
438 {
439 /* Uses data from early_cpu_detect now */
440 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
441 boot_cpu_data.x86 == 6 &&
442 boot_cpu_data.x86_model == 1 &&
443 boot_cpu_data.x86_stepping < 8) {
444 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
445 return 1;
446 }
447 return 0;
448 }
449
intel_smp_check(struct cpuinfo_x86 * c)450 static void intel_smp_check(struct cpuinfo_x86 *c)
451 {
452 /* calling is from identify_secondary_cpu() ? */
453 if (!c->cpu_index)
454 return;
455
456 /*
457 * Mask B, Pentium, but not Pentium MMX
458 */
459 if (c->x86 == 5 &&
460 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
461 c->x86_model <= 3) {
462 /*
463 * Remember we have B step Pentia with bugs
464 */
465 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
466 "with B stepping processors.\n");
467 }
468 }
469
470 static int forcepae;
forcepae_setup(char * __unused)471 static int __init forcepae_setup(char *__unused)
472 {
473 forcepae = 1;
474 return 1;
475 }
476 __setup("forcepae", forcepae_setup);
477
intel_workarounds(struct cpuinfo_x86 * c)478 static void intel_workarounds(struct cpuinfo_x86 *c)
479 {
480 #ifdef CONFIG_X86_F00F_BUG
481 /*
482 * All models of Pentium and Pentium with MMX technology CPUs
483 * have the F0 0F bug, which lets nonprivileged users lock up the
484 * system. Announce that the fault handler will be checking for it.
485 * The Quark is also family 5, but does not have the same bug.
486 */
487 clear_cpu_bug(c, X86_BUG_F00F);
488 if (c->x86 == 5 && c->x86_model < 9) {
489 static int f00f_workaround_enabled;
490
491 set_cpu_bug(c, X86_BUG_F00F);
492 if (!f00f_workaround_enabled) {
493 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
494 f00f_workaround_enabled = 1;
495 }
496 }
497 #endif
498
499 /*
500 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
501 * model 3 mask 3
502 */
503 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
504 clear_cpu_cap(c, X86_FEATURE_SEP);
505
506 /*
507 * PAE CPUID issue: many Pentium M report no PAE but may have a
508 * functionally usable PAE implementation.
509 * Forcefully enable PAE if kernel parameter "forcepae" is present.
510 */
511 if (forcepae) {
512 pr_warn("PAE forced!\n");
513 set_cpu_cap(c, X86_FEATURE_PAE);
514 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
515 }
516
517 /*
518 * P4 Xeon erratum 037 workaround.
519 * Hardware prefetcher may cause stale data to be loaded into the cache.
520 */
521 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
522 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
523 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
524 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
525 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
526 }
527 }
528
529 /*
530 * See if we have a good local APIC by checking for buggy Pentia,
531 * i.e. all B steppings and the C2 stepping of P54C when using their
532 * integrated APIC (see 11AP erratum in "Pentium Processor
533 * Specification Update").
534 */
535 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
536 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
537 set_cpu_bug(c, X86_BUG_11AP);
538
539
540 #ifdef CONFIG_X86_INTEL_USERCOPY
541 /*
542 * Set up the preferred alignment for movsl bulk memory moves
543 */
544 switch (c->x86) {
545 case 4: /* 486: untested */
546 break;
547 case 5: /* Old Pentia: untested */
548 break;
549 case 6: /* PII/PIII only like movsl with 8-byte alignment */
550 movsl_mask.mask = 7;
551 break;
552 case 15: /* P4 is OK down to 8-byte alignment */
553 movsl_mask.mask = 7;
554 break;
555 }
556 #endif
557
558 intel_smp_check(c);
559 }
560 #else
intel_workarounds(struct cpuinfo_x86 * c)561 static void intel_workarounds(struct cpuinfo_x86 *c)
562 {
563 }
564 #endif
565
srat_detect_node(struct cpuinfo_x86 * c)566 static void srat_detect_node(struct cpuinfo_x86 *c)
567 {
568 #ifdef CONFIG_NUMA
569 unsigned node;
570 int cpu = smp_processor_id();
571
572 /* Don't do the funky fallback heuristics the AMD version employs
573 for now. */
574 node = numa_cpu_node(cpu);
575 if (node == NUMA_NO_NODE || !node_online(node)) {
576 /* reuse the value from init_cpu_to_node() */
577 node = cpu_to_node(cpu);
578 }
579 numa_set_node(cpu, node);
580 #endif
581 }
582
init_cpuid_fault(struct cpuinfo_x86 * c)583 static void init_cpuid_fault(struct cpuinfo_x86 *c)
584 {
585 u64 msr;
586
587 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
588 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
589 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
590 }
591 }
592
init_intel_misc_features(struct cpuinfo_x86 * c)593 static void init_intel_misc_features(struct cpuinfo_x86 *c)
594 {
595 u64 msr;
596
597 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
598 return;
599
600 /* Clear all MISC features */
601 this_cpu_write(msr_misc_features_shadow, 0);
602
603 /* Check features and update capabilities and shadow control bits */
604 init_cpuid_fault(c);
605 probe_xeon_phi_r3mwait(c);
606
607 msr = this_cpu_read(msr_misc_features_shadow);
608 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
609 }
610
611 static void split_lock_init(void);
612
init_intel(struct cpuinfo_x86 * c)613 static void init_intel(struct cpuinfo_x86 *c)
614 {
615 early_init_intel(c);
616
617 intel_workarounds(c);
618
619 /*
620 * Detect the extended topology information if available. This
621 * will reinitialise the initial_apicid which will be used
622 * in init_intel_cacheinfo()
623 */
624 detect_extended_topology(c);
625
626 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
627 /*
628 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
629 * detection.
630 */
631 detect_num_cpu_cores(c);
632 #ifdef CONFIG_X86_32
633 detect_ht(c);
634 #endif
635 }
636
637 init_intel_cacheinfo(c);
638
639 if (c->cpuid_level > 9) {
640 unsigned eax = cpuid_eax(10);
641 /* Check for version and the number of counters */
642 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
643 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
644 }
645
646 if (cpu_has(c, X86_FEATURE_XMM2))
647 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
648
649 if (boot_cpu_has(X86_FEATURE_DS)) {
650 unsigned int l1, l2;
651
652 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
653 if (!(l1 & (1<<11)))
654 set_cpu_cap(c, X86_FEATURE_BTS);
655 if (!(l1 & (1<<12)))
656 set_cpu_cap(c, X86_FEATURE_PEBS);
657 }
658
659 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
660 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
661 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
662
663 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
664 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
665 set_cpu_bug(c, X86_BUG_MONITOR);
666
667 #ifdef CONFIG_X86_64
668 if (c->x86 == 15)
669 c->x86_cache_alignment = c->x86_clflush_size * 2;
670 if (c->x86 == 6)
671 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
672 #else
673 /*
674 * Names for the Pentium II/Celeron processors
675 * detectable only by also checking the cache size.
676 * Dixon is NOT a Celeron.
677 */
678 if (c->x86 == 6) {
679 unsigned int l2 = c->x86_cache_size;
680 char *p = NULL;
681
682 switch (c->x86_model) {
683 case 5:
684 if (l2 == 0)
685 p = "Celeron (Covington)";
686 else if (l2 == 256)
687 p = "Mobile Pentium II (Dixon)";
688 break;
689
690 case 6:
691 if (l2 == 128)
692 p = "Celeron (Mendocino)";
693 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
694 p = "Celeron-A";
695 break;
696
697 case 8:
698 if (l2 == 128)
699 p = "Celeron (Coppermine)";
700 break;
701 }
702
703 if (p)
704 strcpy(c->x86_model_id, p);
705 }
706
707 if (c->x86 == 15)
708 set_cpu_cap(c, X86_FEATURE_P4);
709 if (c->x86 == 6)
710 set_cpu_cap(c, X86_FEATURE_P3);
711 #endif
712
713 /* Work around errata */
714 srat_detect_node(c);
715
716 init_ia32_feat_ctl(c);
717
718 init_intel_misc_features(c);
719
720 if (tsx_ctrl_state == TSX_CTRL_ENABLE)
721 tsx_enable();
722 if (tsx_ctrl_state == TSX_CTRL_DISABLE)
723 tsx_disable();
724
725 split_lock_init();
726 }
727
728 #ifdef CONFIG_X86_32
intel_size_cache(struct cpuinfo_x86 * c,unsigned int size)729 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
730 {
731 /*
732 * Intel PIII Tualatin. This comes in two flavours.
733 * One has 256kb of cache, the other 512. We have no way
734 * to determine which, so we use a boottime override
735 * for the 512kb model, and assume 256 otherwise.
736 */
737 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
738 size = 256;
739
740 /*
741 * Intel Quark SoC X1000 contains a 4-way set associative
742 * 16K cache with a 16 byte cache line and 256 lines per tag
743 */
744 if ((c->x86 == 5) && (c->x86_model == 9))
745 size = 16;
746 return size;
747 }
748 #endif
749
750 #define TLB_INST_4K 0x01
751 #define TLB_INST_4M 0x02
752 #define TLB_INST_2M_4M 0x03
753
754 #define TLB_INST_ALL 0x05
755 #define TLB_INST_1G 0x06
756
757 #define TLB_DATA_4K 0x11
758 #define TLB_DATA_4M 0x12
759 #define TLB_DATA_2M_4M 0x13
760 #define TLB_DATA_4K_4M 0x14
761
762 #define TLB_DATA_1G 0x16
763
764 #define TLB_DATA0_4K 0x21
765 #define TLB_DATA0_4M 0x22
766 #define TLB_DATA0_2M_4M 0x23
767
768 #define STLB_4K 0x41
769 #define STLB_4K_2M 0x42
770
771 static const struct _tlb_table intel_tlb_table[] = {
772 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
773 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
774 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
775 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
776 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
777 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
778 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
779 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
780 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
781 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
782 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
783 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
784 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
785 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
786 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
787 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
788 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
789 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
790 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
791 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
792 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
793 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
794 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
795 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
796 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
797 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
798 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
799 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
800 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
801 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
802 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
803 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
804 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
805 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
806 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
807 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
808 { 0x00, 0, 0 }
809 };
810
intel_tlb_lookup(const unsigned char desc)811 static void intel_tlb_lookup(const unsigned char desc)
812 {
813 unsigned char k;
814 if (desc == 0)
815 return;
816
817 /* look up this descriptor in the table */
818 for (k = 0; intel_tlb_table[k].descriptor != desc &&
819 intel_tlb_table[k].descriptor != 0; k++)
820 ;
821
822 if (intel_tlb_table[k].tlb_type == 0)
823 return;
824
825 switch (intel_tlb_table[k].tlb_type) {
826 case STLB_4K:
827 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
828 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
829 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
830 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
831 break;
832 case STLB_4K_2M:
833 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
834 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
835 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
836 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
837 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
838 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
839 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
840 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
841 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
842 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
843 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
844 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
845 break;
846 case TLB_INST_ALL:
847 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
848 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
849 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
850 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
851 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
852 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
853 break;
854 case TLB_INST_4K:
855 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
856 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
857 break;
858 case TLB_INST_4M:
859 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
860 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
861 break;
862 case TLB_INST_2M_4M:
863 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
864 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
865 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
866 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
867 break;
868 case TLB_DATA_4K:
869 case TLB_DATA0_4K:
870 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
871 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
872 break;
873 case TLB_DATA_4M:
874 case TLB_DATA0_4M:
875 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
876 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
877 break;
878 case TLB_DATA_2M_4M:
879 case TLB_DATA0_2M_4M:
880 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
881 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
882 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
883 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
884 break;
885 case TLB_DATA_4K_4M:
886 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
887 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
888 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
889 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
890 break;
891 case TLB_DATA_1G:
892 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
893 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
894 break;
895 }
896 }
897
intel_detect_tlb(struct cpuinfo_x86 * c)898 static void intel_detect_tlb(struct cpuinfo_x86 *c)
899 {
900 int i, j, n;
901 unsigned int regs[4];
902 unsigned char *desc = (unsigned char *)regs;
903
904 if (c->cpuid_level < 2)
905 return;
906
907 /* Number of times to iterate */
908 n = cpuid_eax(2) & 0xFF;
909
910 for (i = 0 ; i < n ; i++) {
911 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
912
913 /* If bit 31 is set, this is an unknown format */
914 for (j = 0 ; j < 3 ; j++)
915 if (regs[j] & (1 << 31))
916 regs[j] = 0;
917
918 /* Byte 0 is level count, not a descriptor */
919 for (j = 1 ; j < 16 ; j++)
920 intel_tlb_lookup(desc[j]);
921 }
922 }
923
924 static const struct cpu_dev intel_cpu_dev = {
925 .c_vendor = "Intel",
926 .c_ident = { "GenuineIntel" },
927 #ifdef CONFIG_X86_32
928 .legacy_models = {
929 { .family = 4, .model_names =
930 {
931 [0] = "486 DX-25/33",
932 [1] = "486 DX-50",
933 [2] = "486 SX",
934 [3] = "486 DX/2",
935 [4] = "486 SL",
936 [5] = "486 SX/2",
937 [7] = "486 DX/2-WB",
938 [8] = "486 DX/4",
939 [9] = "486 DX/4-WB"
940 }
941 },
942 { .family = 5, .model_names =
943 {
944 [0] = "Pentium 60/66 A-step",
945 [1] = "Pentium 60/66",
946 [2] = "Pentium 75 - 200",
947 [3] = "OverDrive PODP5V83",
948 [4] = "Pentium MMX",
949 [7] = "Mobile Pentium 75 - 200",
950 [8] = "Mobile Pentium MMX",
951 [9] = "Quark SoC X1000",
952 }
953 },
954 { .family = 6, .model_names =
955 {
956 [0] = "Pentium Pro A-step",
957 [1] = "Pentium Pro",
958 [3] = "Pentium II (Klamath)",
959 [4] = "Pentium II (Deschutes)",
960 [5] = "Pentium II (Deschutes)",
961 [6] = "Mobile Pentium II",
962 [7] = "Pentium III (Katmai)",
963 [8] = "Pentium III (Coppermine)",
964 [10] = "Pentium III (Cascades)",
965 [11] = "Pentium III (Tualatin)",
966 }
967 },
968 { .family = 15, .model_names =
969 {
970 [0] = "Pentium 4 (Unknown)",
971 [1] = "Pentium 4 (Willamette)",
972 [2] = "Pentium 4 (Northwood)",
973 [4] = "Pentium 4 (Foster)",
974 [5] = "Pentium 4 (Foster)",
975 }
976 },
977 },
978 .legacy_cache_size = intel_size_cache,
979 #endif
980 .c_detect_tlb = intel_detect_tlb,
981 .c_early_init = early_init_intel,
982 .c_bsp_init = bsp_init_intel,
983 .c_init = init_intel,
984 .c_x86_vendor = X86_VENDOR_INTEL,
985 };
986
987 cpu_dev_register(intel_cpu_dev);
988
989 #undef pr_fmt
990 #define pr_fmt(fmt) "x86/split lock detection: " fmt
991
992 static const struct {
993 const char *option;
994 enum split_lock_detect_state state;
995 } sld_options[] __initconst = {
996 { "off", sld_off },
997 { "warn", sld_warn },
998 { "fatal", sld_fatal },
999 };
1000
match_option(const char * arg,int arglen,const char * opt)1001 static inline bool match_option(const char *arg, int arglen, const char *opt)
1002 {
1003 int len = strlen(opt);
1004
1005 return len == arglen && !strncmp(arg, opt, len);
1006 }
1007
split_lock_verify_msr(bool on)1008 static bool split_lock_verify_msr(bool on)
1009 {
1010 u64 ctrl, tmp;
1011
1012 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
1013 return false;
1014 if (on)
1015 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1016 else
1017 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1018 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
1019 return false;
1020 rdmsrl(MSR_TEST_CTRL, tmp);
1021 return ctrl == tmp;
1022 }
1023
split_lock_setup(void)1024 static void __init split_lock_setup(void)
1025 {
1026 enum split_lock_detect_state state = sld_warn;
1027 char arg[20];
1028 int i, ret;
1029
1030 if (!split_lock_verify_msr(false)) {
1031 pr_info("MSR access failed: Disabled\n");
1032 return;
1033 }
1034
1035 ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1036 arg, sizeof(arg));
1037 if (ret >= 0) {
1038 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1039 if (match_option(arg, ret, sld_options[i].option)) {
1040 state = sld_options[i].state;
1041 break;
1042 }
1043 }
1044 }
1045
1046 switch (state) {
1047 case sld_off:
1048 pr_info("disabled\n");
1049 return;
1050 case sld_warn:
1051 pr_info("warning about user-space split_locks\n");
1052 break;
1053 case sld_fatal:
1054 pr_info("sending SIGBUS on user-space split_locks\n");
1055 break;
1056 }
1057
1058 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1059
1060 if (!split_lock_verify_msr(true)) {
1061 pr_info("MSR access failed: Disabled\n");
1062 return;
1063 }
1064
1065 sld_state = state;
1066 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1067 }
1068
1069 /*
1070 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1071 * is not implemented as one thread could undo the setting of the other
1072 * thread immediately after dropping the lock anyway.
1073 */
sld_update_msr(bool on)1074 static void sld_update_msr(bool on)
1075 {
1076 u64 test_ctrl_val = msr_test_ctrl_cache;
1077
1078 if (on)
1079 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1080
1081 wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1082 }
1083
split_lock_init(void)1084 static void split_lock_init(void)
1085 {
1086 if (cpu_model_supports_sld)
1087 split_lock_verify_msr(sld_state != sld_off);
1088 }
1089
split_lock_warn(unsigned long ip)1090 static void split_lock_warn(unsigned long ip)
1091 {
1092 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1093 current->comm, current->pid, ip);
1094
1095 /*
1096 * Disable the split lock detection for this task so it can make
1097 * progress and set TIF_SLD so the detection is re-enabled via
1098 * switch_to_sld() when the task is scheduled out.
1099 */
1100 sld_update_msr(false);
1101 set_tsk_thread_flag(current, TIF_SLD);
1102 }
1103
handle_guest_split_lock(unsigned long ip)1104 bool handle_guest_split_lock(unsigned long ip)
1105 {
1106 if (sld_state == sld_warn) {
1107 split_lock_warn(ip);
1108 return true;
1109 }
1110
1111 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",
1112 current->comm, current->pid,
1113 sld_state == sld_fatal ? "fatal" : "bogus", ip);
1114
1115 current->thread.error_code = 0;
1116 current->thread.trap_nr = X86_TRAP_AC;
1117 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1118 return false;
1119 }
1120 EXPORT_SYMBOL_GPL(handle_guest_split_lock);
1121
handle_user_split_lock(struct pt_regs * regs,long error_code)1122 bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1123 {
1124 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1125 return false;
1126 split_lock_warn(regs->ip);
1127 return true;
1128 }
1129
1130 /*
1131 * This function is called only when switching between tasks with
1132 * different split-lock detection modes. It sets the MSR for the
1133 * mode of the new task. This is right most of the time, but since
1134 * the MSR is shared by hyperthreads on a physical core there can
1135 * be glitches when the two threads need different modes.
1136 */
switch_to_sld(unsigned long tifn)1137 void switch_to_sld(unsigned long tifn)
1138 {
1139 sld_update_msr(!(tifn & _TIF_SLD));
1140 }
1141
1142 /*
1143 * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should
1144 * only be trusted if it is confirmed that a CPU model implements a
1145 * specific feature at a particular bit position.
1146 *
1147 * The possible driver data field values:
1148 *
1149 * - 0: CPU models that are known to have the per-core split-lock detection
1150 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.
1151 *
1152 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use
1153 * bit 5 to enumerate the per-core split-lock detection feature.
1154 */
1155 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1156 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
1157 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
1158 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
1159 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1),
1160 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1),
1161 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1),
1162 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, 1),
1163 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, 1),
1164 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 1),
1165 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 1),
1166 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 1),
1167 {}
1168 };
1169
cpu_set_core_cap_bits(struct cpuinfo_x86 * c)1170 void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c)
1171 {
1172 const struct x86_cpu_id *m;
1173 u64 ia32_core_caps;
1174
1175 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1176 return;
1177
1178 m = x86_match_cpu(split_lock_cpu_ids);
1179 if (!m)
1180 return;
1181
1182 switch (m->driver_data) {
1183 case 0:
1184 break;
1185 case 1:
1186 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
1187 return;
1188 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1189 if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT))
1190 return;
1191 break;
1192 default:
1193 return;
1194 }
1195
1196 cpu_model_supports_sld = true;
1197 split_lock_setup();
1198 }
1199