1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10
11 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
12
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
15 #include "clk-rcg.h"
16 #include "clk-regmap.h"
17 #include "common.h"
18 #include "gdsc.h"
19
20 #define CX_GMU_CBCR_SLEEP_MASK 0xF
21 #define CX_GMU_CBCR_SLEEP_SHIFT 4
22 #define CX_GMU_CBCR_WAKE_MASK 0xF
23 #define CX_GMU_CBCR_WAKE_SHIFT 8
24
25 enum {
26 P_BI_TCXO,
27 P_CORE_BI_PLL_TEST_SE,
28 P_GPLL0_OUT_MAIN,
29 P_GPLL0_OUT_MAIN_DIV,
30 P_GPU_CC_PLL1_OUT_EVEN,
31 P_GPU_CC_PLL1_OUT_MAIN,
32 P_GPU_CC_PLL1_OUT_ODD,
33 };
34
35 static const struct pll_vco fabia_vco[] = {
36 { 249600000, 2000000000, 0 },
37 };
38
39 static struct clk_alpha_pll gpu_cc_pll1 = {
40 .offset = 0x100,
41 .vco_table = fabia_vco,
42 .num_vco = ARRAY_SIZE(fabia_vco),
43 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
44 .clkr = {
45 .hw.init = &(struct clk_init_data){
46 .name = "gpu_cc_pll1",
47 .parent_data = &(const struct clk_parent_data){
48 .fw_name = "bi_tcxo",
49 },
50 .num_parents = 1,
51 .ops = &clk_alpha_pll_fabia_ops,
52 },
53 },
54 };
55
56 static const struct parent_map gpu_cc_parent_map_0[] = {
57 { P_BI_TCXO, 0 },
58 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
59 { P_GPLL0_OUT_MAIN, 5 },
60 { P_GPLL0_OUT_MAIN_DIV, 6 },
61 };
62
63 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
64 { .fw_name = "bi_tcxo" },
65 { .hw = &gpu_cc_pll1.clkr.hw },
66 { .fw_name = "gcc_gpu_gpll0_clk_src" },
67 { .fw_name = "gcc_gpu_gpll0_div_clk_src" },
68 };
69
70 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
71 F(19200000, P_BI_TCXO, 1, 0, 0),
72 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
73 { }
74 };
75
76 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
77 .cmd_rcgr = 0x1120,
78 .mnd_width = 0,
79 .hid_width = 5,
80 .parent_map = gpu_cc_parent_map_0,
81 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
82 .clkr.hw.init = &(struct clk_init_data){
83 .name = "gpu_cc_gmu_clk_src",
84 .parent_data = gpu_cc_parent_data_0,
85 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
86 .flags = CLK_SET_RATE_PARENT,
87 .ops = &clk_rcg2_shared_ops,
88 },
89 };
90
91 static struct clk_branch gpu_cc_crc_ahb_clk = {
92 .halt_reg = 0x107c,
93 .halt_check = BRANCH_HALT_DELAY,
94 .clkr = {
95 .enable_reg = 0x107c,
96 .enable_mask = BIT(0),
97 .hw.init = &(struct clk_init_data){
98 .name = "gpu_cc_crc_ahb_clk",
99 .ops = &clk_branch2_ops,
100 },
101 },
102 };
103
104 static struct clk_branch gpu_cc_cx_gmu_clk = {
105 .halt_reg = 0x1098,
106 .halt_check = BRANCH_HALT,
107 .clkr = {
108 .enable_reg = 0x1098,
109 .enable_mask = BIT(0),
110 .hw.init = &(struct clk_init_data){
111 .name = "gpu_cc_cx_gmu_clk",
112 .parent_data = &(const struct clk_parent_data){
113 .hw = &gpu_cc_gmu_clk_src.clkr.hw,
114 },
115 .num_parents = 1,
116 .flags = CLK_SET_RATE_PARENT,
117 .ops = &clk_branch2_ops,
118 },
119 },
120 };
121
122 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
123 .halt_reg = 0x108c,
124 .halt_check = BRANCH_HALT_DELAY,
125 .clkr = {
126 .enable_reg = 0x108c,
127 .enable_mask = BIT(0),
128 .hw.init = &(struct clk_init_data){
129 .name = "gpu_cc_cx_snoc_dvm_clk",
130 .ops = &clk_branch2_ops,
131 },
132 },
133 };
134
135 static struct clk_branch gpu_cc_cxo_aon_clk = {
136 .halt_reg = 0x1004,
137 .halt_check = BRANCH_HALT_DELAY,
138 .clkr = {
139 .enable_reg = 0x1004,
140 .enable_mask = BIT(0),
141 .hw.init = &(struct clk_init_data){
142 .name = "gpu_cc_cxo_aon_clk",
143 .ops = &clk_branch2_ops,
144 },
145 },
146 };
147
148 static struct clk_branch gpu_cc_cxo_clk = {
149 .halt_reg = 0x109c,
150 .halt_check = BRANCH_HALT,
151 .clkr = {
152 .enable_reg = 0x109c,
153 .enable_mask = BIT(0),
154 .hw.init = &(struct clk_init_data){
155 .name = "gpu_cc_cxo_clk",
156 .ops = &clk_branch2_ops,
157 },
158 },
159 };
160
161 static struct gdsc cx_gdsc = {
162 .gdscr = 0x106c,
163 .gds_hw_ctrl = 0x1540,
164 .clk_dis_wait_val = 8,
165 .pd = {
166 .name = "cx_gdsc",
167 },
168 .pwrsts = PWRSTS_OFF_ON,
169 .flags = VOTABLE,
170 };
171
172 static struct gdsc gx_gdsc = {
173 .gdscr = 0x100c,
174 .clamp_io_ctrl = 0x1508,
175 .pd = {
176 .name = "gx_gdsc",
177 .power_on = gdsc_gx_do_nothing_enable,
178 },
179 .pwrsts = PWRSTS_OFF_ON,
180 .flags = CLAMP_IO,
181 };
182
183 static struct gdsc *gpu_cc_sc7180_gdscs[] = {
184 [CX_GDSC] = &cx_gdsc,
185 [GX_GDSC] = &gx_gdsc,
186 };
187
188 static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
189 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
190 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
191 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
192 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
193 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
194 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
195 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
196 };
197
198 static const struct regmap_config gpu_cc_sc7180_regmap_config = {
199 .reg_bits = 32,
200 .reg_stride = 4,
201 .val_bits = 32,
202 .max_register = 0x8008,
203 .fast_io = true,
204 };
205
206 static const struct qcom_cc_desc gpu_cc_sc7180_desc = {
207 .config = &gpu_cc_sc7180_regmap_config,
208 .clks = gpu_cc_sc7180_clocks,
209 .num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks),
210 .gdscs = gpu_cc_sc7180_gdscs,
211 .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
212 };
213
214 static const struct of_device_id gpu_cc_sc7180_match_table[] = {
215 { .compatible = "qcom,sc7180-gpucc" },
216 { }
217 };
218 MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table);
219
gpu_cc_sc7180_probe(struct platform_device * pdev)220 static int gpu_cc_sc7180_probe(struct platform_device *pdev)
221 {
222 struct regmap *regmap;
223 struct alpha_pll_config gpu_cc_pll_config = {};
224 unsigned int value, mask;
225
226 regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc);
227 if (IS_ERR(regmap))
228 return PTR_ERR(regmap);
229
230 /* 360MHz Configuration */
231 gpu_cc_pll_config.l = 0x12;
232 gpu_cc_pll_config.alpha = 0xc000;
233 gpu_cc_pll_config.config_ctl_val = 0x20485699;
234 gpu_cc_pll_config.config_ctl_hi_val = 0x00002067;
235 gpu_cc_pll_config.user_ctl_val = 0x00000001;
236 gpu_cc_pll_config.user_ctl_hi_val = 0x00004805;
237 gpu_cc_pll_config.test_ctl_hi_val = 0x40000000;
238
239 clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config);
240
241 /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
242 mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
243 mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
244 value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
245 regmap_update_bits(regmap, 0x1098, mask, value);
246
247 return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
248 }
249
250 static struct platform_driver gpu_cc_sc7180_driver = {
251 .probe = gpu_cc_sc7180_probe,
252 .driver = {
253 .name = "sc7180-gpucc",
254 .of_match_table = gpu_cc_sc7180_match_table,
255 },
256 };
257
gpu_cc_sc7180_init(void)258 static int __init gpu_cc_sc7180_init(void)
259 {
260 return platform_driver_register(&gpu_cc_sc7180_driver);
261 }
262 subsys_initcall(gpu_cc_sc7180_init);
263
gpu_cc_sc7180_exit(void)264 static void __exit gpu_cc_sc7180_exit(void)
265 {
266 platform_driver_unregister(&gpu_cc_sc7180_driver);
267 }
268 module_exit(gpu_cc_sc7180_exit);
269
270 MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver");
271 MODULE_LICENSE("GPL v2");
272