1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
24 #include <linux/fs.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <linux/pm_qos.h>
28 #include <trace/events/power.h>
29
30 #include <asm/div64.h>
31 #include <asm/msr.h>
32 #include <asm/cpu_device_id.h>
33 #include <asm/cpufeature.h>
34 #include <asm/intel-family.h>
35
36 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
37
38 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
39 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
40 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
41
42 #ifdef CONFIG_ACPI
43 #include <acpi/processor.h>
44 #include <acpi/cppc_acpi.h>
45 #endif
46
47 #define FRAC_BITS 8
48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
49 #define fp_toint(X) ((X) >> FRAC_BITS)
50
51 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
52
53 #define EXT_BITS 6
54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
57
mul_fp(int32_t x,int32_t y)58 static inline int32_t mul_fp(int32_t x, int32_t y)
59 {
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61 }
62
div_fp(s64 x,s64 y)63 static inline int32_t div_fp(s64 x, s64 y)
64 {
65 return div64_s64((int64_t)x << FRAC_BITS, y);
66 }
67
ceiling_fp(int32_t x)68 static inline int ceiling_fp(int32_t x)
69 {
70 int mask, ret;
71
72 ret = fp_toint(x);
73 mask = (1 << FRAC_BITS) - 1;
74 if (x & mask)
75 ret += 1;
76 return ret;
77 }
78
percent_fp(int percent)79 static inline int32_t percent_fp(int percent)
80 {
81 return div_fp(percent, 100);
82 }
83
mul_ext_fp(u64 x,u64 y)84 static inline u64 mul_ext_fp(u64 x, u64 y)
85 {
86 return (x * y) >> EXT_FRAC_BITS;
87 }
88
div_ext_fp(u64 x,u64 y)89 static inline u64 div_ext_fp(u64 x, u64 y)
90 {
91 return div64_u64(x << EXT_FRAC_BITS, y);
92 }
93
percent_ext_fp(int percent)94 static inline int32_t percent_ext_fp(int percent)
95 {
96 return div_ext_fp(percent, 100);
97 }
98
99 /**
100 * struct sample - Store performance sample
101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
104 * P state. This can be different than core_avg_perf
105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
111 * current sample
112 * @time: Current time from scheduler
113 *
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
116 */
117 struct sample {
118 int32_t core_avg_perf;
119 int32_t busy_scaled;
120 u64 aperf;
121 u64 mperf;
122 u64 tsc;
123 u64 time;
124 };
125
126 /**
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
135 * frequency units
136 * @turbo_pstate: Max Turbo P state possible for this platform
137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
139 *
140 * Stores the per cpu model P state limits and current P state.
141 */
142 struct pstate_data {
143 int current_pstate;
144 int min_pstate;
145 int max_pstate;
146 int max_pstate_physical;
147 int scaling;
148 int turbo_pstate;
149 unsigned int max_freq;
150 unsigned int turbo_freq;
151 };
152
153 /**
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
156 * the lowest P state
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
161 *
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
165 */
166 struct vid_data {
167 int min;
168 int max;
169 int turbo;
170 int32_t ratio;
171 };
172
173 /**
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whether or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
181 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
182 * P-state capacity.
183 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
184 * P-state capacity.
185 */
186 struct global_params {
187 bool no_turbo;
188 bool turbo_disabled;
189 bool turbo_disabled_mf;
190 int max_perf_pct;
191 int min_perf_pct;
192 };
193
194 /**
195 * struct cpudata - Per CPU instance data storage
196 * @cpu: CPU number for this instance data
197 * @policy: CPUFreq policy value
198 * @update_util: CPUFreq utility callback information
199 * @update_util_set: CPUFreq utility callback is set
200 * @iowait_boost: iowait-related boost fraction
201 * @last_update: Time of the last update.
202 * @pstate: Stores P state limits for this CPU
203 * @vid: Stores VID limits for this CPU
204 * @last_sample_time: Last Sample time
205 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
210 * current sample
211 * @sample: Storage for storing last Sample data
212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
219 * @epp_policy: Last saved policy used to set EPP/EPB
220 * @epp_default: Power on default HWP energy performance
221 * preference/bias
222 * @epp_cached Cached HWP energy-performance preference value
223 * @hwp_req_cached: Cached value of the last HWP Request MSR
224 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
225 * @last_io_update: Last time when IO wake flag was set
226 * @sched_flags: Store scheduler flags for possible cross CPU update
227 * @hwp_boost_min: Last HWP boosted min performance
228 * @suspended: Whether or not the driver has been suspended.
229 *
230 * This structure stores per CPU instance data for all CPUs.
231 */
232 struct cpudata {
233 int cpu;
234
235 unsigned int policy;
236 struct update_util_data update_util;
237 bool update_util_set;
238
239 struct pstate_data pstate;
240 struct vid_data vid;
241
242 u64 last_update;
243 u64 last_sample_time;
244 u64 aperf_mperf_shift;
245 u64 prev_aperf;
246 u64 prev_mperf;
247 u64 prev_tsc;
248 u64 prev_cummulative_iowait;
249 struct sample sample;
250 int32_t min_perf_ratio;
251 int32_t max_perf_ratio;
252 #ifdef CONFIG_ACPI
253 struct acpi_processor_performance acpi_perf_data;
254 bool valid_pss_table;
255 #endif
256 unsigned int iowait_boost;
257 s16 epp_powersave;
258 s16 epp_policy;
259 s16 epp_default;
260 s16 epp_cached;
261 u64 hwp_req_cached;
262 u64 hwp_cap_cached;
263 u64 last_io_update;
264 unsigned int sched_flags;
265 u32 hwp_boost_min;
266 bool suspended;
267 };
268
269 static struct cpudata **all_cpu_data;
270
271 /**
272 * struct pstate_funcs - Per CPU model specific callbacks
273 * @get_max: Callback to get maximum non turbo effective P state
274 * @get_max_physical: Callback to get maximum non turbo physical P state
275 * @get_min: Callback to get minimum P state
276 * @get_turbo: Callback to get turbo P state
277 * @get_scaling: Callback to get frequency scaling factor
278 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
279 * @get_val: Callback to convert P state to actual MSR write value
280 * @get_vid: Callback to get VID data for Atom platforms
281 *
282 * Core and Atom CPU models have different way to get P State limits. This
283 * structure is used to store those callbacks.
284 */
285 struct pstate_funcs {
286 int (*get_max)(void);
287 int (*get_max_physical)(void);
288 int (*get_min)(void);
289 int (*get_turbo)(void);
290 int (*get_scaling)(void);
291 int (*get_aperf_mperf_shift)(void);
292 u64 (*get_val)(struct cpudata*, int pstate);
293 void (*get_vid)(struct cpudata *);
294 };
295
296 static struct pstate_funcs pstate_funcs __read_mostly;
297
298 static int hwp_active __read_mostly;
299 static int hwp_mode_bdw __read_mostly;
300 static bool per_cpu_limits __read_mostly;
301 static bool hwp_boost __read_mostly;
302
303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304
305 #ifdef CONFIG_ACPI
306 static bool acpi_ppc;
307 #endif
308
309 static struct global_params global;
310
311 static DEFINE_MUTEX(intel_pstate_driver_lock);
312 static DEFINE_MUTEX(intel_pstate_limits_lock);
313
314 #ifdef CONFIG_ACPI
315
intel_pstate_acpi_pm_profile_server(void)316 static bool intel_pstate_acpi_pm_profile_server(void)
317 {
318 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
319 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
320 return true;
321
322 return false;
323 }
324
intel_pstate_get_ppc_enable_status(void)325 static bool intel_pstate_get_ppc_enable_status(void)
326 {
327 if (intel_pstate_acpi_pm_profile_server())
328 return true;
329
330 return acpi_ppc;
331 }
332
333 #ifdef CONFIG_ACPI_CPPC_LIB
334
335 /* The work item is needed to avoid CPU hotplug locking issues */
intel_pstste_sched_itmt_work_fn(struct work_struct * work)336 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
337 {
338 sched_set_itmt_support();
339 }
340
341 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
342
intel_pstate_set_itmt_prio(int cpu)343 static void intel_pstate_set_itmt_prio(int cpu)
344 {
345 struct cppc_perf_caps cppc_perf;
346 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
347 int ret;
348
349 ret = cppc_get_perf_caps(cpu, &cppc_perf);
350 if (ret)
351 return;
352
353 /*
354 * The priorities can be set regardless of whether or not
355 * sched_set_itmt_support(true) has been called and it is valid to
356 * update them at any time after it has been called.
357 */
358 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
359
360 if (max_highest_perf <= min_highest_perf) {
361 if (cppc_perf.highest_perf > max_highest_perf)
362 max_highest_perf = cppc_perf.highest_perf;
363
364 if (cppc_perf.highest_perf < min_highest_perf)
365 min_highest_perf = cppc_perf.highest_perf;
366
367 if (max_highest_perf > min_highest_perf) {
368 /*
369 * This code can be run during CPU online under the
370 * CPU hotplug locks, so sched_set_itmt_support()
371 * cannot be called from here. Queue up a work item
372 * to invoke it.
373 */
374 schedule_work(&sched_itmt_work);
375 }
376 }
377 }
378
intel_pstate_get_cppc_guranteed(int cpu)379 static int intel_pstate_get_cppc_guranteed(int cpu)
380 {
381 struct cppc_perf_caps cppc_perf;
382 int ret;
383
384 ret = cppc_get_perf_caps(cpu, &cppc_perf);
385 if (ret)
386 return ret;
387
388 if (cppc_perf.guaranteed_perf)
389 return cppc_perf.guaranteed_perf;
390
391 return cppc_perf.nominal_perf;
392 }
393
394 #else /* CONFIG_ACPI_CPPC_LIB */
intel_pstate_set_itmt_prio(int cpu)395 static void intel_pstate_set_itmt_prio(int cpu)
396 {
397 }
398 #endif /* CONFIG_ACPI_CPPC_LIB */
399
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)400 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
401 {
402 struct cpudata *cpu;
403 int ret;
404 int i;
405
406 if (hwp_active) {
407 intel_pstate_set_itmt_prio(policy->cpu);
408 return;
409 }
410
411 if (!intel_pstate_get_ppc_enable_status())
412 return;
413
414 cpu = all_cpu_data[policy->cpu];
415
416 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
417 policy->cpu);
418 if (ret)
419 return;
420
421 /*
422 * Check if the control value in _PSS is for PERF_CTL MSR, which should
423 * guarantee that the states returned by it map to the states in our
424 * list directly.
425 */
426 if (cpu->acpi_perf_data.control_register.space_id !=
427 ACPI_ADR_SPACE_FIXED_HARDWARE)
428 goto err;
429
430 /*
431 * If there is only one entry _PSS, simply ignore _PSS and continue as
432 * usual without taking _PSS into account
433 */
434 if (cpu->acpi_perf_data.state_count < 2)
435 goto err;
436
437 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
438 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
439 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
440 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
441 (u32) cpu->acpi_perf_data.states[i].core_frequency,
442 (u32) cpu->acpi_perf_data.states[i].power,
443 (u32) cpu->acpi_perf_data.states[i].control);
444 }
445
446 cpu->valid_pss_table = true;
447 pr_debug("_PPC limits will be enforced\n");
448
449 return;
450
451 err:
452 cpu->valid_pss_table = false;
453 acpi_processor_unregister_performance(policy->cpu);
454 }
455
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)456 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
457 {
458 struct cpudata *cpu;
459
460 cpu = all_cpu_data[policy->cpu];
461 if (!cpu->valid_pss_table)
462 return;
463
464 acpi_processor_unregister_performance(policy->cpu);
465 }
466 #else /* CONFIG_ACPI */
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)467 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
468 {
469 }
470
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)471 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
472 {
473 }
474
intel_pstate_acpi_pm_profile_server(void)475 static inline bool intel_pstate_acpi_pm_profile_server(void)
476 {
477 return false;
478 }
479 #endif /* CONFIG_ACPI */
480
481 #ifndef CONFIG_ACPI_CPPC_LIB
intel_pstate_get_cppc_guranteed(int cpu)482 static int intel_pstate_get_cppc_guranteed(int cpu)
483 {
484 return -ENOTSUPP;
485 }
486 #endif /* CONFIG_ACPI_CPPC_LIB */
487
update_turbo_state(void)488 static inline void update_turbo_state(void)
489 {
490 u64 misc_en;
491 struct cpudata *cpu;
492
493 cpu = all_cpu_data[0];
494 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
495 global.turbo_disabled =
496 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
497 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
498 }
499
min_perf_pct_min(void)500 static int min_perf_pct_min(void)
501 {
502 struct cpudata *cpu = all_cpu_data[0];
503 int turbo_pstate = cpu->pstate.turbo_pstate;
504
505 return turbo_pstate ?
506 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
507 }
508
intel_pstate_get_epb(struct cpudata * cpu_data)509 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
510 {
511 u64 epb;
512 int ret;
513
514 if (!boot_cpu_has(X86_FEATURE_EPB))
515 return -ENXIO;
516
517 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
518 if (ret)
519 return (s16)ret;
520
521 return (s16)(epb & 0x0f);
522 }
523
intel_pstate_get_epp(struct cpudata * cpu_data,u64 hwp_req_data)524 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
525 {
526 s16 epp;
527
528 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
529 /*
530 * When hwp_req_data is 0, means that caller didn't read
531 * MSR_HWP_REQUEST, so need to read and get EPP.
532 */
533 if (!hwp_req_data) {
534 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
535 &hwp_req_data);
536 if (epp)
537 return epp;
538 }
539 epp = (hwp_req_data >> 24) & 0xff;
540 } else {
541 /* When there is no EPP present, HWP uses EPB settings */
542 epp = intel_pstate_get_epb(cpu_data);
543 }
544
545 return epp;
546 }
547
intel_pstate_set_epb(int cpu,s16 pref)548 static int intel_pstate_set_epb(int cpu, s16 pref)
549 {
550 u64 epb;
551 int ret;
552
553 if (!boot_cpu_has(X86_FEATURE_EPB))
554 return -ENXIO;
555
556 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
557 if (ret)
558 return ret;
559
560 epb = (epb & ~0x0f) | pref;
561 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
562
563 return 0;
564 }
565
566 /*
567 * EPP/EPB display strings corresponding to EPP index in the
568 * energy_perf_strings[]
569 * index String
570 *-------------------------------------
571 * 0 default
572 * 1 performance
573 * 2 balance_performance
574 * 3 balance_power
575 * 4 power
576 */
577 static const char * const energy_perf_strings[] = {
578 "default",
579 "performance",
580 "balance_performance",
581 "balance_power",
582 "power",
583 NULL
584 };
585 static const unsigned int epp_values[] = {
586 HWP_EPP_PERFORMANCE,
587 HWP_EPP_BALANCE_PERFORMANCE,
588 HWP_EPP_BALANCE_POWERSAVE,
589 HWP_EPP_POWERSAVE
590 };
591
intel_pstate_get_energy_pref_index(struct cpudata * cpu_data,int * raw_epp)592 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
593 {
594 s16 epp;
595 int index = -EINVAL;
596
597 *raw_epp = 0;
598 epp = intel_pstate_get_epp(cpu_data, 0);
599 if (epp < 0)
600 return epp;
601
602 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
603 if (epp == HWP_EPP_PERFORMANCE)
604 return 1;
605 if (epp == HWP_EPP_BALANCE_PERFORMANCE)
606 return 2;
607 if (epp == HWP_EPP_BALANCE_POWERSAVE)
608 return 3;
609 if (epp == HWP_EPP_POWERSAVE)
610 return 4;
611 *raw_epp = epp;
612 return 0;
613 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
614 /*
615 * Range:
616 * 0x00-0x03 : Performance
617 * 0x04-0x07 : Balance performance
618 * 0x08-0x0B : Balance power
619 * 0x0C-0x0F : Power
620 * The EPB is a 4 bit value, but our ranges restrict the
621 * value which can be set. Here only using top two bits
622 * effectively.
623 */
624 index = (epp >> 2) + 1;
625 }
626
627 return index;
628 }
629
intel_pstate_set_epp(struct cpudata * cpu,u32 epp)630 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
631 {
632 int ret;
633
634 /*
635 * Use the cached HWP Request MSR value, because in the active mode the
636 * register itself may be updated by intel_pstate_hwp_boost_up() or
637 * intel_pstate_hwp_boost_down() at any time.
638 */
639 u64 value = READ_ONCE(cpu->hwp_req_cached);
640
641 value &= ~GENMASK_ULL(31, 24);
642 value |= (u64)epp << 24;
643 /*
644 * The only other updater of hwp_req_cached in the active mode,
645 * intel_pstate_hwp_set(), is called under the same lock as this
646 * function, so it cannot run in parallel with the update below.
647 */
648 WRITE_ONCE(cpu->hwp_req_cached, value);
649 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
650 if (!ret)
651 cpu->epp_cached = epp;
652
653 return ret;
654 }
655
intel_pstate_set_energy_pref_index(struct cpudata * cpu_data,int pref_index,bool use_raw,u32 raw_epp)656 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
657 int pref_index, bool use_raw,
658 u32 raw_epp)
659 {
660 int epp = -EINVAL;
661 int ret;
662
663 if (!pref_index)
664 epp = cpu_data->epp_default;
665
666 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
667 if (use_raw)
668 epp = raw_epp;
669 else if (epp == -EINVAL)
670 epp = epp_values[pref_index - 1];
671
672 /*
673 * To avoid confusion, refuse to set EPP to any values different
674 * from 0 (performance) if the current policy is "performance",
675 * because those values would be overridden.
676 */
677 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
678 return -EBUSY;
679
680 ret = intel_pstate_set_epp(cpu_data, epp);
681 } else {
682 if (epp == -EINVAL)
683 epp = (pref_index - 1) << 2;
684 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
685 }
686
687 return ret;
688 }
689
show_energy_performance_available_preferences(struct cpufreq_policy * policy,char * buf)690 static ssize_t show_energy_performance_available_preferences(
691 struct cpufreq_policy *policy, char *buf)
692 {
693 int i = 0;
694 int ret = 0;
695
696 while (energy_perf_strings[i] != NULL)
697 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
698
699 ret += sprintf(&buf[ret], "\n");
700
701 return ret;
702 }
703
704 cpufreq_freq_attr_ro(energy_performance_available_preferences);
705
706 static struct cpufreq_driver intel_pstate;
707
store_energy_performance_preference(struct cpufreq_policy * policy,const char * buf,size_t count)708 static ssize_t store_energy_performance_preference(
709 struct cpufreq_policy *policy, const char *buf, size_t count)
710 {
711 struct cpudata *cpu = all_cpu_data[policy->cpu];
712 char str_preference[21];
713 bool raw = false;
714 ssize_t ret;
715 u32 epp = 0;
716
717 ret = sscanf(buf, "%20s", str_preference);
718 if (ret != 1)
719 return -EINVAL;
720
721 ret = match_string(energy_perf_strings, -1, str_preference);
722 if (ret < 0) {
723 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
724 return ret;
725
726 ret = kstrtouint(buf, 10, &epp);
727 if (ret)
728 return ret;
729
730 if (epp > 255)
731 return -EINVAL;
732
733 raw = true;
734 }
735
736 /*
737 * This function runs with the policy R/W semaphore held, which
738 * guarantees that the driver pointer will not change while it is
739 * running.
740 */
741 if (!intel_pstate_driver)
742 return -EAGAIN;
743
744 mutex_lock(&intel_pstate_limits_lock);
745
746 if (intel_pstate_driver == &intel_pstate) {
747 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
748 } else {
749 /*
750 * In the passive mode the governor needs to be stopped on the
751 * target CPU before the EPP update and restarted after it,
752 * which is super-heavy-weight, so make sure it is worth doing
753 * upfront.
754 */
755 if (!raw)
756 epp = ret ? epp_values[ret - 1] : cpu->epp_default;
757
758 if (cpu->epp_cached != epp) {
759 int err;
760
761 cpufreq_stop_governor(policy);
762 ret = intel_pstate_set_epp(cpu, epp);
763 err = cpufreq_start_governor(policy);
764 if (!ret)
765 ret = err;
766 } else {
767 ret = 0;
768 }
769 }
770
771 mutex_unlock(&intel_pstate_limits_lock);
772
773 return ret ?: count;
774 }
775
show_energy_performance_preference(struct cpufreq_policy * policy,char * buf)776 static ssize_t show_energy_performance_preference(
777 struct cpufreq_policy *policy, char *buf)
778 {
779 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
780 int preference, raw_epp;
781
782 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
783 if (preference < 0)
784 return preference;
785
786 if (raw_epp)
787 return sprintf(buf, "%d\n", raw_epp);
788 else
789 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
790 }
791
792 cpufreq_freq_attr_rw(energy_performance_preference);
793
show_base_frequency(struct cpufreq_policy * policy,char * buf)794 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
795 {
796 struct cpudata *cpu;
797 u64 cap;
798 int ratio;
799
800 ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
801 if (ratio <= 0) {
802 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
803 ratio = HWP_GUARANTEED_PERF(cap);
804 }
805
806 cpu = all_cpu_data[policy->cpu];
807
808 return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
809 }
810
811 cpufreq_freq_attr_ro(base_frequency);
812
813 static struct freq_attr *hwp_cpufreq_attrs[] = {
814 &energy_performance_preference,
815 &energy_performance_available_preferences,
816 &base_frequency,
817 NULL,
818 };
819
intel_pstate_get_hwp_max(struct cpudata * cpu,int * phy_max,int * current_max)820 static void intel_pstate_get_hwp_max(struct cpudata *cpu, int *phy_max,
821 int *current_max)
822 {
823 u64 cap;
824
825 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
826 WRITE_ONCE(cpu->hwp_cap_cached, cap);
827 if (global.no_turbo || global.turbo_disabled)
828 *current_max = HWP_GUARANTEED_PERF(cap);
829 else
830 *current_max = HWP_HIGHEST_PERF(cap);
831
832 *phy_max = HWP_HIGHEST_PERF(cap);
833 }
834
intel_pstate_hwp_set(unsigned int cpu)835 static void intel_pstate_hwp_set(unsigned int cpu)
836 {
837 struct cpudata *cpu_data = all_cpu_data[cpu];
838 int max, min;
839 u64 value;
840 s16 epp;
841
842 max = cpu_data->max_perf_ratio;
843 min = cpu_data->min_perf_ratio;
844
845 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
846 min = max;
847
848 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
849
850 value &= ~HWP_MIN_PERF(~0L);
851 value |= HWP_MIN_PERF(min);
852
853 value &= ~HWP_MAX_PERF(~0L);
854 value |= HWP_MAX_PERF(max);
855
856 if (cpu_data->epp_policy == cpu_data->policy)
857 goto skip_epp;
858
859 cpu_data->epp_policy = cpu_data->policy;
860
861 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
862 epp = intel_pstate_get_epp(cpu_data, value);
863 cpu_data->epp_powersave = epp;
864 /* If EPP read was failed, then don't try to write */
865 if (epp < 0)
866 goto skip_epp;
867
868 epp = 0;
869 } else {
870 /* skip setting EPP, when saved value is invalid */
871 if (cpu_data->epp_powersave < 0)
872 goto skip_epp;
873
874 /*
875 * No need to restore EPP when it is not zero. This
876 * means:
877 * - Policy is not changed
878 * - user has manually changed
879 * - Error reading EPB
880 */
881 epp = intel_pstate_get_epp(cpu_data, value);
882 if (epp)
883 goto skip_epp;
884
885 epp = cpu_data->epp_powersave;
886 }
887 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
888 value &= ~GENMASK_ULL(31, 24);
889 value |= (u64)epp << 24;
890 } else {
891 intel_pstate_set_epb(cpu, epp);
892 }
893 skip_epp:
894 WRITE_ONCE(cpu_data->hwp_req_cached, value);
895 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
896 }
897
intel_pstate_hwp_offline(struct cpudata * cpu)898 static void intel_pstate_hwp_offline(struct cpudata *cpu)
899 {
900 u64 value = READ_ONCE(cpu->hwp_req_cached);
901 int min_perf;
902
903 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
904 /*
905 * In case the EPP has been set to "performance" by the
906 * active mode "performance" scaling algorithm, replace that
907 * temporary value with the cached EPP one.
908 */
909 value &= ~GENMASK_ULL(31, 24);
910 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
911 WRITE_ONCE(cpu->hwp_req_cached, value);
912 }
913
914 value &= ~GENMASK_ULL(31, 0);
915 min_perf = HWP_LOWEST_PERF(cpu->hwp_cap_cached);
916
917 /* Set hwp_max = hwp_min */
918 value |= HWP_MAX_PERF(min_perf);
919 value |= HWP_MIN_PERF(min_perf);
920
921 /* Set EPP to min */
922 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
923 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
924
925 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
926 }
927
928 #define POWER_CTL_EE_ENABLE 1
929 #define POWER_CTL_EE_DISABLE 2
930
931 static int power_ctl_ee_state;
932
set_power_ctl_ee_state(bool input)933 static void set_power_ctl_ee_state(bool input)
934 {
935 u64 power_ctl;
936
937 mutex_lock(&intel_pstate_driver_lock);
938 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
939 if (input) {
940 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
941 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
942 } else {
943 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
944 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
945 }
946 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
947 mutex_unlock(&intel_pstate_driver_lock);
948 }
949
950 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
951
intel_pstate_hwp_reenable(struct cpudata * cpu)952 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
953 {
954 intel_pstate_hwp_enable(cpu);
955 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
956 }
957
intel_pstate_suspend(struct cpufreq_policy * policy)958 static int intel_pstate_suspend(struct cpufreq_policy *policy)
959 {
960 struct cpudata *cpu = all_cpu_data[policy->cpu];
961
962 pr_debug("CPU %d suspending\n", cpu->cpu);
963
964 cpu->suspended = true;
965
966 return 0;
967 }
968
intel_pstate_resume(struct cpufreq_policy * policy)969 static int intel_pstate_resume(struct cpufreq_policy *policy)
970 {
971 struct cpudata *cpu = all_cpu_data[policy->cpu];
972
973 pr_debug("CPU %d resuming\n", cpu->cpu);
974
975 /* Only restore if the system default is changed */
976 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
977 set_power_ctl_ee_state(true);
978 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
979 set_power_ctl_ee_state(false);
980
981 if (cpu->suspended && hwp_active) {
982 mutex_lock(&intel_pstate_limits_lock);
983
984 /* Re-enable HWP, because "online" has not done that. */
985 intel_pstate_hwp_reenable(cpu);
986
987 mutex_unlock(&intel_pstate_limits_lock);
988 }
989
990 cpu->suspended = false;
991
992 return 0;
993 }
994
intel_pstate_update_policies(void)995 static void intel_pstate_update_policies(void)
996 {
997 int cpu;
998
999 for_each_possible_cpu(cpu)
1000 cpufreq_update_policy(cpu);
1001 }
1002
intel_pstate_update_max_freq(unsigned int cpu)1003 static void intel_pstate_update_max_freq(unsigned int cpu)
1004 {
1005 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1006 struct cpudata *cpudata;
1007
1008 if (!policy)
1009 return;
1010
1011 cpudata = all_cpu_data[cpu];
1012 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1013 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1014
1015 refresh_frequency_limits(policy);
1016
1017 cpufreq_cpu_release(policy);
1018 }
1019
intel_pstate_update_limits(unsigned int cpu)1020 static void intel_pstate_update_limits(unsigned int cpu)
1021 {
1022 mutex_lock(&intel_pstate_driver_lock);
1023
1024 update_turbo_state();
1025 /*
1026 * If turbo has been turned on or off globally, policy limits for
1027 * all CPUs need to be updated to reflect that.
1028 */
1029 if (global.turbo_disabled_mf != global.turbo_disabled) {
1030 global.turbo_disabled_mf = global.turbo_disabled;
1031 arch_set_max_freq_ratio(global.turbo_disabled);
1032 for_each_possible_cpu(cpu)
1033 intel_pstate_update_max_freq(cpu);
1034 } else {
1035 cpufreq_update_policy(cpu);
1036 }
1037
1038 mutex_unlock(&intel_pstate_driver_lock);
1039 }
1040
1041 /************************** sysfs begin ************************/
1042 #define show_one(file_name, object) \
1043 static ssize_t show_##file_name \
1044 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1045 { \
1046 return sprintf(buf, "%u\n", global.object); \
1047 }
1048
1049 static ssize_t intel_pstate_show_status(char *buf);
1050 static int intel_pstate_update_status(const char *buf, size_t size);
1051
show_status(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1052 static ssize_t show_status(struct kobject *kobj,
1053 struct kobj_attribute *attr, char *buf)
1054 {
1055 ssize_t ret;
1056
1057 mutex_lock(&intel_pstate_driver_lock);
1058 ret = intel_pstate_show_status(buf);
1059 mutex_unlock(&intel_pstate_driver_lock);
1060
1061 return ret;
1062 }
1063
store_status(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1064 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1065 const char *buf, size_t count)
1066 {
1067 char *p = memchr(buf, '\n', count);
1068 int ret;
1069
1070 mutex_lock(&intel_pstate_driver_lock);
1071 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1072 mutex_unlock(&intel_pstate_driver_lock);
1073
1074 return ret < 0 ? ret : count;
1075 }
1076
show_turbo_pct(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1077 static ssize_t show_turbo_pct(struct kobject *kobj,
1078 struct kobj_attribute *attr, char *buf)
1079 {
1080 struct cpudata *cpu;
1081 int total, no_turbo, turbo_pct;
1082 uint32_t turbo_fp;
1083
1084 mutex_lock(&intel_pstate_driver_lock);
1085
1086 if (!intel_pstate_driver) {
1087 mutex_unlock(&intel_pstate_driver_lock);
1088 return -EAGAIN;
1089 }
1090
1091 cpu = all_cpu_data[0];
1092
1093 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1094 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1095 turbo_fp = div_fp(no_turbo, total);
1096 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1097
1098 mutex_unlock(&intel_pstate_driver_lock);
1099
1100 return sprintf(buf, "%u\n", turbo_pct);
1101 }
1102
show_num_pstates(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1103 static ssize_t show_num_pstates(struct kobject *kobj,
1104 struct kobj_attribute *attr, char *buf)
1105 {
1106 struct cpudata *cpu;
1107 int total;
1108
1109 mutex_lock(&intel_pstate_driver_lock);
1110
1111 if (!intel_pstate_driver) {
1112 mutex_unlock(&intel_pstate_driver_lock);
1113 return -EAGAIN;
1114 }
1115
1116 cpu = all_cpu_data[0];
1117 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1118
1119 mutex_unlock(&intel_pstate_driver_lock);
1120
1121 return sprintf(buf, "%u\n", total);
1122 }
1123
show_no_turbo(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1124 static ssize_t show_no_turbo(struct kobject *kobj,
1125 struct kobj_attribute *attr, char *buf)
1126 {
1127 ssize_t ret;
1128
1129 mutex_lock(&intel_pstate_driver_lock);
1130
1131 if (!intel_pstate_driver) {
1132 mutex_unlock(&intel_pstate_driver_lock);
1133 return -EAGAIN;
1134 }
1135
1136 update_turbo_state();
1137 if (global.turbo_disabled)
1138 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1139 else
1140 ret = sprintf(buf, "%u\n", global.no_turbo);
1141
1142 mutex_unlock(&intel_pstate_driver_lock);
1143
1144 return ret;
1145 }
1146
store_no_turbo(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1147 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1148 const char *buf, size_t count)
1149 {
1150 unsigned int input;
1151 int ret;
1152
1153 ret = sscanf(buf, "%u", &input);
1154 if (ret != 1)
1155 return -EINVAL;
1156
1157 mutex_lock(&intel_pstate_driver_lock);
1158
1159 if (!intel_pstate_driver) {
1160 mutex_unlock(&intel_pstate_driver_lock);
1161 return -EAGAIN;
1162 }
1163
1164 mutex_lock(&intel_pstate_limits_lock);
1165
1166 update_turbo_state();
1167 if (global.turbo_disabled) {
1168 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1169 mutex_unlock(&intel_pstate_limits_lock);
1170 mutex_unlock(&intel_pstate_driver_lock);
1171 return -EPERM;
1172 }
1173
1174 global.no_turbo = clamp_t(int, input, 0, 1);
1175
1176 if (global.no_turbo) {
1177 struct cpudata *cpu = all_cpu_data[0];
1178 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1179
1180 /* Squash the global minimum into the permitted range. */
1181 if (global.min_perf_pct > pct)
1182 global.min_perf_pct = pct;
1183 }
1184
1185 mutex_unlock(&intel_pstate_limits_lock);
1186
1187 intel_pstate_update_policies();
1188
1189 mutex_unlock(&intel_pstate_driver_lock);
1190
1191 return count;
1192 }
1193
update_qos_request(enum freq_qos_req_type type)1194 static void update_qos_request(enum freq_qos_req_type type)
1195 {
1196 int max_state, turbo_max, freq, i, perf_pct;
1197 struct freq_qos_request *req;
1198 struct cpufreq_policy *policy;
1199
1200 for_each_possible_cpu(i) {
1201 struct cpudata *cpu = all_cpu_data[i];
1202
1203 policy = cpufreq_cpu_get(i);
1204 if (!policy)
1205 continue;
1206
1207 req = policy->driver_data;
1208 cpufreq_cpu_put(policy);
1209
1210 if (!req)
1211 continue;
1212
1213 if (hwp_active)
1214 intel_pstate_get_hwp_max(cpu, &turbo_max, &max_state);
1215 else
1216 turbo_max = cpu->pstate.turbo_pstate;
1217
1218 if (type == FREQ_QOS_MIN) {
1219 perf_pct = global.min_perf_pct;
1220 } else {
1221 req++;
1222 perf_pct = global.max_perf_pct;
1223 }
1224
1225 freq = DIV_ROUND_UP(turbo_max * perf_pct, 100);
1226 freq *= cpu->pstate.scaling;
1227
1228 if (freq_qos_update_request(req, freq) < 0)
1229 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1230 }
1231 }
1232
store_max_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1233 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1234 const char *buf, size_t count)
1235 {
1236 unsigned int input;
1237 int ret;
1238
1239 ret = sscanf(buf, "%u", &input);
1240 if (ret != 1)
1241 return -EINVAL;
1242
1243 mutex_lock(&intel_pstate_driver_lock);
1244
1245 if (!intel_pstate_driver) {
1246 mutex_unlock(&intel_pstate_driver_lock);
1247 return -EAGAIN;
1248 }
1249
1250 mutex_lock(&intel_pstate_limits_lock);
1251
1252 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1253
1254 mutex_unlock(&intel_pstate_limits_lock);
1255
1256 if (intel_pstate_driver == &intel_pstate)
1257 intel_pstate_update_policies();
1258 else
1259 update_qos_request(FREQ_QOS_MAX);
1260
1261 mutex_unlock(&intel_pstate_driver_lock);
1262
1263 return count;
1264 }
1265
store_min_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1266 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1267 const char *buf, size_t count)
1268 {
1269 unsigned int input;
1270 int ret;
1271
1272 ret = sscanf(buf, "%u", &input);
1273 if (ret != 1)
1274 return -EINVAL;
1275
1276 mutex_lock(&intel_pstate_driver_lock);
1277
1278 if (!intel_pstate_driver) {
1279 mutex_unlock(&intel_pstate_driver_lock);
1280 return -EAGAIN;
1281 }
1282
1283 mutex_lock(&intel_pstate_limits_lock);
1284
1285 global.min_perf_pct = clamp_t(int, input,
1286 min_perf_pct_min(), global.max_perf_pct);
1287
1288 mutex_unlock(&intel_pstate_limits_lock);
1289
1290 if (intel_pstate_driver == &intel_pstate)
1291 intel_pstate_update_policies();
1292 else
1293 update_qos_request(FREQ_QOS_MIN);
1294
1295 mutex_unlock(&intel_pstate_driver_lock);
1296
1297 return count;
1298 }
1299
show_hwp_dynamic_boost(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1300 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1301 struct kobj_attribute *attr, char *buf)
1302 {
1303 return sprintf(buf, "%u\n", hwp_boost);
1304 }
1305
store_hwp_dynamic_boost(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1306 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1307 struct kobj_attribute *b,
1308 const char *buf, size_t count)
1309 {
1310 unsigned int input;
1311 int ret;
1312
1313 ret = kstrtouint(buf, 10, &input);
1314 if (ret)
1315 return ret;
1316
1317 mutex_lock(&intel_pstate_driver_lock);
1318 hwp_boost = !!input;
1319 intel_pstate_update_policies();
1320 mutex_unlock(&intel_pstate_driver_lock);
1321
1322 return count;
1323 }
1324
show_energy_efficiency(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1325 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1326 char *buf)
1327 {
1328 u64 power_ctl;
1329 int enable;
1330
1331 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1332 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1333 return sprintf(buf, "%d\n", !enable);
1334 }
1335
store_energy_efficiency(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1336 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1337 const char *buf, size_t count)
1338 {
1339 bool input;
1340 int ret;
1341
1342 ret = kstrtobool(buf, &input);
1343 if (ret)
1344 return ret;
1345
1346 set_power_ctl_ee_state(input);
1347
1348 return count;
1349 }
1350
1351 show_one(max_perf_pct, max_perf_pct);
1352 show_one(min_perf_pct, min_perf_pct);
1353
1354 define_one_global_rw(status);
1355 define_one_global_rw(no_turbo);
1356 define_one_global_rw(max_perf_pct);
1357 define_one_global_rw(min_perf_pct);
1358 define_one_global_ro(turbo_pct);
1359 define_one_global_ro(num_pstates);
1360 define_one_global_rw(hwp_dynamic_boost);
1361 define_one_global_rw(energy_efficiency);
1362
1363 static struct attribute *intel_pstate_attributes[] = {
1364 &status.attr,
1365 &no_turbo.attr,
1366 &turbo_pct.attr,
1367 &num_pstates.attr,
1368 NULL
1369 };
1370
1371 static const struct attribute_group intel_pstate_attr_group = {
1372 .attrs = intel_pstate_attributes,
1373 };
1374
1375 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1376
1377 static struct kobject *intel_pstate_kobject;
1378
intel_pstate_sysfs_expose_params(void)1379 static void __init intel_pstate_sysfs_expose_params(void)
1380 {
1381 int rc;
1382
1383 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1384 &cpu_subsys.dev_root->kobj);
1385 if (WARN_ON(!intel_pstate_kobject))
1386 return;
1387
1388 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1389 if (WARN_ON(rc))
1390 return;
1391
1392 /*
1393 * If per cpu limits are enforced there are no global limits, so
1394 * return without creating max/min_perf_pct attributes
1395 */
1396 if (per_cpu_limits)
1397 return;
1398
1399 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1400 WARN_ON(rc);
1401
1402 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1403 WARN_ON(rc);
1404
1405 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1406 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1407 WARN_ON(rc);
1408 }
1409 }
1410
intel_pstate_sysfs_remove(void)1411 static void __init intel_pstate_sysfs_remove(void)
1412 {
1413 if (!intel_pstate_kobject)
1414 return;
1415
1416 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1417
1418 if (!per_cpu_limits) {
1419 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1420 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1421
1422 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1423 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1424 }
1425
1426 kobject_put(intel_pstate_kobject);
1427 }
1428
intel_pstate_sysfs_expose_hwp_dynamic_boost(void)1429 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1430 {
1431 int rc;
1432
1433 if (!hwp_active)
1434 return;
1435
1436 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1437 WARN_ON_ONCE(rc);
1438 }
1439
intel_pstate_sysfs_hide_hwp_dynamic_boost(void)1440 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1441 {
1442 if (!hwp_active)
1443 return;
1444
1445 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1446 }
1447
1448 /************************** sysfs end ************************/
1449
intel_pstate_hwp_enable(struct cpudata * cpudata)1450 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1451 {
1452 /* First disable HWP notification interrupt as we don't process them */
1453 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1454 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1455
1456 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1457 if (cpudata->epp_default == -EINVAL)
1458 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1459 }
1460
atom_get_min_pstate(void)1461 static int atom_get_min_pstate(void)
1462 {
1463 u64 value;
1464
1465 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1466 return (value >> 8) & 0x7F;
1467 }
1468
atom_get_max_pstate(void)1469 static int atom_get_max_pstate(void)
1470 {
1471 u64 value;
1472
1473 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1474 return (value >> 16) & 0x7F;
1475 }
1476
atom_get_turbo_pstate(void)1477 static int atom_get_turbo_pstate(void)
1478 {
1479 u64 value;
1480
1481 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1482 return value & 0x7F;
1483 }
1484
atom_get_val(struct cpudata * cpudata,int pstate)1485 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1486 {
1487 u64 val;
1488 int32_t vid_fp;
1489 u32 vid;
1490
1491 val = (u64)pstate << 8;
1492 if (global.no_turbo && !global.turbo_disabled)
1493 val |= (u64)1 << 32;
1494
1495 vid_fp = cpudata->vid.min + mul_fp(
1496 int_tofp(pstate - cpudata->pstate.min_pstate),
1497 cpudata->vid.ratio);
1498
1499 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1500 vid = ceiling_fp(vid_fp);
1501
1502 if (pstate > cpudata->pstate.max_pstate)
1503 vid = cpudata->vid.turbo;
1504
1505 return val | vid;
1506 }
1507
silvermont_get_scaling(void)1508 static int silvermont_get_scaling(void)
1509 {
1510 u64 value;
1511 int i;
1512 /* Defined in Table 35-6 from SDM (Sept 2015) */
1513 static int silvermont_freq_table[] = {
1514 83300, 100000, 133300, 116700, 80000};
1515
1516 rdmsrl(MSR_FSB_FREQ, value);
1517 i = value & 0x7;
1518 WARN_ON(i > 4);
1519
1520 return silvermont_freq_table[i];
1521 }
1522
airmont_get_scaling(void)1523 static int airmont_get_scaling(void)
1524 {
1525 u64 value;
1526 int i;
1527 /* Defined in Table 35-10 from SDM (Sept 2015) */
1528 static int airmont_freq_table[] = {
1529 83300, 100000, 133300, 116700, 80000,
1530 93300, 90000, 88900, 87500};
1531
1532 rdmsrl(MSR_FSB_FREQ, value);
1533 i = value & 0xF;
1534 WARN_ON(i > 8);
1535
1536 return airmont_freq_table[i];
1537 }
1538
atom_get_vid(struct cpudata * cpudata)1539 static void atom_get_vid(struct cpudata *cpudata)
1540 {
1541 u64 value;
1542
1543 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1544 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1545 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1546 cpudata->vid.ratio = div_fp(
1547 cpudata->vid.max - cpudata->vid.min,
1548 int_tofp(cpudata->pstate.max_pstate -
1549 cpudata->pstate.min_pstate));
1550
1551 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1552 cpudata->vid.turbo = value & 0x7f;
1553 }
1554
core_get_min_pstate(void)1555 static int core_get_min_pstate(void)
1556 {
1557 u64 value;
1558
1559 rdmsrl(MSR_PLATFORM_INFO, value);
1560 return (value >> 40) & 0xFF;
1561 }
1562
core_get_max_pstate_physical(void)1563 static int core_get_max_pstate_physical(void)
1564 {
1565 u64 value;
1566
1567 rdmsrl(MSR_PLATFORM_INFO, value);
1568 return (value >> 8) & 0xFF;
1569 }
1570
core_get_tdp_ratio(u64 plat_info)1571 static int core_get_tdp_ratio(u64 plat_info)
1572 {
1573 /* Check how many TDP levels present */
1574 if (plat_info & 0x600000000) {
1575 u64 tdp_ctrl;
1576 u64 tdp_ratio;
1577 int tdp_msr;
1578 int err;
1579
1580 /* Get the TDP level (0, 1, 2) to get ratios */
1581 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1582 if (err)
1583 return err;
1584
1585 /* TDP MSR are continuous starting at 0x648 */
1586 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1587 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1588 if (err)
1589 return err;
1590
1591 /* For level 1 and 2, bits[23:16] contain the ratio */
1592 if (tdp_ctrl & 0x03)
1593 tdp_ratio >>= 16;
1594
1595 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1596 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1597
1598 return (int)tdp_ratio;
1599 }
1600
1601 return -ENXIO;
1602 }
1603
core_get_max_pstate(void)1604 static int core_get_max_pstate(void)
1605 {
1606 u64 tar;
1607 u64 plat_info;
1608 int max_pstate;
1609 int tdp_ratio;
1610 int err;
1611
1612 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1613 max_pstate = (plat_info >> 8) & 0xFF;
1614
1615 tdp_ratio = core_get_tdp_ratio(plat_info);
1616 if (tdp_ratio <= 0)
1617 return max_pstate;
1618
1619 if (hwp_active) {
1620 /* Turbo activation ratio is not used on HWP platforms */
1621 return tdp_ratio;
1622 }
1623
1624 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1625 if (!err) {
1626 int tar_levels;
1627
1628 /* Do some sanity checking for safety */
1629 tar_levels = tar & 0xff;
1630 if (tdp_ratio - 1 == tar_levels) {
1631 max_pstate = tar_levels;
1632 pr_debug("max_pstate=TAC %x\n", max_pstate);
1633 }
1634 }
1635
1636 return max_pstate;
1637 }
1638
core_get_turbo_pstate(void)1639 static int core_get_turbo_pstate(void)
1640 {
1641 u64 value;
1642 int nont, ret;
1643
1644 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1645 nont = core_get_max_pstate();
1646 ret = (value) & 255;
1647 if (ret <= nont)
1648 ret = nont;
1649 return ret;
1650 }
1651
core_get_scaling(void)1652 static inline int core_get_scaling(void)
1653 {
1654 return 100000;
1655 }
1656
core_get_val(struct cpudata * cpudata,int pstate)1657 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1658 {
1659 u64 val;
1660
1661 val = (u64)pstate << 8;
1662 if (global.no_turbo && !global.turbo_disabled)
1663 val |= (u64)1 << 32;
1664
1665 return val;
1666 }
1667
knl_get_aperf_mperf_shift(void)1668 static int knl_get_aperf_mperf_shift(void)
1669 {
1670 return 10;
1671 }
1672
knl_get_turbo_pstate(void)1673 static int knl_get_turbo_pstate(void)
1674 {
1675 u64 value;
1676 int nont, ret;
1677
1678 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1679 nont = core_get_max_pstate();
1680 ret = (((value) >> 8) & 0xFF);
1681 if (ret <= nont)
1682 ret = nont;
1683 return ret;
1684 }
1685
intel_pstate_set_pstate(struct cpudata * cpu,int pstate)1686 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1687 {
1688 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1689 cpu->pstate.current_pstate = pstate;
1690 /*
1691 * Generally, there is no guarantee that this code will always run on
1692 * the CPU being updated, so force the register update to run on the
1693 * right CPU.
1694 */
1695 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1696 pstate_funcs.get_val(cpu, pstate));
1697 }
1698
intel_pstate_set_min_pstate(struct cpudata * cpu)1699 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1700 {
1701 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1702 }
1703
intel_pstate_max_within_limits(struct cpudata * cpu)1704 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1705 {
1706 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1707
1708 update_turbo_state();
1709 intel_pstate_set_pstate(cpu, pstate);
1710 }
1711
intel_pstate_get_cpu_pstates(struct cpudata * cpu)1712 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1713 {
1714 cpu->pstate.min_pstate = pstate_funcs.get_min();
1715 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1716 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1717 cpu->pstate.scaling = pstate_funcs.get_scaling();
1718
1719 if (hwp_active && !hwp_mode_bdw) {
1720 unsigned int phy_max, current_max;
1721
1722 intel_pstate_get_hwp_max(cpu, &phy_max, ¤t_max);
1723 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1724 cpu->pstate.turbo_pstate = phy_max;
1725 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(READ_ONCE(cpu->hwp_cap_cached));
1726 } else {
1727 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1728 cpu->pstate.max_pstate = pstate_funcs.get_max();
1729 }
1730 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1731
1732 if (pstate_funcs.get_aperf_mperf_shift)
1733 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1734
1735 if (pstate_funcs.get_vid)
1736 pstate_funcs.get_vid(cpu);
1737
1738 intel_pstate_set_min_pstate(cpu);
1739 }
1740
1741 /*
1742 * Long hold time will keep high perf limits for long time,
1743 * which negatively impacts perf/watt for some workloads,
1744 * like specpower. 3ms is based on experiements on some
1745 * workoads.
1746 */
1747 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1748
intel_pstate_hwp_boost_up(struct cpudata * cpu)1749 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1750 {
1751 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1752 u32 max_limit = (hwp_req & 0xff00) >> 8;
1753 u32 min_limit = (hwp_req & 0xff);
1754 u32 boost_level1;
1755
1756 /*
1757 * Cases to consider (User changes via sysfs or boot time):
1758 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1759 * No boost, return.
1760 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1761 * Should result in one level boost only for P0.
1762 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1763 * Should result in two level boost:
1764 * (min + p1)/2 and P1.
1765 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1766 * Should result in three level boost:
1767 * (min + p1)/2, P1 and P0.
1768 */
1769
1770 /* If max and min are equal or already at max, nothing to boost */
1771 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1772 return;
1773
1774 if (!cpu->hwp_boost_min)
1775 cpu->hwp_boost_min = min_limit;
1776
1777 /* level at half way mark between min and guranteed */
1778 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1779
1780 if (cpu->hwp_boost_min < boost_level1)
1781 cpu->hwp_boost_min = boost_level1;
1782 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1783 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1784 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1785 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1786 cpu->hwp_boost_min = max_limit;
1787 else
1788 return;
1789
1790 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1791 wrmsrl(MSR_HWP_REQUEST, hwp_req);
1792 cpu->last_update = cpu->sample.time;
1793 }
1794
intel_pstate_hwp_boost_down(struct cpudata * cpu)1795 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1796 {
1797 if (cpu->hwp_boost_min) {
1798 bool expired;
1799
1800 /* Check if we are idle for hold time to boost down */
1801 expired = time_after64(cpu->sample.time, cpu->last_update +
1802 hwp_boost_hold_time_ns);
1803 if (expired) {
1804 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1805 cpu->hwp_boost_min = 0;
1806 }
1807 }
1808 cpu->last_update = cpu->sample.time;
1809 }
1810
intel_pstate_update_util_hwp_local(struct cpudata * cpu,u64 time)1811 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1812 u64 time)
1813 {
1814 cpu->sample.time = time;
1815
1816 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1817 bool do_io = false;
1818
1819 cpu->sched_flags = 0;
1820 /*
1821 * Set iowait_boost flag and update time. Since IO WAIT flag
1822 * is set all the time, we can't just conclude that there is
1823 * some IO bound activity is scheduled on this CPU with just
1824 * one occurrence. If we receive at least two in two
1825 * consecutive ticks, then we treat as boost candidate.
1826 */
1827 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1828 do_io = true;
1829
1830 cpu->last_io_update = time;
1831
1832 if (do_io)
1833 intel_pstate_hwp_boost_up(cpu);
1834
1835 } else {
1836 intel_pstate_hwp_boost_down(cpu);
1837 }
1838 }
1839
intel_pstate_update_util_hwp(struct update_util_data * data,u64 time,unsigned int flags)1840 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1841 u64 time, unsigned int flags)
1842 {
1843 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1844
1845 cpu->sched_flags |= flags;
1846
1847 if (smp_processor_id() == cpu->cpu)
1848 intel_pstate_update_util_hwp_local(cpu, time);
1849 }
1850
intel_pstate_calc_avg_perf(struct cpudata * cpu)1851 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1852 {
1853 struct sample *sample = &cpu->sample;
1854
1855 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1856 }
1857
intel_pstate_sample(struct cpudata * cpu,u64 time)1858 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1859 {
1860 u64 aperf, mperf;
1861 unsigned long flags;
1862 u64 tsc;
1863
1864 local_irq_save(flags);
1865 rdmsrl(MSR_IA32_APERF, aperf);
1866 rdmsrl(MSR_IA32_MPERF, mperf);
1867 tsc = rdtsc();
1868 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1869 local_irq_restore(flags);
1870 return false;
1871 }
1872 local_irq_restore(flags);
1873
1874 cpu->last_sample_time = cpu->sample.time;
1875 cpu->sample.time = time;
1876 cpu->sample.aperf = aperf;
1877 cpu->sample.mperf = mperf;
1878 cpu->sample.tsc = tsc;
1879 cpu->sample.aperf -= cpu->prev_aperf;
1880 cpu->sample.mperf -= cpu->prev_mperf;
1881 cpu->sample.tsc -= cpu->prev_tsc;
1882
1883 cpu->prev_aperf = aperf;
1884 cpu->prev_mperf = mperf;
1885 cpu->prev_tsc = tsc;
1886 /*
1887 * First time this function is invoked in a given cycle, all of the
1888 * previous sample data fields are equal to zero or stale and they must
1889 * be populated with meaningful numbers for things to work, so assume
1890 * that sample.time will always be reset before setting the utilization
1891 * update hook and make the caller skip the sample then.
1892 */
1893 if (cpu->last_sample_time) {
1894 intel_pstate_calc_avg_perf(cpu);
1895 return true;
1896 }
1897 return false;
1898 }
1899
get_avg_frequency(struct cpudata * cpu)1900 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1901 {
1902 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1903 }
1904
get_avg_pstate(struct cpudata * cpu)1905 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1906 {
1907 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1908 cpu->sample.core_avg_perf);
1909 }
1910
get_target_pstate(struct cpudata * cpu)1911 static inline int32_t get_target_pstate(struct cpudata *cpu)
1912 {
1913 struct sample *sample = &cpu->sample;
1914 int32_t busy_frac;
1915 int target, avg_pstate;
1916
1917 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1918 sample->tsc);
1919
1920 if (busy_frac < cpu->iowait_boost)
1921 busy_frac = cpu->iowait_boost;
1922
1923 sample->busy_scaled = busy_frac * 100;
1924
1925 target = global.no_turbo || global.turbo_disabled ?
1926 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1927 target += target >> 2;
1928 target = mul_fp(target, busy_frac);
1929 if (target < cpu->pstate.min_pstate)
1930 target = cpu->pstate.min_pstate;
1931
1932 /*
1933 * If the average P-state during the previous cycle was higher than the
1934 * current target, add 50% of the difference to the target to reduce
1935 * possible performance oscillations and offset possible performance
1936 * loss related to moving the workload from one CPU to another within
1937 * a package/module.
1938 */
1939 avg_pstate = get_avg_pstate(cpu);
1940 if (avg_pstate > target)
1941 target += (avg_pstate - target) >> 1;
1942
1943 return target;
1944 }
1945
intel_pstate_prepare_request(struct cpudata * cpu,int pstate)1946 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1947 {
1948 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1949 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
1950
1951 return clamp_t(int, pstate, min_pstate, max_pstate);
1952 }
1953
intel_pstate_update_pstate(struct cpudata * cpu,int pstate)1954 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1955 {
1956 if (pstate == cpu->pstate.current_pstate)
1957 return;
1958
1959 cpu->pstate.current_pstate = pstate;
1960 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1961 }
1962
intel_pstate_adjust_pstate(struct cpudata * cpu)1963 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1964 {
1965 int from = cpu->pstate.current_pstate;
1966 struct sample *sample;
1967 int target_pstate;
1968
1969 update_turbo_state();
1970
1971 target_pstate = get_target_pstate(cpu);
1972 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1973 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1974 intel_pstate_update_pstate(cpu, target_pstate);
1975
1976 sample = &cpu->sample;
1977 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1978 fp_toint(sample->busy_scaled),
1979 from,
1980 cpu->pstate.current_pstate,
1981 sample->mperf,
1982 sample->aperf,
1983 sample->tsc,
1984 get_avg_frequency(cpu),
1985 fp_toint(cpu->iowait_boost * 100));
1986 }
1987
intel_pstate_update_util(struct update_util_data * data,u64 time,unsigned int flags)1988 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1989 unsigned int flags)
1990 {
1991 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1992 u64 delta_ns;
1993
1994 /* Don't allow remote callbacks */
1995 if (smp_processor_id() != cpu->cpu)
1996 return;
1997
1998 delta_ns = time - cpu->last_update;
1999 if (flags & SCHED_CPUFREQ_IOWAIT) {
2000 /* Start over if the CPU may have been idle. */
2001 if (delta_ns > TICK_NSEC) {
2002 cpu->iowait_boost = ONE_EIGHTH_FP;
2003 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2004 cpu->iowait_boost <<= 1;
2005 if (cpu->iowait_boost > int_tofp(1))
2006 cpu->iowait_boost = int_tofp(1);
2007 } else {
2008 cpu->iowait_boost = ONE_EIGHTH_FP;
2009 }
2010 } else if (cpu->iowait_boost) {
2011 /* Clear iowait_boost if the CPU may have been idle. */
2012 if (delta_ns > TICK_NSEC)
2013 cpu->iowait_boost = 0;
2014 else
2015 cpu->iowait_boost >>= 1;
2016 }
2017 cpu->last_update = time;
2018 delta_ns = time - cpu->sample.time;
2019 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2020 return;
2021
2022 if (intel_pstate_sample(cpu, time))
2023 intel_pstate_adjust_pstate(cpu);
2024 }
2025
2026 static struct pstate_funcs core_funcs = {
2027 .get_max = core_get_max_pstate,
2028 .get_max_physical = core_get_max_pstate_physical,
2029 .get_min = core_get_min_pstate,
2030 .get_turbo = core_get_turbo_pstate,
2031 .get_scaling = core_get_scaling,
2032 .get_val = core_get_val,
2033 };
2034
2035 static const struct pstate_funcs silvermont_funcs = {
2036 .get_max = atom_get_max_pstate,
2037 .get_max_physical = atom_get_max_pstate,
2038 .get_min = atom_get_min_pstate,
2039 .get_turbo = atom_get_turbo_pstate,
2040 .get_val = atom_get_val,
2041 .get_scaling = silvermont_get_scaling,
2042 .get_vid = atom_get_vid,
2043 };
2044
2045 static const struct pstate_funcs airmont_funcs = {
2046 .get_max = atom_get_max_pstate,
2047 .get_max_physical = atom_get_max_pstate,
2048 .get_min = atom_get_min_pstate,
2049 .get_turbo = atom_get_turbo_pstate,
2050 .get_val = atom_get_val,
2051 .get_scaling = airmont_get_scaling,
2052 .get_vid = atom_get_vid,
2053 };
2054
2055 static const struct pstate_funcs knl_funcs = {
2056 .get_max = core_get_max_pstate,
2057 .get_max_physical = core_get_max_pstate_physical,
2058 .get_min = core_get_min_pstate,
2059 .get_turbo = knl_get_turbo_pstate,
2060 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2061 .get_scaling = core_get_scaling,
2062 .get_val = core_get_val,
2063 };
2064
2065 #define X86_MATCH(model, policy) \
2066 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2067 X86_FEATURE_APERFMPERF, &policy)
2068
2069 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2070 X86_MATCH(SANDYBRIDGE, core_funcs),
2071 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2072 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2073 X86_MATCH(IVYBRIDGE, core_funcs),
2074 X86_MATCH(HASWELL, core_funcs),
2075 X86_MATCH(BROADWELL, core_funcs),
2076 X86_MATCH(IVYBRIDGE_X, core_funcs),
2077 X86_MATCH(HASWELL_X, core_funcs),
2078 X86_MATCH(HASWELL_L, core_funcs),
2079 X86_MATCH(HASWELL_G, core_funcs),
2080 X86_MATCH(BROADWELL_G, core_funcs),
2081 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2082 X86_MATCH(SKYLAKE_L, core_funcs),
2083 X86_MATCH(BROADWELL_X, core_funcs),
2084 X86_MATCH(SKYLAKE, core_funcs),
2085 X86_MATCH(BROADWELL_D, core_funcs),
2086 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2087 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2088 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2089 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2090 X86_MATCH(SKYLAKE_X, core_funcs),
2091 {}
2092 };
2093 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2094
2095 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2096 X86_MATCH(BROADWELL_D, core_funcs),
2097 X86_MATCH(BROADWELL_X, core_funcs),
2098 X86_MATCH(SKYLAKE_X, core_funcs),
2099 {}
2100 };
2101
2102 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2103 X86_MATCH(KABYLAKE, core_funcs),
2104 {}
2105 };
2106
2107 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
2108 X86_MATCH(SKYLAKE_X, core_funcs),
2109 X86_MATCH(SKYLAKE, core_funcs),
2110 {}
2111 };
2112
intel_pstate_init_cpu(unsigned int cpunum)2113 static int intel_pstate_init_cpu(unsigned int cpunum)
2114 {
2115 struct cpudata *cpu;
2116
2117 cpu = all_cpu_data[cpunum];
2118
2119 if (!cpu) {
2120 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2121 if (!cpu)
2122 return -ENOMEM;
2123
2124 all_cpu_data[cpunum] = cpu;
2125
2126 cpu->cpu = cpunum;
2127
2128 cpu->epp_default = -EINVAL;
2129
2130 if (hwp_active) {
2131 const struct x86_cpu_id *id;
2132
2133 intel_pstate_hwp_enable(cpu);
2134
2135 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
2136 if (id && intel_pstate_acpi_pm_profile_server())
2137 hwp_boost = true;
2138 }
2139 } else if (hwp_active) {
2140 /*
2141 * Re-enable HWP in case this happens after a resume from ACPI
2142 * S3 if the CPU was offline during the whole system/resume
2143 * cycle.
2144 */
2145 intel_pstate_hwp_reenable(cpu);
2146 }
2147
2148 cpu->epp_powersave = -EINVAL;
2149 cpu->epp_policy = 0;
2150
2151 intel_pstate_get_cpu_pstates(cpu);
2152
2153 pr_debug("controlling: cpu %d\n", cpunum);
2154
2155 return 0;
2156 }
2157
intel_pstate_set_update_util_hook(unsigned int cpu_num)2158 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2159 {
2160 struct cpudata *cpu = all_cpu_data[cpu_num];
2161
2162 if (hwp_active && !hwp_boost)
2163 return;
2164
2165 if (cpu->update_util_set)
2166 return;
2167
2168 /* Prevent intel_pstate_update_util() from using stale data. */
2169 cpu->sample.time = 0;
2170 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2171 (hwp_active ?
2172 intel_pstate_update_util_hwp :
2173 intel_pstate_update_util));
2174 cpu->update_util_set = true;
2175 }
2176
intel_pstate_clear_update_util_hook(unsigned int cpu)2177 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2178 {
2179 struct cpudata *cpu_data = all_cpu_data[cpu];
2180
2181 if (!cpu_data->update_util_set)
2182 return;
2183
2184 cpufreq_remove_update_util_hook(cpu);
2185 cpu_data->update_util_set = false;
2186 synchronize_rcu();
2187 }
2188
intel_pstate_get_max_freq(struct cpudata * cpu)2189 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2190 {
2191 return global.turbo_disabled || global.no_turbo ?
2192 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2193 }
2194
intel_pstate_update_perf_limits(struct cpudata * cpu,unsigned int policy_min,unsigned int policy_max)2195 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2196 unsigned int policy_min,
2197 unsigned int policy_max)
2198 {
2199 int32_t max_policy_perf, min_policy_perf;
2200 int max_state, turbo_max;
2201 int max_freq;
2202
2203 /*
2204 * HWP needs some special consideration, because on BDX the
2205 * HWP_REQUEST uses abstract value to represent performance
2206 * rather than pure ratios.
2207 */
2208 if (hwp_active) {
2209 intel_pstate_get_hwp_max(cpu, &turbo_max, &max_state);
2210 } else {
2211 max_state = global.no_turbo || global.turbo_disabled ?
2212 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2213 turbo_max = cpu->pstate.turbo_pstate;
2214 }
2215 max_freq = max_state * cpu->pstate.scaling;
2216
2217 max_policy_perf = max_state * policy_max / max_freq;
2218 if (policy_max == policy_min) {
2219 min_policy_perf = max_policy_perf;
2220 } else {
2221 min_policy_perf = max_state * policy_min / max_freq;
2222 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2223 0, max_policy_perf);
2224 }
2225
2226 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
2227 cpu->cpu, max_state, min_policy_perf, max_policy_perf);
2228
2229 /* Normalize user input to [min_perf, max_perf] */
2230 if (per_cpu_limits) {
2231 cpu->min_perf_ratio = min_policy_perf;
2232 cpu->max_perf_ratio = max_policy_perf;
2233 } else {
2234 int32_t global_min, global_max;
2235
2236 /* Global limits are in percent of the maximum turbo P-state. */
2237 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2238 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2239 global_min = clamp_t(int32_t, global_min, 0, global_max);
2240
2241 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2242 global_min, global_max);
2243
2244 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2245 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2246 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2247 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2248
2249 /* Make sure min_perf <= max_perf */
2250 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2251 cpu->max_perf_ratio);
2252
2253 }
2254 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2255 cpu->max_perf_ratio,
2256 cpu->min_perf_ratio);
2257 }
2258
intel_pstate_set_policy(struct cpufreq_policy * policy)2259 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2260 {
2261 struct cpudata *cpu;
2262
2263 if (!policy->cpuinfo.max_freq)
2264 return -ENODEV;
2265
2266 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2267 policy->cpuinfo.max_freq, policy->max);
2268
2269 cpu = all_cpu_data[policy->cpu];
2270 cpu->policy = policy->policy;
2271
2272 mutex_lock(&intel_pstate_limits_lock);
2273
2274 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2275
2276 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2277 /*
2278 * NOHZ_FULL CPUs need this as the governor callback may not
2279 * be invoked on them.
2280 */
2281 intel_pstate_clear_update_util_hook(policy->cpu);
2282 intel_pstate_max_within_limits(cpu);
2283 } else {
2284 intel_pstate_set_update_util_hook(policy->cpu);
2285 }
2286
2287 if (hwp_active) {
2288 /*
2289 * When hwp_boost was active before and dynamically it
2290 * was turned off, in that case we need to clear the
2291 * update util hook.
2292 */
2293 if (!hwp_boost)
2294 intel_pstate_clear_update_util_hook(policy->cpu);
2295 intel_pstate_hwp_set(policy->cpu);
2296 }
2297
2298 mutex_unlock(&intel_pstate_limits_lock);
2299
2300 return 0;
2301 }
2302
intel_pstate_adjust_policy_max(struct cpudata * cpu,struct cpufreq_policy_data * policy)2303 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2304 struct cpufreq_policy_data *policy)
2305 {
2306 if (!hwp_active &&
2307 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2308 policy->max < policy->cpuinfo.max_freq &&
2309 policy->max > cpu->pstate.max_freq) {
2310 pr_debug("policy->max > max non turbo frequency\n");
2311 policy->max = policy->cpuinfo.max_freq;
2312 }
2313 }
2314
intel_pstate_verify_cpu_policy(struct cpudata * cpu,struct cpufreq_policy_data * policy)2315 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2316 struct cpufreq_policy_data *policy)
2317 {
2318 int max_freq;
2319
2320 update_turbo_state();
2321 if (hwp_active) {
2322 int max_state, turbo_max;
2323
2324 intel_pstate_get_hwp_max(cpu, &turbo_max, &max_state);
2325 max_freq = max_state * cpu->pstate.scaling;
2326 } else {
2327 max_freq = intel_pstate_get_max_freq(cpu);
2328 }
2329 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2330
2331 intel_pstate_adjust_policy_max(cpu, policy);
2332 }
2333
intel_pstate_verify_policy(struct cpufreq_policy_data * policy)2334 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2335 {
2336 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2337
2338 return 0;
2339 }
2340
intel_pstate_cpu_offline(struct cpufreq_policy * policy)2341 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2342 {
2343 struct cpudata *cpu = all_cpu_data[policy->cpu];
2344
2345 pr_debug("CPU %d going offline\n", cpu->cpu);
2346
2347 if (cpu->suspended)
2348 return 0;
2349
2350 /*
2351 * If the CPU is an SMT thread and it goes offline with the performance
2352 * settings different from the minimum, it will prevent its sibling
2353 * from getting to lower performance levels, so force the minimum
2354 * performance on CPU offline to prevent that from happening.
2355 */
2356 if (hwp_active)
2357 intel_pstate_hwp_offline(cpu);
2358 else
2359 intel_pstate_set_min_pstate(cpu);
2360
2361 intel_pstate_exit_perf_limits(policy);
2362
2363 return 0;
2364 }
2365
intel_pstate_cpu_online(struct cpufreq_policy * policy)2366 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2367 {
2368 struct cpudata *cpu = all_cpu_data[policy->cpu];
2369
2370 pr_debug("CPU %d going online\n", cpu->cpu);
2371
2372 intel_pstate_init_acpi_perf_limits(policy);
2373
2374 if (hwp_active) {
2375 /*
2376 * Re-enable HWP and clear the "suspended" flag to let "resume"
2377 * know that it need not do that.
2378 */
2379 intel_pstate_hwp_reenable(cpu);
2380 cpu->suspended = false;
2381 }
2382
2383 return 0;
2384 }
2385
intel_pstate_stop_cpu(struct cpufreq_policy * policy)2386 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2387 {
2388 pr_debug("CPU %d stopping\n", policy->cpu);
2389
2390 intel_pstate_clear_update_util_hook(policy->cpu);
2391 }
2392
intel_pstate_cpu_exit(struct cpufreq_policy * policy)2393 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2394 {
2395 pr_debug("CPU %d exiting\n", policy->cpu);
2396
2397 policy->fast_switch_possible = false;
2398
2399 return 0;
2400 }
2401
__intel_pstate_cpu_init(struct cpufreq_policy * policy)2402 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2403 {
2404 struct cpudata *cpu;
2405 int rc;
2406
2407 rc = intel_pstate_init_cpu(policy->cpu);
2408 if (rc)
2409 return rc;
2410
2411 cpu = all_cpu_data[policy->cpu];
2412
2413 cpu->max_perf_ratio = 0xFF;
2414 cpu->min_perf_ratio = 0;
2415
2416 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2417 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2418
2419 /* cpuinfo and default policy values */
2420 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2421 update_turbo_state();
2422 global.turbo_disabled_mf = global.turbo_disabled;
2423 policy->cpuinfo.max_freq = global.turbo_disabled ?
2424 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2425 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2426
2427 if (hwp_active) {
2428 unsigned int max_freq;
2429
2430 max_freq = global.turbo_disabled ?
2431 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2432 if (max_freq < policy->cpuinfo.max_freq)
2433 policy->cpuinfo.max_freq = max_freq;
2434 }
2435
2436 intel_pstate_init_acpi_perf_limits(policy);
2437
2438 policy->fast_switch_possible = true;
2439
2440 return 0;
2441 }
2442
intel_pstate_cpu_init(struct cpufreq_policy * policy)2443 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2444 {
2445 int ret = __intel_pstate_cpu_init(policy);
2446
2447 if (ret)
2448 return ret;
2449
2450 /*
2451 * Set the policy to powersave to provide a valid fallback value in case
2452 * the default cpufreq governor is neither powersave nor performance.
2453 */
2454 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2455
2456 if (hwp_active) {
2457 struct cpudata *cpu = all_cpu_data[policy->cpu];
2458
2459 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2460 }
2461
2462 return 0;
2463 }
2464
2465 static struct cpufreq_driver intel_pstate = {
2466 .flags = CPUFREQ_CONST_LOOPS,
2467 .verify = intel_pstate_verify_policy,
2468 .setpolicy = intel_pstate_set_policy,
2469 .suspend = intel_pstate_suspend,
2470 .resume = intel_pstate_resume,
2471 .init = intel_pstate_cpu_init,
2472 .exit = intel_pstate_cpu_exit,
2473 .stop_cpu = intel_pstate_stop_cpu,
2474 .offline = intel_pstate_cpu_offline,
2475 .online = intel_pstate_cpu_online,
2476 .update_limits = intel_pstate_update_limits,
2477 .name = "intel_pstate",
2478 };
2479
intel_cpufreq_verify_policy(struct cpufreq_policy_data * policy)2480 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2481 {
2482 struct cpudata *cpu = all_cpu_data[policy->cpu];
2483
2484 intel_pstate_verify_cpu_policy(cpu, policy);
2485 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2486
2487 return 0;
2488 }
2489
2490 /* Use of trace in passive mode:
2491 *
2492 * In passive mode the trace core_busy field (also known as the
2493 * performance field, and lablelled as such on the graphs; also known as
2494 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2495 * driver call was via the normal or fast switch path. Various graphs
2496 * output from the intel_pstate_tracer.py utility that include core_busy
2497 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2498 * so we use 10 to indicate the the normal path through the driver, and
2499 * 90 to indicate the fast switch path through the driver.
2500 * The scaled_busy field is not used, and is set to 0.
2501 */
2502
2503 #define INTEL_PSTATE_TRACE_TARGET 10
2504 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2505
intel_cpufreq_trace(struct cpudata * cpu,unsigned int trace_type,int old_pstate)2506 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2507 {
2508 struct sample *sample;
2509
2510 if (!trace_pstate_sample_enabled())
2511 return;
2512
2513 if (!intel_pstate_sample(cpu, ktime_get()))
2514 return;
2515
2516 sample = &cpu->sample;
2517 trace_pstate_sample(trace_type,
2518 0,
2519 old_pstate,
2520 cpu->pstate.current_pstate,
2521 sample->mperf,
2522 sample->aperf,
2523 sample->tsc,
2524 get_avg_frequency(cpu),
2525 fp_toint(cpu->iowait_boost * 100));
2526 }
2527
intel_cpufreq_adjust_hwp(struct cpudata * cpu,u32 target_pstate,bool strict,bool fast_switch)2528 static void intel_cpufreq_adjust_hwp(struct cpudata *cpu, u32 target_pstate,
2529 bool strict, bool fast_switch)
2530 {
2531 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2532
2533 value &= ~HWP_MIN_PERF(~0L);
2534 value |= HWP_MIN_PERF(target_pstate);
2535
2536 /*
2537 * The entire MSR needs to be updated in order to update the HWP min
2538 * field in it, so opportunistically update the max too if needed.
2539 */
2540 value &= ~HWP_MAX_PERF(~0L);
2541 value |= HWP_MAX_PERF(strict ? target_pstate : cpu->max_perf_ratio);
2542
2543 if (value == prev)
2544 return;
2545
2546 WRITE_ONCE(cpu->hwp_req_cached, value);
2547 if (fast_switch)
2548 wrmsrl(MSR_HWP_REQUEST, value);
2549 else
2550 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2551 }
2552
intel_cpufreq_adjust_perf_ctl(struct cpudata * cpu,u32 target_pstate,bool fast_switch)2553 static void intel_cpufreq_adjust_perf_ctl(struct cpudata *cpu,
2554 u32 target_pstate, bool fast_switch)
2555 {
2556 if (fast_switch)
2557 wrmsrl(MSR_IA32_PERF_CTL,
2558 pstate_funcs.get_val(cpu, target_pstate));
2559 else
2560 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2561 pstate_funcs.get_val(cpu, target_pstate));
2562 }
2563
intel_cpufreq_update_pstate(struct cpufreq_policy * policy,int target_pstate,bool fast_switch)2564 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2565 int target_pstate, bool fast_switch)
2566 {
2567 struct cpudata *cpu = all_cpu_data[policy->cpu];
2568 int old_pstate = cpu->pstate.current_pstate;
2569
2570 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2571 if (hwp_active) {
2572 intel_cpufreq_adjust_hwp(cpu, target_pstate,
2573 policy->strict_target, fast_switch);
2574 cpu->pstate.current_pstate = target_pstate;
2575 } else if (target_pstate != old_pstate) {
2576 intel_cpufreq_adjust_perf_ctl(cpu, target_pstate, fast_switch);
2577 cpu->pstate.current_pstate = target_pstate;
2578 }
2579
2580 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2581 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2582
2583 return target_pstate;
2584 }
2585
intel_cpufreq_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)2586 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2587 unsigned int target_freq,
2588 unsigned int relation)
2589 {
2590 struct cpudata *cpu = all_cpu_data[policy->cpu];
2591 struct cpufreq_freqs freqs;
2592 int target_pstate;
2593
2594 update_turbo_state();
2595
2596 freqs.old = policy->cur;
2597 freqs.new = target_freq;
2598
2599 cpufreq_freq_transition_begin(policy, &freqs);
2600
2601 switch (relation) {
2602 case CPUFREQ_RELATION_L:
2603 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2604 break;
2605 case CPUFREQ_RELATION_H:
2606 target_pstate = freqs.new / cpu->pstate.scaling;
2607 break;
2608 default:
2609 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2610 break;
2611 }
2612
2613 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2614
2615 freqs.new = target_pstate * cpu->pstate.scaling;
2616
2617 cpufreq_freq_transition_end(policy, &freqs, false);
2618
2619 return 0;
2620 }
2621
intel_cpufreq_fast_switch(struct cpufreq_policy * policy,unsigned int target_freq)2622 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2623 unsigned int target_freq)
2624 {
2625 struct cpudata *cpu = all_cpu_data[policy->cpu];
2626 int target_pstate;
2627
2628 update_turbo_state();
2629
2630 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2631
2632 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2633
2634 return target_pstate * cpu->pstate.scaling;
2635 }
2636
intel_cpufreq_cpu_init(struct cpufreq_policy * policy)2637 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2638 {
2639 int max_state, turbo_max, min_freq, max_freq, ret;
2640 struct freq_qos_request *req;
2641 struct cpudata *cpu;
2642 struct device *dev;
2643
2644 dev = get_cpu_device(policy->cpu);
2645 if (!dev)
2646 return -ENODEV;
2647
2648 ret = __intel_pstate_cpu_init(policy);
2649 if (ret)
2650 return ret;
2651
2652 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2653 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2654 policy->cur = policy->cpuinfo.min_freq;
2655
2656 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
2657 if (!req) {
2658 ret = -ENOMEM;
2659 goto pstate_exit;
2660 }
2661
2662 cpu = all_cpu_data[policy->cpu];
2663
2664 if (hwp_active) {
2665 u64 value;
2666
2667 intel_pstate_get_hwp_max(cpu, &turbo_max, &max_state);
2668 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
2669 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
2670 WRITE_ONCE(cpu->hwp_req_cached, value);
2671 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
2672 } else {
2673 turbo_max = cpu->pstate.turbo_pstate;
2674 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2675 }
2676
2677 min_freq = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2678 min_freq *= cpu->pstate.scaling;
2679 max_freq = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2680 max_freq *= cpu->pstate.scaling;
2681
2682 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
2683 min_freq);
2684 if (ret < 0) {
2685 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
2686 goto free_req;
2687 }
2688
2689 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
2690 max_freq);
2691 if (ret < 0) {
2692 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
2693 goto remove_min_req;
2694 }
2695
2696 policy->driver_data = req;
2697
2698 return 0;
2699
2700 remove_min_req:
2701 freq_qos_remove_request(req);
2702 free_req:
2703 kfree(req);
2704 pstate_exit:
2705 intel_pstate_exit_perf_limits(policy);
2706
2707 return ret;
2708 }
2709
intel_cpufreq_cpu_exit(struct cpufreq_policy * policy)2710 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
2711 {
2712 struct freq_qos_request *req;
2713
2714 req = policy->driver_data;
2715
2716 freq_qos_remove_request(req + 1);
2717 freq_qos_remove_request(req);
2718 kfree(req);
2719
2720 return intel_pstate_cpu_exit(policy);
2721 }
2722
2723 static struct cpufreq_driver intel_cpufreq = {
2724 .flags = CPUFREQ_CONST_LOOPS,
2725 .verify = intel_cpufreq_verify_policy,
2726 .target = intel_cpufreq_target,
2727 .fast_switch = intel_cpufreq_fast_switch,
2728 .init = intel_cpufreq_cpu_init,
2729 .exit = intel_cpufreq_cpu_exit,
2730 .offline = intel_pstate_cpu_offline,
2731 .online = intel_pstate_cpu_online,
2732 .suspend = intel_pstate_suspend,
2733 .resume = intel_pstate_resume,
2734 .update_limits = intel_pstate_update_limits,
2735 .name = "intel_cpufreq",
2736 };
2737
2738 static struct cpufreq_driver *default_driver;
2739
intel_pstate_driver_cleanup(void)2740 static void intel_pstate_driver_cleanup(void)
2741 {
2742 unsigned int cpu;
2743
2744 get_online_cpus();
2745 for_each_online_cpu(cpu) {
2746 if (all_cpu_data[cpu]) {
2747 if (intel_pstate_driver == &intel_pstate)
2748 intel_pstate_clear_update_util_hook(cpu);
2749
2750 kfree(all_cpu_data[cpu]);
2751 all_cpu_data[cpu] = NULL;
2752 }
2753 }
2754 put_online_cpus();
2755
2756 intel_pstate_driver = NULL;
2757 }
2758
intel_pstate_register_driver(struct cpufreq_driver * driver)2759 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2760 {
2761 int ret;
2762
2763 if (driver == &intel_pstate)
2764 intel_pstate_sysfs_expose_hwp_dynamic_boost();
2765
2766 memset(&global, 0, sizeof(global));
2767 global.max_perf_pct = 100;
2768
2769 intel_pstate_driver = driver;
2770 ret = cpufreq_register_driver(intel_pstate_driver);
2771 if (ret) {
2772 intel_pstate_driver_cleanup();
2773 return ret;
2774 }
2775
2776 global.min_perf_pct = min_perf_pct_min();
2777
2778 return 0;
2779 }
2780
intel_pstate_show_status(char * buf)2781 static ssize_t intel_pstate_show_status(char *buf)
2782 {
2783 if (!intel_pstate_driver)
2784 return sprintf(buf, "off\n");
2785
2786 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2787 "active" : "passive");
2788 }
2789
intel_pstate_update_status(const char * buf,size_t size)2790 static int intel_pstate_update_status(const char *buf, size_t size)
2791 {
2792 if (size == 3 && !strncmp(buf, "off", size)) {
2793 if (!intel_pstate_driver)
2794 return -EINVAL;
2795
2796 if (hwp_active)
2797 return -EBUSY;
2798
2799 cpufreq_unregister_driver(intel_pstate_driver);
2800 intel_pstate_driver_cleanup();
2801 return 0;
2802 }
2803
2804 if (size == 6 && !strncmp(buf, "active", size)) {
2805 if (intel_pstate_driver) {
2806 if (intel_pstate_driver == &intel_pstate)
2807 return 0;
2808
2809 cpufreq_unregister_driver(intel_pstate_driver);
2810 }
2811
2812 return intel_pstate_register_driver(&intel_pstate);
2813 }
2814
2815 if (size == 7 && !strncmp(buf, "passive", size)) {
2816 if (intel_pstate_driver) {
2817 if (intel_pstate_driver == &intel_cpufreq)
2818 return 0;
2819
2820 cpufreq_unregister_driver(intel_pstate_driver);
2821 intel_pstate_sysfs_hide_hwp_dynamic_boost();
2822 }
2823
2824 return intel_pstate_register_driver(&intel_cpufreq);
2825 }
2826
2827 return -EINVAL;
2828 }
2829
2830 static int no_load __initdata;
2831 static int no_hwp __initdata;
2832 static int hwp_only __initdata;
2833 static unsigned int force_load __initdata;
2834
intel_pstate_msrs_not_valid(void)2835 static int __init intel_pstate_msrs_not_valid(void)
2836 {
2837 if (!pstate_funcs.get_max() ||
2838 !pstate_funcs.get_min() ||
2839 !pstate_funcs.get_turbo())
2840 return -ENODEV;
2841
2842 return 0;
2843 }
2844
copy_cpu_funcs(struct pstate_funcs * funcs)2845 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2846 {
2847 pstate_funcs.get_max = funcs->get_max;
2848 pstate_funcs.get_max_physical = funcs->get_max_physical;
2849 pstate_funcs.get_min = funcs->get_min;
2850 pstate_funcs.get_turbo = funcs->get_turbo;
2851 pstate_funcs.get_scaling = funcs->get_scaling;
2852 pstate_funcs.get_val = funcs->get_val;
2853 pstate_funcs.get_vid = funcs->get_vid;
2854 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2855 }
2856
2857 #ifdef CONFIG_ACPI
2858
intel_pstate_no_acpi_pss(void)2859 static bool __init intel_pstate_no_acpi_pss(void)
2860 {
2861 int i;
2862
2863 for_each_possible_cpu(i) {
2864 acpi_status status;
2865 union acpi_object *pss;
2866 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2867 struct acpi_processor *pr = per_cpu(processors, i);
2868
2869 if (!pr)
2870 continue;
2871
2872 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2873 if (ACPI_FAILURE(status))
2874 continue;
2875
2876 pss = buffer.pointer;
2877 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2878 kfree(pss);
2879 return false;
2880 }
2881
2882 kfree(pss);
2883 }
2884
2885 pr_debug("ACPI _PSS not found\n");
2886 return true;
2887 }
2888
intel_pstate_no_acpi_pcch(void)2889 static bool __init intel_pstate_no_acpi_pcch(void)
2890 {
2891 acpi_status status;
2892 acpi_handle handle;
2893
2894 status = acpi_get_handle(NULL, "\\_SB", &handle);
2895 if (ACPI_FAILURE(status))
2896 goto not_found;
2897
2898 if (acpi_has_method(handle, "PCCH"))
2899 return false;
2900
2901 not_found:
2902 pr_debug("ACPI PCCH not found\n");
2903 return true;
2904 }
2905
intel_pstate_has_acpi_ppc(void)2906 static bool __init intel_pstate_has_acpi_ppc(void)
2907 {
2908 int i;
2909
2910 for_each_possible_cpu(i) {
2911 struct acpi_processor *pr = per_cpu(processors, i);
2912
2913 if (!pr)
2914 continue;
2915 if (acpi_has_method(pr->handle, "_PPC"))
2916 return true;
2917 }
2918 pr_debug("ACPI _PPC not found\n");
2919 return false;
2920 }
2921
2922 enum {
2923 PSS,
2924 PPC,
2925 };
2926
2927 /* Hardware vendor-specific info that has its own power management modes */
2928 static struct acpi_platform_list plat_info[] __initdata = {
2929 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
2930 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2931 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2932 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2933 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2934 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2935 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2936 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2937 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2938 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2939 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2940 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2941 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2942 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2943 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2944 { } /* End */
2945 };
2946
2947 #define BITMASK_OOB (BIT(8) | BIT(18))
2948
intel_pstate_platform_pwr_mgmt_exists(void)2949 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2950 {
2951 const struct x86_cpu_id *id;
2952 u64 misc_pwr;
2953 int idx;
2954
2955 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2956 if (id) {
2957 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2958 if (misc_pwr & BITMASK_OOB) {
2959 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
2960 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
2961 return true;
2962 }
2963 }
2964
2965 idx = acpi_match_platform_list(plat_info);
2966 if (idx < 0)
2967 return false;
2968
2969 switch (plat_info[idx].data) {
2970 case PSS:
2971 if (!intel_pstate_no_acpi_pss())
2972 return false;
2973
2974 return intel_pstate_no_acpi_pcch();
2975 case PPC:
2976 return intel_pstate_has_acpi_ppc() && !force_load;
2977 }
2978
2979 return false;
2980 }
2981
intel_pstate_request_control_from_smm(void)2982 static void intel_pstate_request_control_from_smm(void)
2983 {
2984 /*
2985 * It may be unsafe to request P-states control from SMM if _PPC support
2986 * has not been enabled.
2987 */
2988 if (acpi_ppc)
2989 acpi_processor_pstate_control();
2990 }
2991 #else /* CONFIG_ACPI not enabled */
intel_pstate_platform_pwr_mgmt_exists(void)2992 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
intel_pstate_has_acpi_ppc(void)2993 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
intel_pstate_request_control_from_smm(void)2994 static inline void intel_pstate_request_control_from_smm(void) {}
2995 #endif /* CONFIG_ACPI */
2996
2997 #define INTEL_PSTATE_HWP_BROADWELL 0x01
2998
2999 #define X86_MATCH_HWP(model, hwp_mode) \
3000 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3001 X86_FEATURE_HWP, hwp_mode)
3002
3003 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3004 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3005 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3006 X86_MATCH_HWP(ANY, 0),
3007 {}
3008 };
3009
intel_pstate_hwp_is_enabled(void)3010 static bool intel_pstate_hwp_is_enabled(void)
3011 {
3012 u64 value;
3013
3014 rdmsrl(MSR_PM_ENABLE, value);
3015 return !!(value & 0x1);
3016 }
3017
intel_pstate_init(void)3018 static int __init intel_pstate_init(void)
3019 {
3020 const struct x86_cpu_id *id;
3021 int rc;
3022
3023 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3024 return -ENODEV;
3025
3026 id = x86_match_cpu(hwp_support_ids);
3027 if (id) {
3028 bool hwp_forced = intel_pstate_hwp_is_enabled();
3029
3030 if (hwp_forced)
3031 pr_info("HWP enabled by BIOS\n");
3032 else if (no_load)
3033 return -ENODEV;
3034
3035 copy_cpu_funcs(&core_funcs);
3036 /*
3037 * Avoid enabling HWP for processors without EPP support,
3038 * because that means incomplete HWP implementation which is a
3039 * corner case and supporting it is generally problematic.
3040 *
3041 * If HWP is enabled already, though, there is no choice but to
3042 * deal with it.
3043 */
3044 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3045 hwp_active++;
3046 hwp_mode_bdw = id->driver_data;
3047 intel_pstate.attr = hwp_cpufreq_attrs;
3048 intel_cpufreq.attr = hwp_cpufreq_attrs;
3049 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3050 if (!default_driver)
3051 default_driver = &intel_pstate;
3052
3053 goto hwp_cpu_matched;
3054 }
3055 pr_info("HWP not enabled\n");
3056 } else {
3057 if (no_load)
3058 return -ENODEV;
3059
3060 id = x86_match_cpu(intel_pstate_cpu_ids);
3061 if (!id) {
3062 pr_info("CPU model not supported\n");
3063 return -ENODEV;
3064 }
3065
3066 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3067 }
3068
3069 if (intel_pstate_msrs_not_valid()) {
3070 pr_info("Invalid MSRs\n");
3071 return -ENODEV;
3072 }
3073 /* Without HWP start in the passive mode. */
3074 if (!default_driver)
3075 default_driver = &intel_cpufreq;
3076
3077 hwp_cpu_matched:
3078 /*
3079 * The Intel pstate driver will be ignored if the platform
3080 * firmware has its own power management modes.
3081 */
3082 if (intel_pstate_platform_pwr_mgmt_exists()) {
3083 pr_info("P-states controlled by the platform\n");
3084 return -ENODEV;
3085 }
3086
3087 if (!hwp_active && hwp_only)
3088 return -ENOTSUPP;
3089
3090 pr_info("Intel P-state driver initializing\n");
3091
3092 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3093 if (!all_cpu_data)
3094 return -ENOMEM;
3095
3096 intel_pstate_request_control_from_smm();
3097
3098 intel_pstate_sysfs_expose_params();
3099
3100 mutex_lock(&intel_pstate_driver_lock);
3101 rc = intel_pstate_register_driver(default_driver);
3102 mutex_unlock(&intel_pstate_driver_lock);
3103 if (rc) {
3104 intel_pstate_sysfs_remove();
3105 return rc;
3106 }
3107
3108 if (hwp_active) {
3109 const struct x86_cpu_id *id;
3110
3111 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3112 if (id) {
3113 set_power_ctl_ee_state(false);
3114 pr_info("Disabling energy efficiency optimization\n");
3115 }
3116
3117 pr_info("HWP enabled\n");
3118 }
3119
3120 return 0;
3121 }
3122 device_initcall(intel_pstate_init);
3123
intel_pstate_setup(char * str)3124 static int __init intel_pstate_setup(char *str)
3125 {
3126 if (!str)
3127 return -EINVAL;
3128
3129 if (!strcmp(str, "disable"))
3130 no_load = 1;
3131 else if (!strcmp(str, "active"))
3132 default_driver = &intel_pstate;
3133 else if (!strcmp(str, "passive"))
3134 default_driver = &intel_cpufreq;
3135
3136 if (!strcmp(str, "no_hwp"))
3137 no_hwp = 1;
3138
3139 if (!strcmp(str, "force"))
3140 force_load = 1;
3141 if (!strcmp(str, "hwp_only"))
3142 hwp_only = 1;
3143 if (!strcmp(str, "per_cpu_perf_limits"))
3144 per_cpu_limits = true;
3145
3146 #ifdef CONFIG_ACPI
3147 if (!strcmp(str, "support_acpi_ppc"))
3148 acpi_ppc = true;
3149 #endif
3150
3151 return 0;
3152 }
3153 early_param("intel_pstate", intel_pstate_setup);
3154
3155 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3156 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3157 MODULE_LICENSE("GPL");
3158