1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #include <linux/acpi.h>
4 #include <linux/aer.h>
5 #include <linux/bitops.h>
6 #include <linux/debugfs.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/seq_file.h>
13 #include <linux/topology.h>
14 #include <linux/uacce.h>
15 #include "zip.h"
16
17 #define PCI_DEVICE_ID_ZIP_PF 0xa250
18 #define PCI_DEVICE_ID_ZIP_VF 0xa251
19
20 #define HZIP_QUEUE_NUM_V1 4096
21 #define HZIP_QUEUE_NUM_V2 1024
22
23 #define HZIP_CLOCK_GATE_CTRL 0x301004
24 #define COMP0_ENABLE BIT(0)
25 #define COMP1_ENABLE BIT(1)
26 #define DECOMP0_ENABLE BIT(2)
27 #define DECOMP1_ENABLE BIT(3)
28 #define DECOMP2_ENABLE BIT(4)
29 #define DECOMP3_ENABLE BIT(5)
30 #define DECOMP4_ENABLE BIT(6)
31 #define DECOMP5_ENABLE BIT(7)
32 #define HZIP_ALL_COMP_DECOMP_EN (COMP0_ENABLE | COMP1_ENABLE | \
33 DECOMP0_ENABLE | DECOMP1_ENABLE | \
34 DECOMP2_ENABLE | DECOMP3_ENABLE | \
35 DECOMP4_ENABLE | DECOMP5_ENABLE)
36 #define HZIP_DECOMP_CHECK_ENABLE BIT(16)
37 #define HZIP_FSM_MAX_CNT 0x301008
38
39 #define HZIP_PORT_ARCA_CHE_0 0x301040
40 #define HZIP_PORT_ARCA_CHE_1 0x301044
41 #define HZIP_PORT_AWCA_CHE_0 0x301060
42 #define HZIP_PORT_AWCA_CHE_1 0x301064
43 #define HZIP_CACHE_ALL_EN 0xffffffff
44
45 #define HZIP_BD_RUSER_32_63 0x301110
46 #define HZIP_SGL_RUSER_32_63 0x30111c
47 #define HZIP_DATA_RUSER_32_63 0x301128
48 #define HZIP_DATA_WUSER_32_63 0x301134
49 #define HZIP_BD_WUSER_32_63 0x301140
50
51 #define HZIP_QM_IDEL_STATUS 0x3040e4
52
53 #define HZIP_CORE_DEBUG_COMP_0 0x302000
54 #define HZIP_CORE_DEBUG_COMP_1 0x303000
55 #define HZIP_CORE_DEBUG_DECOMP_0 0x304000
56 #define HZIP_CORE_DEBUG_DECOMP_1 0x305000
57 #define HZIP_CORE_DEBUG_DECOMP_2 0x306000
58 #define HZIP_CORE_DEBUG_DECOMP_3 0x307000
59 #define HZIP_CORE_DEBUG_DECOMP_4 0x308000
60 #define HZIP_CORE_DEBUG_DECOMP_5 0x309000
61
62 #define HZIP_CORE_INT_SOURCE 0x3010A0
63 #define HZIP_CORE_INT_MASK_REG 0x3010A4
64 #define HZIP_CORE_INT_SET 0x3010A8
65 #define HZIP_CORE_INT_STATUS 0x3010AC
66 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1)
67 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148
68 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160
69 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164
70 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168
71 #define HZIP_CORE_INT_RAS_NFE_ENABLE 0x7FE
72 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16
73 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24
74 #define HZIP_CORE_INT_MASK_ALL GENMASK(10, 0)
75 #define HZIP_COMP_CORE_NUM 2
76 #define HZIP_DECOMP_CORE_NUM 6
77 #define HZIP_CORE_NUM (HZIP_COMP_CORE_NUM + \
78 HZIP_DECOMP_CORE_NUM)
79 #define HZIP_SQE_SIZE 128
80 #define HZIP_SQ_SIZE (HZIP_SQE_SIZE * QM_Q_DEPTH)
81 #define HZIP_PF_DEF_Q_NUM 64
82 #define HZIP_PF_DEF_Q_BASE 0
83
84 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000
85 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0)
86 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C
87 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14)
88 #define HZIP_WR_PORT BIT(11)
89
90 #define HZIP_BUF_SIZE 22
91 #define HZIP_SQE_MASK_OFFSET 64
92 #define HZIP_SQE_MASK_LEN 48
93
94 #define HZIP_CNT_CLR_CE_EN BIT(0)
95 #define HZIP_RO_CNT_CLR_CE_EN BIT(2)
96 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \
97 HZIP_RO_CNT_CLR_CE_EN)
98
99 static const char hisi_zip_name[] = "hisi_zip";
100 static struct dentry *hzip_debugfs_root;
101
102 struct hisi_zip_hw_error {
103 u32 int_msk;
104 const char *msg;
105 };
106
107 struct zip_dfx_item {
108 const char *name;
109 u32 offset;
110 };
111
112 static struct hisi_qm_list zip_devices = {
113 .register_to_crypto = hisi_zip_register_to_crypto,
114 .unregister_from_crypto = hisi_zip_unregister_from_crypto,
115 };
116
117 static struct zip_dfx_item zip_dfx_files[] = {
118 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)},
119 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)},
120 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)},
121 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)},
122 };
123
124 static const struct hisi_zip_hw_error zip_hw_error[] = {
125 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" },
126 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" },
127 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" },
128 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" },
129 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" },
130 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" },
131 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" },
132 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" },
133 { .int_msk = BIT(8), .msg = "zip_com_inf_err" },
134 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" },
135 { .int_msk = BIT(10), .msg = "zip_pre_out_err" },
136 { /* sentinel */ }
137 };
138
139 enum ctrl_debug_file_index {
140 HZIP_CURRENT_QM,
141 HZIP_CLEAR_ENABLE,
142 HZIP_DEBUG_FILE_NUM,
143 };
144
145 static const char * const ctrl_debug_file_name[] = {
146 [HZIP_CURRENT_QM] = "current_qm",
147 [HZIP_CLEAR_ENABLE] = "clear_enable",
148 };
149
150 struct ctrl_debug_file {
151 enum ctrl_debug_file_index index;
152 spinlock_t lock;
153 struct hisi_zip_ctrl *ctrl;
154 };
155
156 /*
157 * One ZIP controller has one PF and multiple VFs, some global configurations
158 * which PF has need this structure.
159 *
160 * Just relevant for PF.
161 */
162 struct hisi_zip_ctrl {
163 struct hisi_zip *hisi_zip;
164 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM];
165 };
166
167 enum {
168 HZIP_COMP_CORE0,
169 HZIP_COMP_CORE1,
170 HZIP_DECOMP_CORE0,
171 HZIP_DECOMP_CORE1,
172 HZIP_DECOMP_CORE2,
173 HZIP_DECOMP_CORE3,
174 HZIP_DECOMP_CORE4,
175 HZIP_DECOMP_CORE5,
176 };
177
178 static const u64 core_offsets[] = {
179 [HZIP_COMP_CORE0] = 0x302000,
180 [HZIP_COMP_CORE1] = 0x303000,
181 [HZIP_DECOMP_CORE0] = 0x304000,
182 [HZIP_DECOMP_CORE1] = 0x305000,
183 [HZIP_DECOMP_CORE2] = 0x306000,
184 [HZIP_DECOMP_CORE3] = 0x307000,
185 [HZIP_DECOMP_CORE4] = 0x308000,
186 [HZIP_DECOMP_CORE5] = 0x309000,
187 };
188
189 static const struct debugfs_reg32 hzip_dfx_regs[] = {
190 {"HZIP_GET_BD_NUM ", 0x00ull},
191 {"HZIP_GET_RIGHT_BD ", 0x04ull},
192 {"HZIP_GET_ERROR_BD ", 0x08ull},
193 {"HZIP_DONE_BD_NUM ", 0x0cull},
194 {"HZIP_WORK_CYCLE ", 0x10ull},
195 {"HZIP_IDLE_CYCLE ", 0x18ull},
196 {"HZIP_MAX_DELAY ", 0x20ull},
197 {"HZIP_MIN_DELAY ", 0x24ull},
198 {"HZIP_AVG_DELAY ", 0x28ull},
199 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull},
200 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull},
201 {"HZIP_COMSUMED_BYTE ", 0x38ull},
202 {"HZIP_PRODUCED_BYTE ", 0x40ull},
203 {"HZIP_COMP_INF ", 0x70ull},
204 {"HZIP_PRE_OUT ", 0x78ull},
205 {"HZIP_BD_RD ", 0x7cull},
206 {"HZIP_BD_WR ", 0x80ull},
207 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull},
208 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull},
209 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull},
210 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull},
211 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull},
212 };
213
pf_q_num_set(const char * val,const struct kernel_param * kp)214 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
215 {
216 return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF);
217 }
218
219 static const struct kernel_param_ops pf_q_num_ops = {
220 .set = pf_q_num_set,
221 .get = param_get_int,
222 };
223
224 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM;
225 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444);
226 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
227
228 static const struct kernel_param_ops vfs_num_ops = {
229 .set = vfs_num_set,
230 .get = param_get_int,
231 };
232
233 static u32 vfs_num;
234 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
235 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
236
237 static const struct pci_device_id hisi_zip_dev_ids[] = {
238 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) },
239 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) },
240 { 0, }
241 };
242 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids);
243
zip_create_qps(struct hisi_qp ** qps,int qp_num,int node)244 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node)
245 {
246 if (node == NUMA_NO_NODE)
247 node = cpu_to_node(smp_processor_id());
248
249 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps);
250 }
251
hisi_zip_set_user_domain_and_cache(struct hisi_qm * qm)252 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
253 {
254 void __iomem *base = qm->io_base;
255
256 /* qm user domain */
257 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
258 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE);
259 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1);
260 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE);
261 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE);
262
263 /* qm cache */
264 writel(AXI_M_CFG, base + QM_AXI_M_CFG);
265 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
266
267 /* disable FLR triggered by BME(bus master enable) */
268 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
269 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
270
271 /* cache */
272 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0);
273 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1);
274 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0);
275 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1);
276
277 /* user domain configurations */
278 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
279 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
280 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
281
282 if (qm->use_sva) {
283 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
284 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
285 } else {
286 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
287 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
288 }
289
290 /* let's open all compression/decompression cores */
291 writel(HZIP_DECOMP_CHECK_ENABLE | HZIP_ALL_COMP_DECOMP_EN,
292 base + HZIP_CLOCK_GATE_CTRL);
293
294 /* enable sqc,cqc writeback */
295 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
296 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
297 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
298
299 return 0;
300 }
301
hisi_zip_hw_error_enable(struct hisi_qm * qm)302 static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
303 {
304 u32 val;
305
306 if (qm->ver == QM_HW_V1) {
307 writel(HZIP_CORE_INT_MASK_ALL,
308 qm->io_base + HZIP_CORE_INT_MASK_REG);
309 dev_info(&qm->pdev->dev, "Does not support hw error handle\n");
310 return;
311 }
312
313 /* clear ZIP hw error source if having */
314 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE);
315
316 /* configure error type */
317 writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
318 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
319 writel(HZIP_CORE_INT_RAS_NFE_ENABLE,
320 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
321
322 /* enable ZIP hw error interrupts */
323 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
324
325 /* enable ZIP block master OOO when m-bit error occur */
326 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
327 val = val | HZIP_AXI_SHUTDOWN_ENABLE;
328 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
329 }
330
hisi_zip_hw_error_disable(struct hisi_qm * qm)331 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)
332 {
333 u32 val;
334
335 /* disable ZIP hw error interrupts */
336 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG);
337
338 /* disable ZIP block master OOO when m-bit error occur */
339 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
340 val = val & ~HZIP_AXI_SHUTDOWN_ENABLE;
341 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
342 }
343
file_to_qm(struct ctrl_debug_file * file)344 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file)
345 {
346 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip;
347
348 return &hisi_zip->qm;
349 }
350
current_qm_read(struct ctrl_debug_file * file)351 static u32 current_qm_read(struct ctrl_debug_file *file)
352 {
353 struct hisi_qm *qm = file_to_qm(file);
354
355 return readl(qm->io_base + QM_DFX_MB_CNT_VF);
356 }
357
current_qm_write(struct ctrl_debug_file * file,u32 val)358 static int current_qm_write(struct ctrl_debug_file *file, u32 val)
359 {
360 struct hisi_qm *qm = file_to_qm(file);
361 u32 vfq_num;
362 u32 tmp;
363
364 if (val > qm->vfs_num)
365 return -EINVAL;
366
367 /* According PF or VF Dev ID to calculation curr_qm_qp_num and store */
368 if (val == 0) {
369 qm->debug.curr_qm_qp_num = qm->qp_num;
370 } else {
371 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / qm->vfs_num;
372 if (val == qm->vfs_num)
373 qm->debug.curr_qm_qp_num = qm->ctrl_qp_num -
374 qm->qp_num - (qm->vfs_num - 1) * vfq_num;
375 else
376 qm->debug.curr_qm_qp_num = vfq_num;
377 }
378
379 writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
380 writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
381
382 tmp = val |
383 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
384 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
385
386 tmp = val |
387 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
388 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
389
390 return 0;
391 }
392
clear_enable_read(struct ctrl_debug_file * file)393 static u32 clear_enable_read(struct ctrl_debug_file *file)
394 {
395 struct hisi_qm *qm = file_to_qm(file);
396
397 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
398 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT;
399 }
400
clear_enable_write(struct ctrl_debug_file * file,u32 val)401 static int clear_enable_write(struct ctrl_debug_file *file, u32 val)
402 {
403 struct hisi_qm *qm = file_to_qm(file);
404 u32 tmp;
405
406 if (val != 1 && val != 0)
407 return -EINVAL;
408
409 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
410 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val;
411 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
412
413 return 0;
414 }
415
hisi_zip_ctrl_debug_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)416 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf,
417 size_t count, loff_t *pos)
418 {
419 struct ctrl_debug_file *file = filp->private_data;
420 char tbuf[HZIP_BUF_SIZE];
421 u32 val;
422 int ret;
423
424 spin_lock_irq(&file->lock);
425 switch (file->index) {
426 case HZIP_CURRENT_QM:
427 val = current_qm_read(file);
428 break;
429 case HZIP_CLEAR_ENABLE:
430 val = clear_enable_read(file);
431 break;
432 default:
433 spin_unlock_irq(&file->lock);
434 return -EINVAL;
435 }
436 spin_unlock_irq(&file->lock);
437 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val);
438 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
439 }
440
hisi_zip_ctrl_debug_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)441 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp,
442 const char __user *buf,
443 size_t count, loff_t *pos)
444 {
445 struct ctrl_debug_file *file = filp->private_data;
446 char tbuf[HZIP_BUF_SIZE];
447 unsigned long val;
448 int len, ret;
449
450 if (*pos != 0)
451 return 0;
452
453 if (count >= HZIP_BUF_SIZE)
454 return -ENOSPC;
455
456 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count);
457 if (len < 0)
458 return len;
459
460 tbuf[len] = '\0';
461 if (kstrtoul(tbuf, 0, &val))
462 return -EFAULT;
463
464 spin_lock_irq(&file->lock);
465 switch (file->index) {
466 case HZIP_CURRENT_QM:
467 ret = current_qm_write(file, val);
468 if (ret)
469 goto err_input;
470 break;
471 case HZIP_CLEAR_ENABLE:
472 ret = clear_enable_write(file, val);
473 if (ret)
474 goto err_input;
475 break;
476 default:
477 ret = -EINVAL;
478 goto err_input;
479 }
480 spin_unlock_irq(&file->lock);
481
482 return count;
483
484 err_input:
485 spin_unlock_irq(&file->lock);
486 return ret;
487 }
488
489 static const struct file_operations ctrl_debug_fops = {
490 .owner = THIS_MODULE,
491 .open = simple_open,
492 .read = hisi_zip_ctrl_debug_read,
493 .write = hisi_zip_ctrl_debug_write,
494 };
495
zip_debugfs_atomic64_set(void * data,u64 val)496 static int zip_debugfs_atomic64_set(void *data, u64 val)
497 {
498 if (val)
499 return -EINVAL;
500
501 atomic64_set((atomic64_t *)data, 0);
502
503 return 0;
504 }
505
zip_debugfs_atomic64_get(void * data,u64 * val)506 static int zip_debugfs_atomic64_get(void *data, u64 *val)
507 {
508 *val = atomic64_read((atomic64_t *)data);
509
510 return 0;
511 }
512
513 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get,
514 zip_debugfs_atomic64_set, "%llu\n");
515
hisi_zip_core_debug_init(struct hisi_qm * qm)516 static int hisi_zip_core_debug_init(struct hisi_qm *qm)
517 {
518 struct device *dev = &qm->pdev->dev;
519 struct debugfs_regset32 *regset;
520 struct dentry *tmp_d;
521 char buf[HZIP_BUF_SIZE];
522 int i;
523
524 for (i = 0; i < HZIP_CORE_NUM; i++) {
525 if (i < HZIP_COMP_CORE_NUM)
526 scnprintf(buf, sizeof(buf), "comp_core%d", i);
527 else
528 scnprintf(buf, sizeof(buf), "decomp_core%d",
529 i - HZIP_COMP_CORE_NUM);
530
531 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
532 if (!regset)
533 return -ENOENT;
534
535 regset->regs = hzip_dfx_regs;
536 regset->nregs = ARRAY_SIZE(hzip_dfx_regs);
537 regset->base = qm->io_base + core_offsets[i];
538
539 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
540 debugfs_create_regset32("regs", 0444, tmp_d, regset);
541 }
542
543 return 0;
544 }
545
hisi_zip_dfx_debug_init(struct hisi_qm * qm)546 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm)
547 {
548 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
549 struct hisi_zip_dfx *dfx = &zip->dfx;
550 struct dentry *tmp_dir;
551 void *data;
552 int i;
553
554 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root);
555 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) {
556 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset);
557 debugfs_create_file(zip_dfx_files[i].name,
558 0644, tmp_dir, data,
559 &zip_atomic64_ops);
560 }
561 }
562
hisi_zip_ctrl_debug_init(struct hisi_qm * qm)563 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm)
564 {
565 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
566 int i;
567
568 for (i = HZIP_CURRENT_QM; i < HZIP_DEBUG_FILE_NUM; i++) {
569 spin_lock_init(&zip->ctrl->files[i].lock);
570 zip->ctrl->files[i].ctrl = zip->ctrl;
571 zip->ctrl->files[i].index = i;
572
573 debugfs_create_file(ctrl_debug_file_name[i], 0600,
574 qm->debug.debug_root,
575 zip->ctrl->files + i,
576 &ctrl_debug_fops);
577 }
578
579 return hisi_zip_core_debug_init(qm);
580 }
581
hisi_zip_debugfs_init(struct hisi_qm * qm)582 static int hisi_zip_debugfs_init(struct hisi_qm *qm)
583 {
584 struct device *dev = &qm->pdev->dev;
585 struct dentry *dev_d;
586 int ret;
587
588 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root);
589
590 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET;
591 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN;
592 qm->debug.debug_root = dev_d;
593 ret = hisi_qm_debug_init(qm);
594 if (ret)
595 goto failed_to_create;
596
597 if (qm->fun_type == QM_HW_PF) {
598 ret = hisi_zip_ctrl_debug_init(qm);
599 if (ret)
600 goto failed_to_create;
601 }
602
603 hisi_zip_dfx_debug_init(qm);
604
605 return 0;
606
607 failed_to_create:
608 debugfs_remove_recursive(hzip_debugfs_root);
609 return ret;
610 }
611
612 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */
hisi_zip_debug_regs_clear(struct hisi_qm * qm)613 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm)
614 {
615 int i, j;
616
617 /* clear current_qm */
618 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
619 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
620
621 /* enable register read_clear bit */
622 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
623 for (i = 0; i < ARRAY_SIZE(core_offsets); i++)
624 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++)
625 readl(qm->io_base + core_offsets[i] +
626 hzip_dfx_regs[j].offset);
627
628 /* disable register read_clear bit */
629 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
630
631 hisi_qm_debug_regs_clear(qm);
632 }
633
hisi_zip_debugfs_exit(struct hisi_qm * qm)634 static void hisi_zip_debugfs_exit(struct hisi_qm *qm)
635 {
636 debugfs_remove_recursive(qm->debug.debug_root);
637
638 if (qm->fun_type == QM_HW_PF) {
639 hisi_zip_debug_regs_clear(qm);
640 qm->debug.curr_qm_qp_num = 0;
641 }
642 }
643
hisi_zip_log_hw_error(struct hisi_qm * qm,u32 err_sts)644 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
645 {
646 const struct hisi_zip_hw_error *err = zip_hw_error;
647 struct device *dev = &qm->pdev->dev;
648 u32 err_val;
649
650 while (err->msg) {
651 if (err->int_msk & err_sts) {
652 dev_err(dev, "%s [error status=0x%x] found\n",
653 err->msg, err->int_msk);
654
655 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) {
656 err_val = readl(qm->io_base +
657 HZIP_CORE_SRAM_ECC_ERR_INFO);
658 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n",
659 ((err_val >>
660 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF));
661 }
662 }
663 err++;
664 }
665 }
666
hisi_zip_get_hw_err_status(struct hisi_qm * qm)667 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
668 {
669 return readl(qm->io_base + HZIP_CORE_INT_STATUS);
670 }
671
hisi_zip_clear_hw_err_status(struct hisi_qm * qm,u32 err_sts)672 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
673 {
674 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
675 }
676
hisi_zip_open_axi_master_ooo(struct hisi_qm * qm)677 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)
678 {
679 u32 val;
680
681 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
682
683 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE,
684 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
685
686 writel(val | HZIP_AXI_SHUTDOWN_ENABLE,
687 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
688 }
689
hisi_zip_close_axi_master_ooo(struct hisi_qm * qm)690 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)
691 {
692 u32 nfe_enb;
693
694 /* Disable ECC Mbit error report. */
695 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
696 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC,
697 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
698
699 /* Inject zip ECC Mbit error to block master ooo. */
700 writel(HZIP_CORE_INT_STATUS_M_ECC,
701 qm->io_base + HZIP_CORE_INT_SET);
702 }
703
704 static const struct hisi_qm_err_ini hisi_zip_err_ini = {
705 .hw_init = hisi_zip_set_user_domain_and_cache,
706 .hw_err_enable = hisi_zip_hw_error_enable,
707 .hw_err_disable = hisi_zip_hw_error_disable,
708 .get_dev_hw_err_status = hisi_zip_get_hw_err_status,
709 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status,
710 .log_dev_hw_err = hisi_zip_log_hw_error,
711 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo,
712 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo,
713 .err_info = {
714 .ce = QM_BASE_CE,
715 .nfe = QM_BASE_NFE |
716 QM_ACC_WB_NOT_READY_TIMEOUT,
717 .fe = 0,
718 .ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC,
719 .msi_wr_port = HZIP_WR_PORT,
720 .acpi_rst = "ZRST",
721 }
722 };
723
hisi_zip_pf_probe_init(struct hisi_zip * hisi_zip)724 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
725 {
726 struct hisi_qm *qm = &hisi_zip->qm;
727 struct hisi_zip_ctrl *ctrl;
728
729 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
730 if (!ctrl)
731 return -ENOMEM;
732
733 hisi_zip->ctrl = ctrl;
734 ctrl->hisi_zip = hisi_zip;
735
736 if (qm->ver == QM_HW_V1)
737 qm->ctrl_qp_num = HZIP_QUEUE_NUM_V1;
738 else
739 qm->ctrl_qp_num = HZIP_QUEUE_NUM_V2;
740
741 qm->err_ini = &hisi_zip_err_ini;
742
743 hisi_zip_set_user_domain_and_cache(qm);
744 hisi_qm_dev_err_init(qm);
745 hisi_zip_debug_regs_clear(qm);
746
747 return 0;
748 }
749
hisi_zip_qm_init(struct hisi_qm * qm,struct pci_dev * pdev)750 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
751 {
752 qm->pdev = pdev;
753 qm->ver = pdev->revision;
754 qm->algs = "zlib\ngzip";
755 qm->sqe_size = HZIP_SQE_SIZE;
756 qm->dev_name = hisi_zip_name;
757
758 qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ?
759 QM_HW_PF : QM_HW_VF;
760 if (qm->fun_type == QM_HW_PF) {
761 qm->qp_base = HZIP_PF_DEF_Q_BASE;
762 qm->qp_num = pf_q_num;
763 qm->debug.curr_qm_qp_num = pf_q_num;
764 qm->qm_list = &zip_devices;
765 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
766 /*
767 * have no way to get qm configure in VM in v1 hardware,
768 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force
769 * to trigger only one VF in v1 hardware.
770 *
771 * v2 hardware has no such problem.
772 */
773 qm->qp_base = HZIP_PF_DEF_Q_NUM;
774 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
775 }
776
777 return hisi_qm_init(qm);
778 }
779
hisi_zip_probe_init(struct hisi_zip * hisi_zip)780 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip)
781 {
782 struct hisi_qm *qm = &hisi_zip->qm;
783 int ret;
784
785 if (qm->fun_type == QM_HW_PF) {
786 ret = hisi_zip_pf_probe_init(hisi_zip);
787 if (ret)
788 return ret;
789 }
790
791 return 0;
792 }
793
hisi_zip_probe(struct pci_dev * pdev,const struct pci_device_id * id)794 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
795 {
796 struct hisi_zip *hisi_zip;
797 struct hisi_qm *qm;
798 int ret;
799
800 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL);
801 if (!hisi_zip)
802 return -ENOMEM;
803
804 qm = &hisi_zip->qm;
805
806 ret = hisi_zip_qm_init(qm, pdev);
807 if (ret) {
808 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret);
809 return ret;
810 }
811
812 ret = hisi_zip_probe_init(hisi_zip);
813 if (ret) {
814 pci_err(pdev, "Failed to probe (%d)!\n", ret);
815 goto err_qm_uninit;
816 }
817
818 ret = hisi_qm_start(qm);
819 if (ret)
820 goto err_dev_err_uninit;
821
822 ret = hisi_zip_debugfs_init(qm);
823 if (ret)
824 pci_err(pdev, "failed to init debugfs (%d)!\n", ret);
825
826 ret = hisi_qm_alg_register(qm, &zip_devices);
827 if (ret < 0) {
828 pci_err(pdev, "failed to register driver to crypto!\n");
829 goto err_qm_stop;
830 }
831
832 if (qm->uacce) {
833 ret = uacce_register(qm->uacce);
834 if (ret) {
835 pci_err(pdev, "failed to register uacce (%d)!\n", ret);
836 goto err_qm_alg_unregister;
837 }
838 }
839
840 if (qm->fun_type == QM_HW_PF && vfs_num > 0) {
841 ret = hisi_qm_sriov_enable(pdev, vfs_num);
842 if (ret < 0)
843 goto err_qm_alg_unregister;
844 }
845
846 return 0;
847
848 err_qm_alg_unregister:
849 hisi_qm_alg_unregister(qm, &zip_devices);
850
851 err_qm_stop:
852 hisi_zip_debugfs_exit(qm);
853 hisi_qm_stop(qm, QM_NORMAL);
854
855 err_dev_err_uninit:
856 hisi_qm_dev_err_uninit(qm);
857
858 err_qm_uninit:
859 hisi_qm_uninit(qm);
860
861 return ret;
862 }
863
hisi_zip_remove(struct pci_dev * pdev)864 static void hisi_zip_remove(struct pci_dev *pdev)
865 {
866 struct hisi_qm *qm = pci_get_drvdata(pdev);
867
868 hisi_qm_wait_task_finish(qm, &zip_devices);
869 hisi_qm_alg_unregister(qm, &zip_devices);
870
871 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
872 hisi_qm_sriov_disable(pdev, qm->is_frozen);
873
874 hisi_zip_debugfs_exit(qm);
875 hisi_qm_stop(qm, QM_NORMAL);
876 hisi_qm_dev_err_uninit(qm);
877 hisi_qm_uninit(qm);
878 }
879
880 static const struct pci_error_handlers hisi_zip_err_handler = {
881 .error_detected = hisi_qm_dev_err_detected,
882 .slot_reset = hisi_qm_dev_slot_reset,
883 .reset_prepare = hisi_qm_reset_prepare,
884 .reset_done = hisi_qm_reset_done,
885 };
886
887 static struct pci_driver hisi_zip_pci_driver = {
888 .name = "hisi_zip",
889 .id_table = hisi_zip_dev_ids,
890 .probe = hisi_zip_probe,
891 .remove = hisi_zip_remove,
892 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ?
893 hisi_qm_sriov_configure : NULL,
894 .err_handler = &hisi_zip_err_handler,
895 .shutdown = hisi_qm_dev_shutdown,
896 };
897
hisi_zip_register_debugfs(void)898 static void hisi_zip_register_debugfs(void)
899 {
900 if (!debugfs_initialized())
901 return;
902
903 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL);
904 }
905
hisi_zip_unregister_debugfs(void)906 static void hisi_zip_unregister_debugfs(void)
907 {
908 debugfs_remove_recursive(hzip_debugfs_root);
909 }
910
hisi_zip_init(void)911 static int __init hisi_zip_init(void)
912 {
913 int ret;
914
915 hisi_qm_init_list(&zip_devices);
916 hisi_zip_register_debugfs();
917
918 ret = pci_register_driver(&hisi_zip_pci_driver);
919 if (ret < 0) {
920 hisi_zip_unregister_debugfs();
921 pr_err("Failed to register pci driver.\n");
922 }
923
924 return ret;
925 }
926
hisi_zip_exit(void)927 static void __exit hisi_zip_exit(void)
928 {
929 pci_unregister_driver(&hisi_zip_pci_driver);
930 hisi_zip_unregister_debugfs();
931 }
932
933 module_init(hisi_zip_init);
934 module_exit(hisi_zip_exit);
935
936 MODULE_LICENSE("GPL v2");
937 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
938 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator");
939