1 /* SPDX-License-Identifier: GPL-2.0 2 * Marvell OcteonTX CPT driver 3 * 4 * Copyright (C) 2019 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __OTX_CPTPF_UCODE_H 12 #define __OTX_CPTPF_UCODE_H 13 14 #include <linux/pci.h> 15 #include <linux/types.h> 16 #include <linux/module.h> 17 #include "otx_cpt_hw_types.h" 18 19 /* CPT ucode name maximum length */ 20 #define OTX_CPT_UCODE_NAME_LENGTH 64 21 /* 22 * On OcteonTX 83xx platform, only one type of engines is allowed to be 23 * attached to an engine group. 24 */ 25 #define OTX_CPT_MAX_ETYPES_PER_GRP 1 26 27 /* Default tar archive file names */ 28 #define OTX_CPT_UCODE_TAR_FILE_NAME "cpt8x-mc.tar" 29 30 /* CPT ucode alignment */ 31 #define OTX_CPT_UCODE_ALIGNMENT 128 32 33 /* CPT ucode signature size */ 34 #define OTX_CPT_UCODE_SIGN_LEN 256 35 36 /* Microcode version string length */ 37 #define OTX_CPT_UCODE_VER_STR_SZ 44 38 39 /* Maximum number of supported engines/cores on OcteonTX 83XX platform */ 40 #define OTX_CPT_MAX_ENGINES 64 41 42 #define OTX_CPT_ENGS_BITMASK_LEN (OTX_CPT_MAX_ENGINES/(BITS_PER_BYTE * \ 43 sizeof(unsigned long))) 44 45 /* Microcode types */ 46 enum otx_cpt_ucode_type { 47 OTX_CPT_AE_UC_TYPE = 1, /* AE-MAIN */ 48 OTX_CPT_SE_UC_TYPE1 = 20, /* SE-MAIN - combination of 21 and 22 */ 49 OTX_CPT_SE_UC_TYPE2 = 21, /* Fast Path IPSec + AirCrypto */ 50 OTX_CPT_SE_UC_TYPE3 = 22, /* 51 * Hash + HMAC + FlexiCrypto + RNG + Full 52 * Feature IPSec + AirCrypto + Kasumi 53 */ 54 }; 55 56 struct otx_cpt_bitmap { 57 unsigned long bits[OTX_CPT_ENGS_BITMASK_LEN]; 58 int size; 59 }; 60 61 struct otx_cpt_engines { 62 int type; 63 int count; 64 }; 65 66 /* Microcode version number */ 67 struct otx_cpt_ucode_ver_num { 68 u8 nn; 69 u8 xx; 70 u8 yy; 71 u8 zz; 72 }; 73 74 struct otx_cpt_ucode_hdr { 75 struct otx_cpt_ucode_ver_num ver_num; 76 u8 ver_str[OTX_CPT_UCODE_VER_STR_SZ]; 77 __be32 code_length; 78 u32 padding[3]; 79 }; 80 81 struct otx_cpt_ucode { 82 u8 ver_str[OTX_CPT_UCODE_VER_STR_SZ];/* 83 * ucode version in readable format 84 */ 85 struct otx_cpt_ucode_ver_num ver_num;/* ucode version number */ 86 char filename[OTX_CPT_UCODE_NAME_LENGTH]; /* ucode filename */ 87 dma_addr_t dma; /* phys address of ucode image */ 88 dma_addr_t align_dma; /* aligned phys address of ucode image */ 89 void *va; /* virt address of ucode image */ 90 void *align_va; /* aligned virt address of ucode image */ 91 u32 size; /* ucode image size */ 92 int type; /* ucode image type SE or AE */ 93 }; 94 95 struct tar_ucode_info_t { 96 struct list_head list; 97 struct otx_cpt_ucode ucode;/* microcode information */ 98 const u8 *ucode_ptr; /* pointer to microcode in tar archive */ 99 }; 100 101 /* Maximum and current number of engines available for all engine groups */ 102 struct otx_cpt_engs_available { 103 int max_se_cnt; 104 int max_ae_cnt; 105 int se_cnt; 106 int ae_cnt; 107 }; 108 109 /* Engines reserved to an engine group */ 110 struct otx_cpt_engs_rsvd { 111 int type; /* engine type */ 112 int count; /* number of engines attached */ 113 int offset; /* constant offset of engine type in the bitmap */ 114 unsigned long *bmap; /* attached engines bitmap */ 115 struct otx_cpt_ucode *ucode; /* ucode used by these engines */ 116 }; 117 118 struct otx_cpt_mirror_info { 119 int is_ena; /* 120 * is mirroring enabled, it is set only for engine 121 * group which mirrors another engine group 122 */ 123 int idx; /* 124 * index of engine group which is mirrored by this 125 * group, set only for engine group which mirrors 126 * another group 127 */ 128 int ref_count; /* 129 * number of times this engine group is mirrored by 130 * other groups, this is set only for engine group 131 * which is mirrored by other group(s) 132 */ 133 }; 134 135 struct otx_cpt_eng_grp_info { 136 struct otx_cpt_eng_grps *g; /* pointer to engine_groups structure */ 137 struct device_attribute info_attr; /* group info entry attr */ 138 /* engines attached */ 139 struct otx_cpt_engs_rsvd engs[OTX_CPT_MAX_ETYPES_PER_GRP]; 140 /* Microcode information */ 141 struct otx_cpt_ucode ucode[OTX_CPT_MAX_ETYPES_PER_GRP]; 142 /* sysfs info entry name */ 143 char sysfs_info_name[OTX_CPT_UCODE_NAME_LENGTH]; 144 /* engine group mirroring information */ 145 struct otx_cpt_mirror_info mirror; 146 int idx; /* engine group index */ 147 bool is_enabled; /* 148 * is engine group enabled, engine group is enabled 149 * when it has engines attached and ucode loaded 150 */ 151 }; 152 153 struct otx_cpt_eng_grps { 154 struct otx_cpt_eng_grp_info grp[OTX_CPT_MAX_ENGINE_GROUPS]; 155 struct device_attribute ucode_load_attr;/* ucode load attr */ 156 struct otx_cpt_engs_available avail; 157 struct mutex lock; 158 void *obj; 159 int engs_num; /* total number of engines supported */ 160 int eng_types_supported; /* engine types supported SE, AE */ 161 u8 eng_ref_cnt[OTX_CPT_MAX_ENGINES];/* engines reference count */ 162 bool is_ucode_load_created; /* is ucode_load sysfs entry created */ 163 bool is_first_try; /* is this first try to create kcrypto engine grp */ 164 bool is_rdonly; /* do engine groups configuration can be modified */ 165 }; 166 167 int otx_cpt_init_eng_grps(struct pci_dev *pdev, 168 struct otx_cpt_eng_grps *eng_grps, int pf_type); 169 void otx_cpt_cleanup_eng_grps(struct pci_dev *pdev, 170 struct otx_cpt_eng_grps *eng_grps); 171 int otx_cpt_try_create_default_eng_grps(struct pci_dev *pdev, 172 struct otx_cpt_eng_grps *eng_grps, 173 int pf_type); 174 void otx_cpt_set_eng_grps_is_rdonly(struct otx_cpt_eng_grps *eng_grps, 175 bool is_rdonly); 176 int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type); 177 int otx_cpt_eng_grp_has_eng_type(struct otx_cpt_eng_grp_info *eng_grp, 178 int eng_type); 179 180 #endif /* __OTX_CPTPF_UCODE_H */ 181