1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_10_3_0_offset.h"
34 #include "gc/gc_10_3_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39
40 #include "soc15_common.h"
41 #include "soc15.h"
42 #include "navi10_sdma_pkt_open.h"
43 #include "nbio_v2_3.h"
44 #include "sdma_common.h"
45 #include "sdma_v5_2.h"
46
47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49
50 #define SDMA1_REG_OFFSET 0x600
51 #define SDMA3_REG_OFFSET 0x400
52 #define SDMA0_HYP_DEC_REG_START 0x5880
53 #define SDMA0_HYP_DEC_REG_END 0x5893
54 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
55
56 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
57 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
58 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
59 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
60
sdma_v5_2_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)61 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
62 {
63 u32 base;
64
65 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
66 internal_offset <= SDMA0_HYP_DEC_REG_END) {
67 base = adev->reg_offset[GC_HWIP][0][1];
68 if (instance != 0)
69 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
70 } else {
71 if (instance < 2) {
72 base = adev->reg_offset[GC_HWIP][0][0];
73 if (instance == 1)
74 internal_offset += SDMA1_REG_OFFSET;
75 } else {
76 base = adev->reg_offset[GC_HWIP][0][2];
77 if (instance == 3)
78 internal_offset += SDMA3_REG_OFFSET;
79 }
80 }
81
82 return base + internal_offset;
83 }
84
sdma_v5_2_init_golden_registers(struct amdgpu_device * adev)85 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
86 {
87 switch (adev->asic_type) {
88 case CHIP_SIENNA_CICHLID:
89 case CHIP_NAVY_FLOUNDER:
90 break;
91 default:
92 break;
93 }
94 }
95
sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance * sdma_inst)96 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
97 {
98 int err = 0;
99 const struct sdma_firmware_header_v1_0 *hdr;
100
101 err = amdgpu_ucode_validate(sdma_inst->fw);
102 if (err)
103 return err;
104
105 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
106 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
107 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
108
109 if (sdma_inst->feature_version >= 20)
110 sdma_inst->burst_nop = true;
111
112 return 0;
113 }
114
sdma_v5_2_destroy_inst_ctx(struct amdgpu_device * adev)115 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
116 {
117 int i;
118
119 for (i = 0; i < adev->sdma.num_instances; i++) {
120 release_firmware(adev->sdma.instance[i].fw);
121 adev->sdma.instance[i].fw = NULL;
122
123 if (adev->asic_type == CHIP_SIENNA_CICHLID)
124 break;
125 }
126
127 memset((void*)adev->sdma.instance, 0,
128 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
129 }
130
131 /**
132 * sdma_v5_2_init_microcode - load ucode images from disk
133 *
134 * @adev: amdgpu_device pointer
135 *
136 * Use the firmware interface to load the ucode images into
137 * the driver (not loaded into hw).
138 * Returns 0 on success, error on failure.
139 */
140
141 // emulation only, won't work on real chip
142 // navi10 real chip need to use PSP to load firmware
sdma_v5_2_init_microcode(struct amdgpu_device * adev)143 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
144 {
145 const char *chip_name;
146 char fw_name[40];
147 int err = 0, i;
148 struct amdgpu_firmware_info *info = NULL;
149 const struct common_firmware_header *header = NULL;
150
151 if (amdgpu_sriov_vf(adev))
152 return 0;
153
154 DRM_DEBUG("\n");
155
156 switch (adev->asic_type) {
157 case CHIP_SIENNA_CICHLID:
158 chip_name = "sienna_cichlid";
159 break;
160 case CHIP_NAVY_FLOUNDER:
161 chip_name = "navy_flounder";
162 break;
163 default:
164 BUG();
165 }
166
167 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
168
169 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
170 if (err)
171 goto out;
172
173 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
174 if (err)
175 goto out;
176
177 for (i = 1; i < adev->sdma.num_instances; i++) {
178 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
179 adev->asic_type == CHIP_NAVY_FLOUNDER) {
180 memcpy((void*)&adev->sdma.instance[i],
181 (void*)&adev->sdma.instance[0],
182 sizeof(struct amdgpu_sdma_instance));
183 } else {
184 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
185 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
186 if (err)
187 goto out;
188
189 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[i]);
190 if (err)
191 goto out;
192 }
193 }
194
195 DRM_DEBUG("psp_load == '%s'\n",
196 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
197
198 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
199 for (i = 0; i < adev->sdma.num_instances; i++) {
200 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
201 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
202 info->fw = adev->sdma.instance[i].fw;
203 header = (const struct common_firmware_header *)info->fw->data;
204 adev->firmware.fw_size +=
205 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
206 }
207 }
208
209 out:
210 if (err) {
211 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
212 sdma_v5_2_destroy_inst_ctx(adev);
213 }
214 return err;
215 }
216
sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring * ring)217 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
218 {
219 unsigned ret;
220
221 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
222 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
223 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
224 amdgpu_ring_write(ring, 1);
225 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
226 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
227
228 return ret;
229 }
230
sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)231 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
232 unsigned offset)
233 {
234 unsigned cur;
235
236 BUG_ON(offset > ring->buf_mask);
237 BUG_ON(ring->ring[offset] != 0x55aa55aa);
238
239 cur = (ring->wptr - 1) & ring->buf_mask;
240 if (cur > offset)
241 ring->ring[offset] = cur - offset;
242 else
243 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
244 }
245
246 /**
247 * sdma_v5_2_ring_get_rptr - get the current read pointer
248 *
249 * @ring: amdgpu ring pointer
250 *
251 * Get the current rptr from the hardware (NAVI10+).
252 */
sdma_v5_2_ring_get_rptr(struct amdgpu_ring * ring)253 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
254 {
255 u64 *rptr;
256
257 /* XXX check if swapping is necessary on BE */
258 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
259
260 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
261 return ((*rptr) >> 2);
262 }
263
264 /**
265 * sdma_v5_2_ring_get_wptr - get the current write pointer
266 *
267 * @ring: amdgpu ring pointer
268 *
269 * Get the current wptr from the hardware (NAVI10+).
270 */
sdma_v5_2_ring_get_wptr(struct amdgpu_ring * ring)271 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
272 {
273 struct amdgpu_device *adev = ring->adev;
274 u64 wptr;
275
276 if (ring->use_doorbell) {
277 /* XXX check if swapping is necessary on BE */
278 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
279 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
280 } else {
281 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
282 wptr = wptr << 32;
283 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
284 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
285 }
286
287 return wptr >> 2;
288 }
289
290 /**
291 * sdma_v5_2_ring_set_wptr - commit the write pointer
292 *
293 * @ring: amdgpu ring pointer
294 *
295 * Write the wptr back to the hardware (NAVI10+).
296 */
sdma_v5_2_ring_set_wptr(struct amdgpu_ring * ring)297 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
298 {
299 struct amdgpu_device *adev = ring->adev;
300
301 DRM_DEBUG("Setting write pointer\n");
302 if (ring->use_doorbell) {
303 DRM_DEBUG("Using doorbell -- "
304 "wptr_offs == 0x%08x "
305 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
306 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
307 ring->wptr_offs,
308 lower_32_bits(ring->wptr << 2),
309 upper_32_bits(ring->wptr << 2));
310 /* XXX check if swapping is necessary on BE */
311 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
312 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
313 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
314 ring->doorbell_index, ring->wptr << 2);
315 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
316 } else {
317 DRM_DEBUG("Not using doorbell -- "
318 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
319 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
320 ring->me,
321 lower_32_bits(ring->wptr << 2),
322 ring->me,
323 upper_32_bits(ring->wptr << 2));
324 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
325 lower_32_bits(ring->wptr << 2));
326 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
327 upper_32_bits(ring->wptr << 2));
328 }
329 }
330
sdma_v5_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)331 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
332 {
333 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
334 int i;
335
336 for (i = 0; i < count; i++)
337 if (sdma && sdma->burst_nop && (i == 0))
338 amdgpu_ring_write(ring, ring->funcs->nop |
339 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
340 else
341 amdgpu_ring_write(ring, ring->funcs->nop);
342 }
343
344 /**
345 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
346 *
347 * @ring: amdgpu ring pointer
348 * @ib: IB object to schedule
349 *
350 * Schedule an IB in the DMA ring.
351 */
sdma_v5_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)352 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
353 struct amdgpu_job *job,
354 struct amdgpu_ib *ib,
355 uint32_t flags)
356 {
357 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
358 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
359
360 /* An IB packet must end on a 8 DW boundary--the next dword
361 * must be on a 8-dword boundary. Our IB packet below is 6
362 * dwords long, thus add x number of NOPs, such that, in
363 * modular arithmetic,
364 * wptr + 6 + x = 8k, k >= 0, which in C is,
365 * (wptr + 6 + x) % 8 = 0.
366 * The expression below, is a solution of x.
367 */
368 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
369
370 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
371 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
372 /* base must be 32 byte aligned */
373 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
374 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
375 amdgpu_ring_write(ring, ib->length_dw);
376 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
377 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
378 }
379
380 /**
381 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
382 *
383 * @ring: amdgpu ring pointer
384 *
385 * Emit an hdp flush packet on the requested DMA ring.
386 */
sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring * ring)387 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
388 {
389 struct amdgpu_device *adev = ring->adev;
390 u32 ref_and_mask = 0;
391 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
392
393 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
394
395 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
396 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
397 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
398 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
399 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
400 amdgpu_ring_write(ring, ref_and_mask); /* reference */
401 amdgpu_ring_write(ring, ref_and_mask); /* mask */
402 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
403 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
404 }
405
406 /**
407 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
408 *
409 * @ring: amdgpu ring pointer
410 * @fence: amdgpu fence object
411 *
412 * Add a DMA fence packet to the ring to write
413 * the fence seq number and DMA trap packet to generate
414 * an interrupt if needed.
415 */
sdma_v5_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)416 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
417 unsigned flags)
418 {
419 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
420 /* write the fence */
421 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
422 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
423 /* zero in first two bits */
424 BUG_ON(addr & 0x3);
425 amdgpu_ring_write(ring, lower_32_bits(addr));
426 amdgpu_ring_write(ring, upper_32_bits(addr));
427 amdgpu_ring_write(ring, lower_32_bits(seq));
428
429 /* optionally write high bits as well */
430 if (write64bit) {
431 addr += 4;
432 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
433 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
434 /* zero in first two bits */
435 BUG_ON(addr & 0x3);
436 amdgpu_ring_write(ring, lower_32_bits(addr));
437 amdgpu_ring_write(ring, upper_32_bits(addr));
438 amdgpu_ring_write(ring, upper_32_bits(seq));
439 }
440
441 if (flags & AMDGPU_FENCE_FLAG_INT) {
442 /* generate an interrupt */
443 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
444 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
445 }
446 }
447
448
449 /**
450 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
451 *
452 * @adev: amdgpu_device pointer
453 *
454 * Stop the gfx async dma ring buffers.
455 */
sdma_v5_2_gfx_stop(struct amdgpu_device * adev)456 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
457 {
458 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
459 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
460 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
461 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
462 u32 rb_cntl, ib_cntl;
463 int i;
464
465 if ((adev->mman.buffer_funcs_ring == sdma0) ||
466 (adev->mman.buffer_funcs_ring == sdma1) ||
467 (adev->mman.buffer_funcs_ring == sdma2) ||
468 (adev->mman.buffer_funcs_ring == sdma3))
469 amdgpu_ttm_set_buffer_funcs_status(adev, false);
470
471 for (i = 0; i < adev->sdma.num_instances; i++) {
472 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
473 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
474 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
475 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
476 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
477 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
478 }
479 }
480
481 /**
482 * sdma_v5_2_rlc_stop - stop the compute async dma engines
483 *
484 * @adev: amdgpu_device pointer
485 *
486 * Stop the compute async dma queues.
487 */
sdma_v5_2_rlc_stop(struct amdgpu_device * adev)488 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
489 {
490 /* XXX todo */
491 }
492
493 /**
494 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
495 *
496 * @adev: amdgpu_device pointer
497 * @enable: enable/disable the DMA MEs context switch.
498 *
499 * Halt or unhalt the async dma engines context switch.
500 */
sdma_v5_2_ctx_switch_enable(struct amdgpu_device * adev,bool enable)501 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
502 {
503 u32 f32_cntl, phase_quantum = 0;
504 int i;
505
506 if (amdgpu_sdma_phase_quantum) {
507 unsigned value = amdgpu_sdma_phase_quantum;
508 unsigned unit = 0;
509
510 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
511 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
512 value = (value + 1) >> 1;
513 unit++;
514 }
515 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
516 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
517 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
518 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
519 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
520 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
521 WARN_ONCE(1,
522 "clamping sdma_phase_quantum to %uK clock cycles\n",
523 value << unit);
524 }
525 phase_quantum =
526 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
527 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
528 }
529
530 for (i = 0; i < adev->sdma.num_instances; i++) {
531 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
532 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
533 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
534 if (enable && amdgpu_sdma_phase_quantum) {
535 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
536 phase_quantum);
537 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
538 phase_quantum);
539 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
540 phase_quantum);
541 }
542 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
543 }
544
545 }
546
547 /**
548 * sdma_v5_2_enable - stop the async dma engines
549 *
550 * @adev: amdgpu_device pointer
551 * @enable: enable/disable the DMA MEs.
552 *
553 * Halt or unhalt the async dma engines.
554 */
sdma_v5_2_enable(struct amdgpu_device * adev,bool enable)555 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
556 {
557 u32 f32_cntl;
558 int i;
559
560 if (!enable) {
561 sdma_v5_2_gfx_stop(adev);
562 sdma_v5_2_rlc_stop(adev);
563 }
564
565 for (i = 0; i < adev->sdma.num_instances; i++) {
566 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
567 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
568 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
569 }
570 }
571
572 /**
573 * sdma_v5_2_gfx_resume - setup and start the async dma engines
574 *
575 * @adev: amdgpu_device pointer
576 *
577 * Set up the gfx DMA ring buffers and enable them.
578 * Returns 0 for success, error for failure.
579 */
sdma_v5_2_gfx_resume(struct amdgpu_device * adev)580 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
581 {
582 struct amdgpu_ring *ring;
583 u32 rb_cntl, ib_cntl;
584 u32 rb_bufsz;
585 u32 wb_offset;
586 u32 doorbell;
587 u32 doorbell_offset;
588 u32 temp;
589 u32 wptr_poll_cntl;
590 u64 wptr_gpu_addr;
591 int i, r;
592
593 for (i = 0; i < adev->sdma.num_instances; i++) {
594 ring = &adev->sdma.instance[i].ring;
595 wb_offset = (ring->rptr_offs * 4);
596
597 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
598
599 /* Set ring buffer size in dwords */
600 rb_bufsz = order_base_2(ring->ring_size / 4);
601 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
602 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
603 #ifdef __BIG_ENDIAN
604 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
605 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
606 RPTR_WRITEBACK_SWAP_ENABLE, 1);
607 #endif
608 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
609
610 /* Initialize the ring buffer's read and write pointers */
611 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
612 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
613 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
614 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
615
616 /* setup the wptr shadow polling */
617 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
618 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
619 lower_32_bits(wptr_gpu_addr));
620 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
621 upper_32_bits(wptr_gpu_addr));
622 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
623 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
624 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
625 SDMA0_GFX_RB_WPTR_POLL_CNTL,
626 F32_POLL_ENABLE, 1);
627 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
628 wptr_poll_cntl);
629
630 /* set the wb address whether it's enabled or not */
631 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
632 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
633 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
634 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
635
636 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
637
638 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
639 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
640
641 ring->wptr = 0;
642
643 /* before programing wptr to a less value, need set minor_ptr_update first */
644 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
645
646 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
647 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
648 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
649 }
650
651 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
652 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
653
654 if (ring->use_doorbell) {
655 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
656 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
657 OFFSET, ring->doorbell_index);
658 } else {
659 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
660 }
661 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
662 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
663
664 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
665 ring->doorbell_index,
666 adev->doorbell_index.sdma_doorbell_range);
667
668 if (amdgpu_sriov_vf(adev))
669 sdma_v5_2_ring_set_wptr(ring);
670
671 /* set minor_ptr_update to 0 after wptr programed */
672 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
673
674 /* set utc l1 enable flag always to 1 */
675 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
676 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
677
678 /* enable MCBP */
679 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
680 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
681
682 /* Set up RESP_MODE to non-copy addresses */
683 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
684 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
685 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
686 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
687
688 /* program default cache read and write policy */
689 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
690 /* clean read policy and write policy bits */
691 temp &= 0xFF0FFF;
692 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
693 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
694 0x01000000);
695 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
696
697 if (!amdgpu_sriov_vf(adev)) {
698 /* unhalt engine */
699 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
700 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
701 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
702 }
703
704 /* enable DMA RB */
705 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
706 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
707
708 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
709 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
710 #ifdef __BIG_ENDIAN
711 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
712 #endif
713 /* enable DMA IBs */
714 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
715
716 ring->sched.ready = true;
717
718 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
719 sdma_v5_2_ctx_switch_enable(adev, true);
720 sdma_v5_2_enable(adev, true);
721 }
722
723 r = amdgpu_ring_test_ring(ring);
724 if (r) {
725 ring->sched.ready = false;
726 return r;
727 }
728
729 if (adev->mman.buffer_funcs_ring == ring)
730 amdgpu_ttm_set_buffer_funcs_status(adev, true);
731 }
732
733 return 0;
734 }
735
736 /**
737 * sdma_v5_2_rlc_resume - setup and start the async dma engines
738 *
739 * @adev: amdgpu_device pointer
740 *
741 * Set up the compute DMA queues and enable them.
742 * Returns 0 for success, error for failure.
743 */
sdma_v5_2_rlc_resume(struct amdgpu_device * adev)744 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
745 {
746 return 0;
747 }
748
749 /**
750 * sdma_v5_2_load_microcode - load the sDMA ME ucode
751 *
752 * @adev: amdgpu_device pointer
753 *
754 * Loads the sDMA0/1/2/3 ucode.
755 * Returns 0 for success, -EINVAL if the ucode is not available.
756 */
sdma_v5_2_load_microcode(struct amdgpu_device * adev)757 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
758 {
759 const struct sdma_firmware_header_v1_0 *hdr;
760 const __le32 *fw_data;
761 u32 fw_size;
762 int i, j;
763
764 /* halt the MEs */
765 sdma_v5_2_enable(adev, false);
766
767 for (i = 0; i < adev->sdma.num_instances; i++) {
768 if (!adev->sdma.instance[i].fw)
769 return -EINVAL;
770
771 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
772 amdgpu_ucode_print_sdma_hdr(&hdr->header);
773 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
774
775 fw_data = (const __le32 *)
776 (adev->sdma.instance[i].fw->data +
777 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
778
779 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
780
781 for (j = 0; j < fw_size; j++) {
782 if (amdgpu_emu_mode == 1 && j % 500 == 0)
783 msleep(1);
784 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
785 }
786
787 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
788 }
789
790 return 0;
791 }
792
793 /**
794 * sdma_v5_2_start - setup and start the async dma engines
795 *
796 * @adev: amdgpu_device pointer
797 *
798 * Set up the DMA engines and enable them.
799 * Returns 0 for success, error for failure.
800 */
sdma_v5_2_start(struct amdgpu_device * adev)801 static int sdma_v5_2_start(struct amdgpu_device *adev)
802 {
803 int r = 0;
804
805 if (amdgpu_sriov_vf(adev)) {
806 sdma_v5_2_ctx_switch_enable(adev, false);
807 sdma_v5_2_enable(adev, false);
808
809 /* set RB registers */
810 r = sdma_v5_2_gfx_resume(adev);
811 return r;
812 }
813
814 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
815 r = sdma_v5_2_load_microcode(adev);
816 if (r)
817 return r;
818
819 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
820 if (amdgpu_emu_mode == 1)
821 msleep(1000);
822 }
823
824 /* unhalt the MEs */
825 sdma_v5_2_enable(adev, true);
826 /* enable sdma ring preemption */
827 sdma_v5_2_ctx_switch_enable(adev, true);
828
829 /* start the gfx rings and rlc compute queues */
830 r = sdma_v5_2_gfx_resume(adev);
831 if (r)
832 return r;
833 r = sdma_v5_2_rlc_resume(adev);
834
835 return r;
836 }
837
838 /**
839 * sdma_v5_2_ring_test_ring - simple async dma engine test
840 *
841 * @ring: amdgpu_ring structure holding ring information
842 *
843 * Test the DMA engine by writing using it to write an
844 * value to memory.
845 * Returns 0 for success, error for failure.
846 */
sdma_v5_2_ring_test_ring(struct amdgpu_ring * ring)847 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
848 {
849 struct amdgpu_device *adev = ring->adev;
850 unsigned i;
851 unsigned index;
852 int r;
853 u32 tmp;
854 u64 gpu_addr;
855
856 r = amdgpu_device_wb_get(adev, &index);
857 if (r) {
858 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
859 return r;
860 }
861
862 gpu_addr = adev->wb.gpu_addr + (index * 4);
863 tmp = 0xCAFEDEAD;
864 adev->wb.wb[index] = cpu_to_le32(tmp);
865
866 r = amdgpu_ring_alloc(ring, 5);
867 if (r) {
868 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
869 amdgpu_device_wb_free(adev, index);
870 return r;
871 }
872
873 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
874 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
875 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
876 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
877 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
878 amdgpu_ring_write(ring, 0xDEADBEEF);
879 amdgpu_ring_commit(ring);
880
881 for (i = 0; i < adev->usec_timeout; i++) {
882 tmp = le32_to_cpu(adev->wb.wb[index]);
883 if (tmp == 0xDEADBEEF)
884 break;
885 if (amdgpu_emu_mode == 1)
886 msleep(1);
887 else
888 udelay(1);
889 }
890
891 if (i >= adev->usec_timeout)
892 r = -ETIMEDOUT;
893
894 amdgpu_device_wb_free(adev, index);
895
896 return r;
897 }
898
899 /**
900 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
901 *
902 * @ring: amdgpu_ring structure holding ring information
903 *
904 * Test a simple IB in the DMA ring.
905 * Returns 0 on success, error on failure.
906 */
sdma_v5_2_ring_test_ib(struct amdgpu_ring * ring,long timeout)907 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
908 {
909 struct amdgpu_device *adev = ring->adev;
910 struct amdgpu_ib ib;
911 struct dma_fence *f = NULL;
912 unsigned index;
913 long r;
914 u32 tmp = 0;
915 u64 gpu_addr;
916
917 r = amdgpu_device_wb_get(adev, &index);
918 if (r) {
919 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
920 return r;
921 }
922
923 gpu_addr = adev->wb.gpu_addr + (index * 4);
924 tmp = 0xCAFEDEAD;
925 adev->wb.wb[index] = cpu_to_le32(tmp);
926 memset(&ib, 0, sizeof(ib));
927 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
928 if (r) {
929 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
930 goto err0;
931 }
932
933 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
934 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
935 ib.ptr[1] = lower_32_bits(gpu_addr);
936 ib.ptr[2] = upper_32_bits(gpu_addr);
937 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
938 ib.ptr[4] = 0xDEADBEEF;
939 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
940 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
941 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
942 ib.length_dw = 8;
943
944 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
945 if (r)
946 goto err1;
947
948 r = dma_fence_wait_timeout(f, false, timeout);
949 if (r == 0) {
950 DRM_ERROR("amdgpu: IB test timed out\n");
951 r = -ETIMEDOUT;
952 goto err1;
953 } else if (r < 0) {
954 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
955 goto err1;
956 }
957 tmp = le32_to_cpu(adev->wb.wb[index]);
958 if (tmp == 0xDEADBEEF)
959 r = 0;
960 else
961 r = -EINVAL;
962
963 err1:
964 amdgpu_ib_free(adev, &ib, NULL);
965 dma_fence_put(f);
966 err0:
967 amdgpu_device_wb_free(adev, index);
968 return r;
969 }
970
971
972 /**
973 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
974 *
975 * @ib: indirect buffer to fill with commands
976 * @pe: addr of the page entry
977 * @src: src addr to copy from
978 * @count: number of page entries to update
979 *
980 * Update PTEs by copying them from the GART using sDMA.
981 */
sdma_v5_2_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)982 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
983 uint64_t pe, uint64_t src,
984 unsigned count)
985 {
986 unsigned bytes = count * 8;
987
988 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
989 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
990 ib->ptr[ib->length_dw++] = bytes - 1;
991 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
992 ib->ptr[ib->length_dw++] = lower_32_bits(src);
993 ib->ptr[ib->length_dw++] = upper_32_bits(src);
994 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
995 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
996
997 }
998
999 /**
1000 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1001 *
1002 * @ib: indirect buffer to fill with commands
1003 * @pe: addr of the page entry
1004 * @addr: dst addr to write into pe
1005 * @count: number of page entries to update
1006 * @incr: increase next addr by incr bytes
1007 * @flags: access flags
1008 *
1009 * Update PTEs by writing them manually using sDMA.
1010 */
sdma_v5_2_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1011 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1012 uint64_t value, unsigned count,
1013 uint32_t incr)
1014 {
1015 unsigned ndw = count * 2;
1016
1017 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1018 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1019 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1020 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1021 ib->ptr[ib->length_dw++] = ndw - 1;
1022 for (; ndw > 0; ndw -= 2) {
1023 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1024 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1025 value += incr;
1026 }
1027 }
1028
1029 /**
1030 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1031 *
1032 * @ib: indirect buffer to fill with commands
1033 * @pe: addr of the page entry
1034 * @addr: dst addr to write into pe
1035 * @count: number of page entries to update
1036 * @incr: increase next addr by incr bytes
1037 * @flags: access flags
1038 *
1039 * Update the page tables using sDMA.
1040 */
sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1041 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1042 uint64_t pe,
1043 uint64_t addr, unsigned count,
1044 uint32_t incr, uint64_t flags)
1045 {
1046 /* for physically contiguous pages (vram) */
1047 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1048 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1049 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1050 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1051 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1052 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1053 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1054 ib->ptr[ib->length_dw++] = incr; /* increment size */
1055 ib->ptr[ib->length_dw++] = 0;
1056 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1057 }
1058
1059 /**
1060 * sdma_v5_2_ring_pad_ib - pad the IB
1061 *
1062 * @ib: indirect buffer to fill with padding
1063 *
1064 * Pad the IB with NOPs to a boundary multiple of 8.
1065 */
sdma_v5_2_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1066 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1067 {
1068 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1069 u32 pad_count;
1070 int i;
1071
1072 pad_count = (-ib->length_dw) & 0x7;
1073 for (i = 0; i < pad_count; i++)
1074 if (sdma && sdma->burst_nop && (i == 0))
1075 ib->ptr[ib->length_dw++] =
1076 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1077 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1078 else
1079 ib->ptr[ib->length_dw++] =
1080 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1081 }
1082
1083
1084 /**
1085 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1086 *
1087 * @ring: amdgpu_ring pointer
1088 *
1089 * Make sure all previous operations are completed (CIK).
1090 */
sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1091 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1092 {
1093 uint32_t seq = ring->fence_drv.sync_seq;
1094 uint64_t addr = ring->fence_drv.gpu_addr;
1095
1096 /* wait for idle */
1097 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1098 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1099 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1100 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1101 amdgpu_ring_write(ring, addr & 0xfffffffc);
1102 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1103 amdgpu_ring_write(ring, seq); /* reference */
1104 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1105 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1106 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1107 }
1108
1109
1110 /**
1111 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1112 *
1113 * @ring: amdgpu_ring pointer
1114 * @vm: amdgpu_vm pointer
1115 *
1116 * Update the page table base and flush the VM TLB
1117 * using sDMA.
1118 */
sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1119 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1120 unsigned vmid, uint64_t pd_addr)
1121 {
1122 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1123 }
1124
sdma_v5_2_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1125 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1126 uint32_t reg, uint32_t val)
1127 {
1128 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1129 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1130 amdgpu_ring_write(ring, reg);
1131 amdgpu_ring_write(ring, val);
1132 }
1133
sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1134 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1135 uint32_t val, uint32_t mask)
1136 {
1137 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1138 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1139 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1140 amdgpu_ring_write(ring, reg << 2);
1141 amdgpu_ring_write(ring, 0);
1142 amdgpu_ring_write(ring, val); /* reference */
1143 amdgpu_ring_write(ring, mask); /* mask */
1144 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1145 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1146 }
1147
sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1148 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1149 uint32_t reg0, uint32_t reg1,
1150 uint32_t ref, uint32_t mask)
1151 {
1152 amdgpu_ring_emit_wreg(ring, reg0, ref);
1153 /* wait for a cycle to reset vm_inv_eng*_ack */
1154 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1155 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1156 }
1157
sdma_v5_2_early_init(void * handle)1158 static int sdma_v5_2_early_init(void *handle)
1159 {
1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1161
1162 switch (adev->asic_type) {
1163 case CHIP_SIENNA_CICHLID:
1164 adev->sdma.num_instances = 4;
1165 break;
1166 case CHIP_NAVY_FLOUNDER:
1167 adev->sdma.num_instances = 2;
1168 break;
1169 default:
1170 break;
1171 }
1172
1173 sdma_v5_2_set_ring_funcs(adev);
1174 sdma_v5_2_set_buffer_funcs(adev);
1175 sdma_v5_2_set_vm_pte_funcs(adev);
1176 sdma_v5_2_set_irq_funcs(adev);
1177
1178 return 0;
1179 }
1180
sdma_v5_2_seq_to_irq_id(int seq_num)1181 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1182 {
1183 switch (seq_num) {
1184 case 0:
1185 return SOC15_IH_CLIENTID_SDMA0;
1186 case 1:
1187 return SOC15_IH_CLIENTID_SDMA1;
1188 case 2:
1189 return SOC15_IH_CLIENTID_SDMA2;
1190 case 3:
1191 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1192 default:
1193 break;
1194 }
1195 return -EINVAL;
1196 }
1197
sdma_v5_2_seq_to_trap_id(int seq_num)1198 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1199 {
1200 switch (seq_num) {
1201 case 0:
1202 return SDMA0_5_0__SRCID__SDMA_TRAP;
1203 case 1:
1204 return SDMA1_5_0__SRCID__SDMA_TRAP;
1205 case 2:
1206 return SDMA2_5_0__SRCID__SDMA_TRAP;
1207 case 3:
1208 return SDMA3_5_0__SRCID__SDMA_TRAP;
1209 default:
1210 break;
1211 }
1212 return -EINVAL;
1213 }
1214
sdma_v5_2_sw_init(void * handle)1215 static int sdma_v5_2_sw_init(void *handle)
1216 {
1217 struct amdgpu_ring *ring;
1218 int r, i;
1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
1221 /* SDMA trap event */
1222 for (i = 0; i < adev->sdma.num_instances; i++) {
1223 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1224 sdma_v5_2_seq_to_trap_id(i),
1225 &adev->sdma.trap_irq);
1226 if (r)
1227 return r;
1228 }
1229
1230 r = sdma_v5_2_init_microcode(adev);
1231 if (r) {
1232 DRM_ERROR("Failed to load sdma firmware!\n");
1233 return r;
1234 }
1235
1236 for (i = 0; i < adev->sdma.num_instances; i++) {
1237 ring = &adev->sdma.instance[i].ring;
1238 ring->ring_obj = NULL;
1239 ring->use_doorbell = true;
1240 ring->me = i;
1241
1242 DRM_INFO("use_doorbell being set to: [%s]\n",
1243 ring->use_doorbell?"true":"false");
1244
1245 ring->doorbell_index =
1246 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1247
1248 sprintf(ring->name, "sdma%d", i);
1249 r = amdgpu_ring_init(adev, ring, 1024,
1250 &adev->sdma.trap_irq,
1251 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1252 AMDGPU_RING_PRIO_DEFAULT);
1253 if (r)
1254 return r;
1255 }
1256
1257 return r;
1258 }
1259
sdma_v5_2_sw_fini(void * handle)1260 static int sdma_v5_2_sw_fini(void *handle)
1261 {
1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263 int i;
1264
1265 for (i = 0; i < adev->sdma.num_instances; i++)
1266 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1267
1268 sdma_v5_2_destroy_inst_ctx(adev);
1269
1270 return 0;
1271 }
1272
sdma_v5_2_hw_init(void * handle)1273 static int sdma_v5_2_hw_init(void *handle)
1274 {
1275 int r;
1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277
1278 sdma_v5_2_init_golden_registers(adev);
1279
1280 r = sdma_v5_2_start(adev);
1281
1282 return r;
1283 }
1284
sdma_v5_2_hw_fini(void * handle)1285 static int sdma_v5_2_hw_fini(void *handle)
1286 {
1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288
1289 if (amdgpu_sriov_vf(adev))
1290 return 0;
1291
1292 sdma_v5_2_ctx_switch_enable(adev, false);
1293 sdma_v5_2_enable(adev, false);
1294
1295 return 0;
1296 }
1297
sdma_v5_2_suspend(void * handle)1298 static int sdma_v5_2_suspend(void *handle)
1299 {
1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1301
1302 return sdma_v5_2_hw_fini(adev);
1303 }
1304
sdma_v5_2_resume(void * handle)1305 static int sdma_v5_2_resume(void *handle)
1306 {
1307 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1308
1309 return sdma_v5_2_hw_init(adev);
1310 }
1311
sdma_v5_2_is_idle(void * handle)1312 static bool sdma_v5_2_is_idle(void *handle)
1313 {
1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1315 u32 i;
1316
1317 for (i = 0; i < adev->sdma.num_instances; i++) {
1318 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1319
1320 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1321 return false;
1322 }
1323
1324 return true;
1325 }
1326
sdma_v5_2_wait_for_idle(void * handle)1327 static int sdma_v5_2_wait_for_idle(void *handle)
1328 {
1329 unsigned i;
1330 u32 sdma0, sdma1, sdma2, sdma3;
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1332
1333 for (i = 0; i < adev->usec_timeout; i++) {
1334 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1335 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1336 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1337 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1338
1339 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1340 return 0;
1341 udelay(1);
1342 }
1343 return -ETIMEDOUT;
1344 }
1345
sdma_v5_2_soft_reset(void * handle)1346 static int sdma_v5_2_soft_reset(void *handle)
1347 {
1348 /* todo */
1349
1350 return 0;
1351 }
1352
sdma_v5_2_ring_preempt_ib(struct amdgpu_ring * ring)1353 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1354 {
1355 int i, r = 0;
1356 struct amdgpu_device *adev = ring->adev;
1357 u32 index = 0;
1358 u64 sdma_gfx_preempt;
1359
1360 amdgpu_sdma_get_index_from_ring(ring, &index);
1361 sdma_gfx_preempt =
1362 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1363
1364 /* assert preemption condition */
1365 amdgpu_ring_set_preempt_cond_exec(ring, false);
1366
1367 /* emit the trailing fence */
1368 ring->trail_seq += 1;
1369 amdgpu_ring_alloc(ring, 10);
1370 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1371 ring->trail_seq, 0);
1372 amdgpu_ring_commit(ring);
1373
1374 /* assert IB preemption */
1375 WREG32(sdma_gfx_preempt, 1);
1376
1377 /* poll the trailing fence */
1378 for (i = 0; i < adev->usec_timeout; i++) {
1379 if (ring->trail_seq ==
1380 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1381 break;
1382 udelay(1);
1383 }
1384
1385 if (i >= adev->usec_timeout) {
1386 r = -EINVAL;
1387 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1388 }
1389
1390 /* deassert IB preemption */
1391 WREG32(sdma_gfx_preempt, 0);
1392
1393 /* deassert the preemption condition */
1394 amdgpu_ring_set_preempt_cond_exec(ring, true);
1395 return r;
1396 }
1397
sdma_v5_2_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1398 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1399 struct amdgpu_irq_src *source,
1400 unsigned type,
1401 enum amdgpu_interrupt_state state)
1402 {
1403 u32 sdma_cntl;
1404
1405 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1406
1407 sdma_cntl = RREG32(reg_offset);
1408 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1409 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1410 WREG32(reg_offset, sdma_cntl);
1411
1412 return 0;
1413 }
1414
sdma_v5_2_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1415 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1416 struct amdgpu_irq_src *source,
1417 struct amdgpu_iv_entry *entry)
1418 {
1419 DRM_DEBUG("IH: SDMA trap\n");
1420 switch (entry->client_id) {
1421 case SOC15_IH_CLIENTID_SDMA0:
1422 switch (entry->ring_id) {
1423 case 0:
1424 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1425 break;
1426 case 1:
1427 /* XXX compute */
1428 break;
1429 case 2:
1430 /* XXX compute */
1431 break;
1432 case 3:
1433 /* XXX page queue*/
1434 break;
1435 }
1436 break;
1437 case SOC15_IH_CLIENTID_SDMA1:
1438 switch (entry->ring_id) {
1439 case 0:
1440 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1441 break;
1442 case 1:
1443 /* XXX compute */
1444 break;
1445 case 2:
1446 /* XXX compute */
1447 break;
1448 case 3:
1449 /* XXX page queue*/
1450 break;
1451 }
1452 break;
1453 case SOC15_IH_CLIENTID_SDMA2:
1454 switch (entry->ring_id) {
1455 case 0:
1456 amdgpu_fence_process(&adev->sdma.instance[2].ring);
1457 break;
1458 case 1:
1459 /* XXX compute */
1460 break;
1461 case 2:
1462 /* XXX compute */
1463 break;
1464 case 3:
1465 /* XXX page queue*/
1466 break;
1467 }
1468 break;
1469 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1470 switch (entry->ring_id) {
1471 case 0:
1472 amdgpu_fence_process(&adev->sdma.instance[3].ring);
1473 break;
1474 case 1:
1475 /* XXX compute */
1476 break;
1477 case 2:
1478 /* XXX compute */
1479 break;
1480 case 3:
1481 /* XXX page queue*/
1482 break;
1483 }
1484 break;
1485 }
1486 return 0;
1487 }
1488
sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1489 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1490 struct amdgpu_irq_src *source,
1491 struct amdgpu_iv_entry *entry)
1492 {
1493 return 0;
1494 }
1495
sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1496 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1497 bool enable)
1498 {
1499 uint32_t data, def;
1500 int i;
1501
1502 for (i = 0; i < adev->sdma.num_instances; i++) {
1503 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1504 /* Enable sdma clock gating */
1505 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1506 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1507 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1508 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1509 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1510 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1511 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1512 if (def != data)
1513 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1514 } else {
1515 /* Disable sdma clock gating */
1516 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1517 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1519 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1520 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1521 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1522 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1523 if (def != data)
1524 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1525 }
1526 }
1527 }
1528
sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1529 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1530 bool enable)
1531 {
1532 uint32_t data, def;
1533 int i;
1534
1535 for (i = 0; i < adev->sdma.num_instances; i++) {
1536 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1537 /* Enable sdma mem light sleep */
1538 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1539 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1540 if (def != data)
1541 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1542
1543 } else {
1544 /* Disable sdma mem light sleep */
1545 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1546 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1547 if (def != data)
1548 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1549
1550 }
1551 }
1552 }
1553
sdma_v5_2_set_clockgating_state(void * handle,enum amd_clockgating_state state)1554 static int sdma_v5_2_set_clockgating_state(void *handle,
1555 enum amd_clockgating_state state)
1556 {
1557 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1558
1559 if (amdgpu_sriov_vf(adev))
1560 return 0;
1561
1562 switch (adev->asic_type) {
1563 case CHIP_SIENNA_CICHLID:
1564 case CHIP_NAVY_FLOUNDER:
1565 sdma_v5_2_update_medium_grain_clock_gating(adev,
1566 state == AMD_CG_STATE_GATE ? true : false);
1567 sdma_v5_2_update_medium_grain_light_sleep(adev,
1568 state == AMD_CG_STATE_GATE ? true : false);
1569 break;
1570 default:
1571 break;
1572 }
1573
1574 return 0;
1575 }
1576
sdma_v5_2_set_powergating_state(void * handle,enum amd_powergating_state state)1577 static int sdma_v5_2_set_powergating_state(void *handle,
1578 enum amd_powergating_state state)
1579 {
1580 return 0;
1581 }
1582
sdma_v5_2_get_clockgating_state(void * handle,u32 * flags)1583 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1584 {
1585 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1586 int data;
1587
1588 if (amdgpu_sriov_vf(adev))
1589 *flags = 0;
1590
1591 /* AMD_CG_SUPPORT_SDMA_LS */
1592 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1593 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1594 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1595 }
1596
1597 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1598 .name = "sdma_v5_2",
1599 .early_init = sdma_v5_2_early_init,
1600 .late_init = NULL,
1601 .sw_init = sdma_v5_2_sw_init,
1602 .sw_fini = sdma_v5_2_sw_fini,
1603 .hw_init = sdma_v5_2_hw_init,
1604 .hw_fini = sdma_v5_2_hw_fini,
1605 .suspend = sdma_v5_2_suspend,
1606 .resume = sdma_v5_2_resume,
1607 .is_idle = sdma_v5_2_is_idle,
1608 .wait_for_idle = sdma_v5_2_wait_for_idle,
1609 .soft_reset = sdma_v5_2_soft_reset,
1610 .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1611 .set_powergating_state = sdma_v5_2_set_powergating_state,
1612 .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1613 };
1614
1615 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1616 .type = AMDGPU_RING_TYPE_SDMA,
1617 .align_mask = 0xf,
1618 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1619 .support_64bit_ptrs = true,
1620 .vmhub = AMDGPU_GFXHUB_0,
1621 .get_rptr = sdma_v5_2_ring_get_rptr,
1622 .get_wptr = sdma_v5_2_ring_get_wptr,
1623 .set_wptr = sdma_v5_2_ring_set_wptr,
1624 .emit_frame_size =
1625 5 + /* sdma_v5_2_ring_init_cond_exec */
1626 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1627 3 + /* hdp_invalidate */
1628 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1629 /* sdma_v5_2_ring_emit_vm_flush */
1630 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1631 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1632 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1633 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1634 .emit_ib = sdma_v5_2_ring_emit_ib,
1635 .emit_fence = sdma_v5_2_ring_emit_fence,
1636 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1637 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1638 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1639 .test_ring = sdma_v5_2_ring_test_ring,
1640 .test_ib = sdma_v5_2_ring_test_ib,
1641 .insert_nop = sdma_v5_2_ring_insert_nop,
1642 .pad_ib = sdma_v5_2_ring_pad_ib,
1643 .emit_wreg = sdma_v5_2_ring_emit_wreg,
1644 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1645 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1646 .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1647 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1648 .preempt_ib = sdma_v5_2_ring_preempt_ib,
1649 };
1650
sdma_v5_2_set_ring_funcs(struct amdgpu_device * adev)1651 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1652 {
1653 int i;
1654
1655 for (i = 0; i < adev->sdma.num_instances; i++) {
1656 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1657 adev->sdma.instance[i].ring.me = i;
1658 }
1659 }
1660
1661 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1662 .set = sdma_v5_2_set_trap_irq_state,
1663 .process = sdma_v5_2_process_trap_irq,
1664 };
1665
1666 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1667 .process = sdma_v5_2_process_illegal_inst_irq,
1668 };
1669
sdma_v5_2_set_irq_funcs(struct amdgpu_device * adev)1670 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1671 {
1672 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1673 adev->sdma.num_instances;
1674 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1675 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1676 }
1677
1678 /**
1679 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1680 *
1681 * @ring: amdgpu_ring structure holding ring information
1682 * @src_offset: src GPU address
1683 * @dst_offset: dst GPU address
1684 * @byte_count: number of bytes to xfer
1685 *
1686 * Copy GPU buffers using the DMA engine.
1687 * Used by the amdgpu ttm implementation to move pages if
1688 * registered as the asic copy callback.
1689 */
sdma_v5_2_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,bool tmz)1690 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1691 uint64_t src_offset,
1692 uint64_t dst_offset,
1693 uint32_t byte_count,
1694 bool tmz)
1695 {
1696 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1697 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1698 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1699 ib->ptr[ib->length_dw++] = byte_count - 1;
1700 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1701 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1702 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1703 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1704 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1705 }
1706
1707 /**
1708 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1709 *
1710 * @ring: amdgpu_ring structure holding ring information
1711 * @src_data: value to write to buffer
1712 * @dst_offset: dst GPU address
1713 * @byte_count: number of bytes to xfer
1714 *
1715 * Fill GPU buffers using the DMA engine.
1716 */
sdma_v5_2_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1717 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1718 uint32_t src_data,
1719 uint64_t dst_offset,
1720 uint32_t byte_count)
1721 {
1722 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1723 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1724 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1725 ib->ptr[ib->length_dw++] = src_data;
1726 ib->ptr[ib->length_dw++] = byte_count - 1;
1727 }
1728
1729 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1730 .copy_max_bytes = 0x400000,
1731 .copy_num_dw = 7,
1732 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1733
1734 .fill_max_bytes = 0x400000,
1735 .fill_num_dw = 5,
1736 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1737 };
1738
sdma_v5_2_set_buffer_funcs(struct amdgpu_device * adev)1739 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1740 {
1741 if (adev->mman.buffer_funcs == NULL) {
1742 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1743 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1744 }
1745 }
1746
1747 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1748 .copy_pte_num_dw = 7,
1749 .copy_pte = sdma_v5_2_vm_copy_pte,
1750 .write_pte = sdma_v5_2_vm_write_pte,
1751 .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1752 };
1753
sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device * adev)1754 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1755 {
1756 unsigned i;
1757
1758 if (adev->vm_manager.vm_pte_funcs == NULL) {
1759 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1760 for (i = 0; i < adev->sdma.num_instances; i++) {
1761 adev->vm_manager.vm_pte_scheds[i] =
1762 &adev->sdma.instance[i].ring.sched;
1763 }
1764 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1765 }
1766 }
1767
1768 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1769 .type = AMD_IP_BLOCK_TYPE_SDMA,
1770 .major = 5,
1771 .minor = 2,
1772 .rev = 0,
1773 .funcs = &sdma_v5_2_ip_funcs,
1774 };
1775