1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/delay.h>
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/thermal.h>
17
18 #include "etnaviv_cmdbuf.h"
19 #include "etnaviv_dump.h"
20 #include "etnaviv_gpu.h"
21 #include "etnaviv_gem.h"
22 #include "etnaviv_mmu.h"
23 #include "etnaviv_perfmon.h"
24 #include "etnaviv_sched.h"
25 #include "common.xml.h"
26 #include "state.xml.h"
27 #include "state_hi.xml.h"
28 #include "cmdstream.xml.h"
29
30 #ifndef PHYS_OFFSET
31 #define PHYS_OFFSET 0
32 #endif
33
34 static const struct platform_device_id gpu_ids[] = {
35 { .name = "etnaviv-gpu,2d" },
36 { },
37 };
38
39 /*
40 * Driver functions:
41 */
42
etnaviv_gpu_get_param(struct etnaviv_gpu * gpu,u32 param,u64 * value)43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
44 {
45 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
46
47 switch (param) {
48 case ETNAVIV_PARAM_GPU_MODEL:
49 *value = gpu->identity.model;
50 break;
51
52 case ETNAVIV_PARAM_GPU_REVISION:
53 *value = gpu->identity.revision;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_0:
57 *value = gpu->identity.features;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_1:
61 *value = gpu->identity.minor_features0;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_2:
65 *value = gpu->identity.minor_features1;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_3:
69 *value = gpu->identity.minor_features2;
70 break;
71
72 case ETNAVIV_PARAM_GPU_FEATURES_4:
73 *value = gpu->identity.minor_features3;
74 break;
75
76 case ETNAVIV_PARAM_GPU_FEATURES_5:
77 *value = gpu->identity.minor_features4;
78 break;
79
80 case ETNAVIV_PARAM_GPU_FEATURES_6:
81 *value = gpu->identity.minor_features5;
82 break;
83
84 case ETNAVIV_PARAM_GPU_FEATURES_7:
85 *value = gpu->identity.minor_features6;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_8:
89 *value = gpu->identity.minor_features7;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_9:
93 *value = gpu->identity.minor_features8;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_10:
97 *value = gpu->identity.minor_features9;
98 break;
99
100 case ETNAVIV_PARAM_GPU_FEATURES_11:
101 *value = gpu->identity.minor_features10;
102 break;
103
104 case ETNAVIV_PARAM_GPU_FEATURES_12:
105 *value = gpu->identity.minor_features11;
106 break;
107
108 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
109 *value = gpu->identity.stream_count;
110 break;
111
112 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
113 *value = gpu->identity.register_max;
114 break;
115
116 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
117 *value = gpu->identity.thread_count;
118 break;
119
120 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
121 *value = gpu->identity.vertex_cache_size;
122 break;
123
124 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
125 *value = gpu->identity.shader_core_count;
126 break;
127
128 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
129 *value = gpu->identity.pixel_pipes;
130 break;
131
132 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
133 *value = gpu->identity.vertex_output_buffer_size;
134 break;
135
136 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
137 *value = gpu->identity.buffer_size;
138 break;
139
140 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
141 *value = gpu->identity.instruction_count;
142 break;
143
144 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
145 *value = gpu->identity.num_constants;
146 break;
147
148 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
149 *value = gpu->identity.varyings_count;
150 break;
151
152 case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
153 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
154 *value = ETNAVIV_SOFTPIN_START_ADDRESS;
155 else
156 *value = ~0ULL;
157 break;
158
159 default:
160 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
161 return -EINVAL;
162 }
163
164 return 0;
165 }
166
167
168 #define etnaviv_is_model_rev(gpu, mod, rev) \
169 ((gpu)->identity.model == chipModel_##mod && \
170 (gpu)->identity.revision == rev)
171 #define etnaviv_field(val, field) \
172 (((val) & field##__MASK) >> field##__SHIFT)
173
etnaviv_hw_specs(struct etnaviv_gpu * gpu)174 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
175 {
176 if (gpu->identity.minor_features0 &
177 chipMinorFeatures0_MORE_MINOR_FEATURES) {
178 u32 specs[4];
179 unsigned int streams;
180
181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
182 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
183 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
184 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
185
186 gpu->identity.stream_count = etnaviv_field(specs[0],
187 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
188 gpu->identity.register_max = etnaviv_field(specs[0],
189 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
190 gpu->identity.thread_count = etnaviv_field(specs[0],
191 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
192 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
193 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
194 gpu->identity.shader_core_count = etnaviv_field(specs[0],
195 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
196 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
197 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
198 gpu->identity.vertex_output_buffer_size =
199 etnaviv_field(specs[0],
200 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
201
202 gpu->identity.buffer_size = etnaviv_field(specs[1],
203 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
204 gpu->identity.instruction_count = etnaviv_field(specs[1],
205 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
206 gpu->identity.num_constants = etnaviv_field(specs[1],
207 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
208
209 gpu->identity.varyings_count = etnaviv_field(specs[2],
210 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
211
212 /* This overrides the value from older register if non-zero */
213 streams = etnaviv_field(specs[3],
214 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
215 if (streams)
216 gpu->identity.stream_count = streams;
217 }
218
219 /* Fill in the stream count if not specified */
220 if (gpu->identity.stream_count == 0) {
221 if (gpu->identity.model >= 0x1000)
222 gpu->identity.stream_count = 4;
223 else
224 gpu->identity.stream_count = 1;
225 }
226
227 /* Convert the register max value */
228 if (gpu->identity.register_max)
229 gpu->identity.register_max = 1 << gpu->identity.register_max;
230 else if (gpu->identity.model == chipModel_GC400)
231 gpu->identity.register_max = 32;
232 else
233 gpu->identity.register_max = 64;
234
235 /* Convert thread count */
236 if (gpu->identity.thread_count)
237 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
238 else if (gpu->identity.model == chipModel_GC400)
239 gpu->identity.thread_count = 64;
240 else if (gpu->identity.model == chipModel_GC500 ||
241 gpu->identity.model == chipModel_GC530)
242 gpu->identity.thread_count = 128;
243 else
244 gpu->identity.thread_count = 256;
245
246 if (gpu->identity.vertex_cache_size == 0)
247 gpu->identity.vertex_cache_size = 8;
248
249 if (gpu->identity.shader_core_count == 0) {
250 if (gpu->identity.model >= 0x1000)
251 gpu->identity.shader_core_count = 2;
252 else
253 gpu->identity.shader_core_count = 1;
254 }
255
256 if (gpu->identity.pixel_pipes == 0)
257 gpu->identity.pixel_pipes = 1;
258
259 /* Convert virtex buffer size */
260 if (gpu->identity.vertex_output_buffer_size) {
261 gpu->identity.vertex_output_buffer_size =
262 1 << gpu->identity.vertex_output_buffer_size;
263 } else if (gpu->identity.model == chipModel_GC400) {
264 if (gpu->identity.revision < 0x4000)
265 gpu->identity.vertex_output_buffer_size = 512;
266 else if (gpu->identity.revision < 0x4200)
267 gpu->identity.vertex_output_buffer_size = 256;
268 else
269 gpu->identity.vertex_output_buffer_size = 128;
270 } else {
271 gpu->identity.vertex_output_buffer_size = 512;
272 }
273
274 switch (gpu->identity.instruction_count) {
275 case 0:
276 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
277 gpu->identity.model == chipModel_GC880)
278 gpu->identity.instruction_count = 512;
279 else
280 gpu->identity.instruction_count = 256;
281 break;
282
283 case 1:
284 gpu->identity.instruction_count = 1024;
285 break;
286
287 case 2:
288 gpu->identity.instruction_count = 2048;
289 break;
290
291 default:
292 gpu->identity.instruction_count = 256;
293 break;
294 }
295
296 if (gpu->identity.num_constants == 0)
297 gpu->identity.num_constants = 168;
298
299 if (gpu->identity.varyings_count == 0) {
300 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
301 gpu->identity.varyings_count = 12;
302 else
303 gpu->identity.varyings_count = 8;
304 }
305
306 /*
307 * For some cores, two varyings are consumed for position, so the
308 * maximum varying count needs to be reduced by one.
309 */
310 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
311 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
312 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
313 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
314 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
315 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
316 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
317 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
318 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
319 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
320 etnaviv_is_model_rev(gpu, GC880, 0x5106))
321 gpu->identity.varyings_count -= 1;
322 }
323
etnaviv_hw_identify(struct etnaviv_gpu * gpu)324 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
325 {
326 u32 chipIdentity;
327
328 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
329
330 /* Special case for older graphic cores. */
331 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
332 gpu->identity.model = chipModel_GC500;
333 gpu->identity.revision = etnaviv_field(chipIdentity,
334 VIVS_HI_CHIP_IDENTITY_REVISION);
335 } else {
336 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
337
338 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
339 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
340 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
341
342 /*
343 * Reading these two registers on GC600 rev 0x19 result in a
344 * unhandled fault: external abort on non-linefetch
345 */
346 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
347 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
348 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
349 }
350
351 /*
352 * !!!! HACK ALERT !!!!
353 * Because people change device IDs without letting software
354 * know about it - here is the hack to make it all look the
355 * same. Only for GC400 family.
356 */
357 if ((gpu->identity.model & 0xff00) == 0x0400 &&
358 gpu->identity.model != chipModel_GC420) {
359 gpu->identity.model = gpu->identity.model & 0x0400;
360 }
361
362 /* Another special case */
363 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
364 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
365
366 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
367 /*
368 * This IP has an ECO; put the correct
369 * revision in it.
370 */
371 gpu->identity.revision = 0x1051;
372 }
373 }
374
375 /*
376 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
377 * reality it's just a re-branded GC3000. We can identify this
378 * core by the upper half of the revision register being all 1.
379 * Fix model/rev here, so all other places can refer to this
380 * core by its real identity.
381 */
382 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
383 gpu->identity.model = chipModel_GC3000;
384 gpu->identity.revision &= 0xffff;
385 }
386
387 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
388 gpu->identity.eco_id = 1;
389
390 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
391 gpu->identity.eco_id = 1;
392 }
393
394 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
395 gpu->identity.model, gpu->identity.revision);
396
397 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
398 /*
399 * If there is a match in the HWDB, we aren't interested in the
400 * remaining register values, as they might be wrong.
401 */
402 if (etnaviv_fill_identity_from_hwdb(gpu))
403 return;
404
405 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
406
407 /* Disable fast clear on GC700. */
408 if (gpu->identity.model == chipModel_GC700)
409 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
410
411 /* These models/revisions don't have the 2D pipe bit */
412 if ((gpu->identity.model == chipModel_GC500 &&
413 gpu->identity.revision <= 2) ||
414 gpu->identity.model == chipModel_GC300)
415 gpu->identity.features |= chipFeatures_PIPE_2D;
416
417 if ((gpu->identity.model == chipModel_GC500 &&
418 gpu->identity.revision < 2) ||
419 (gpu->identity.model == chipModel_GC300 &&
420 gpu->identity.revision < 0x2000)) {
421
422 /*
423 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
424 * registers.
425 */
426 gpu->identity.minor_features0 = 0;
427 gpu->identity.minor_features1 = 0;
428 gpu->identity.minor_features2 = 0;
429 gpu->identity.minor_features3 = 0;
430 gpu->identity.minor_features4 = 0;
431 gpu->identity.minor_features5 = 0;
432 } else
433 gpu->identity.minor_features0 =
434 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
435
436 if (gpu->identity.minor_features0 &
437 chipMinorFeatures0_MORE_MINOR_FEATURES) {
438 gpu->identity.minor_features1 =
439 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
440 gpu->identity.minor_features2 =
441 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
442 gpu->identity.minor_features3 =
443 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
444 gpu->identity.minor_features4 =
445 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
446 gpu->identity.minor_features5 =
447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
448 }
449
450 /* GC600/300 idle register reports zero bits where modules aren't present */
451 if (gpu->identity.model == chipModel_GC600 ||
452 gpu->identity.model == chipModel_GC300)
453 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
454 VIVS_HI_IDLE_STATE_RA |
455 VIVS_HI_IDLE_STATE_SE |
456 VIVS_HI_IDLE_STATE_PA |
457 VIVS_HI_IDLE_STATE_SH |
458 VIVS_HI_IDLE_STATE_PE |
459 VIVS_HI_IDLE_STATE_DE |
460 VIVS_HI_IDLE_STATE_FE;
461
462 etnaviv_hw_specs(gpu);
463 }
464
etnaviv_gpu_load_clock(struct etnaviv_gpu * gpu,u32 clock)465 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
466 {
467 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
468 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
469 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
470 }
471
etnaviv_gpu_update_clock(struct etnaviv_gpu * gpu)472 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
473 {
474 if (gpu->identity.minor_features2 &
475 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
476 clk_set_rate(gpu->clk_core,
477 gpu->base_rate_core >> gpu->freq_scale);
478 clk_set_rate(gpu->clk_shader,
479 gpu->base_rate_shader >> gpu->freq_scale);
480 } else {
481 unsigned int fscale = 1 << (6 - gpu->freq_scale);
482 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
483
484 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
485 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
486 etnaviv_gpu_load_clock(gpu, clock);
487 }
488 }
489
etnaviv_hw_reset(struct etnaviv_gpu * gpu)490 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
491 {
492 u32 control, idle;
493 unsigned long timeout;
494 bool failed = true;
495
496 /* We hope that the GPU resets in under one second */
497 timeout = jiffies + msecs_to_jiffies(1000);
498
499 while (time_is_after_jiffies(timeout)) {
500 /* enable clock */
501 unsigned int fscale = 1 << (6 - gpu->freq_scale);
502 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
503 etnaviv_gpu_load_clock(gpu, control);
504
505 /* isolate the GPU. */
506 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
507 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
508
509 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
510 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
511 VIVS_MMUv2_AHB_CONTROL_RESET);
512 } else {
513 /* set soft reset. */
514 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
515 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
516 }
517
518 /* wait for reset. */
519 usleep_range(10, 20);
520
521 /* reset soft reset bit. */
522 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
523 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
524
525 /* reset GPU isolation. */
526 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
527 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
528
529 /* read idle register. */
530 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
531
532 /* try resetting again if FE is not idle */
533 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
534 dev_dbg(gpu->dev, "FE is not idle\n");
535 continue;
536 }
537
538 /* read reset register. */
539 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
540
541 /* is the GPU idle? */
542 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
543 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
544 dev_dbg(gpu->dev, "GPU is not idle\n");
545 continue;
546 }
547
548 /* disable debug registers, as they are not normally needed */
549 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
550 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
551
552 failed = false;
553 break;
554 }
555
556 if (failed) {
557 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
558 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
559
560 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
561 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
562 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
563 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
564
565 return -EBUSY;
566 }
567
568 /* We rely on the GPU running, so program the clock */
569 etnaviv_gpu_update_clock(gpu);
570
571 gpu->fe_running = false;
572 gpu->exec_state = -1;
573 if (gpu->mmu_context)
574 etnaviv_iommu_context_put(gpu->mmu_context);
575 gpu->mmu_context = NULL;
576
577 return 0;
578 }
579
etnaviv_gpu_enable_mlcg(struct etnaviv_gpu * gpu)580 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
581 {
582 u32 pmc, ppc;
583
584 /* enable clock gating */
585 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
586 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
587
588 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
589 if (gpu->identity.revision == 0x4301 ||
590 gpu->identity.revision == 0x4302)
591 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
592
593 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
594
595 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
596
597 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
598 if (gpu->identity.model >= chipModel_GC400 &&
599 gpu->identity.model != chipModel_GC420 &&
600 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
601 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
602
603 /*
604 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
605 * present without a bug fix.
606 */
607 if (gpu->identity.revision < 0x5000 &&
608 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
609 !(gpu->identity.minor_features1 &
610 chipMinorFeatures1_DISABLE_PE_GATING))
611 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
612
613 if (gpu->identity.revision < 0x5422)
614 pmc |= BIT(15); /* Unknown bit */
615
616 /* Disable TX clock gating on affected core revisions. */
617 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
618 etnaviv_is_model_rev(gpu, GC2000, 0x5108))
619 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
620
621 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
622 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
623
624 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
625 }
626
etnaviv_gpu_start_fe(struct etnaviv_gpu * gpu,u32 address,u16 prefetch)627 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
628 {
629 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
630 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
631 VIVS_FE_COMMAND_CONTROL_ENABLE |
632 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
633
634 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
635 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
636 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
637 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
638 }
639
640 gpu->fe_running = true;
641 }
642
etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu * gpu,struct etnaviv_iommu_context * context)643 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
644 struct etnaviv_iommu_context *context)
645 {
646 u16 prefetch;
647 u32 address;
648
649 /* setup the MMU */
650 etnaviv_iommu_restore(gpu, context);
651
652 /* Start command processor */
653 prefetch = etnaviv_buffer_init(gpu);
654 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
655 &gpu->mmu_context->cmdbuf_mapping);
656
657 etnaviv_gpu_start_fe(gpu, address, prefetch);
658 }
659
etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu * gpu)660 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
661 {
662 /*
663 * Base value for VIVS_PM_PULSE_EATER register on models where it
664 * cannot be read, extracted from vivante kernel driver.
665 */
666 u32 pulse_eater = 0x01590880;
667
668 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
669 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
670 pulse_eater |= BIT(23);
671
672 }
673
674 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
675 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
676 pulse_eater &= ~BIT(16);
677 pulse_eater |= BIT(17);
678 }
679
680 if ((gpu->identity.revision > 0x5420) &&
681 (gpu->identity.features & chipFeatures_PIPE_3D))
682 {
683 /* Performance fix: disable internal DFS */
684 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
685 pulse_eater |= BIT(18);
686 }
687
688 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
689 }
690
etnaviv_gpu_hw_init(struct etnaviv_gpu * gpu)691 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
692 {
693 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
694 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
695 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
696 u32 mc_memory_debug;
697
698 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
699
700 if (gpu->identity.revision == 0x5007)
701 mc_memory_debug |= 0x0c;
702 else
703 mc_memory_debug |= 0x08;
704
705 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
706 }
707
708 /* enable module-level clock gating */
709 etnaviv_gpu_enable_mlcg(gpu);
710
711 /*
712 * Update GPU AXI cache atttribute to "cacheable, no allocate".
713 * This is necessary to prevent the iMX6 SoC locking up.
714 */
715 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
716 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
717 VIVS_HI_AXI_CONFIG_ARCACHE(2));
718
719 /* GC2000 rev 5108 needs a special bus config */
720 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
721 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
722 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
723 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
724 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
725 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
726 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
727 }
728
729 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
730 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
731 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
732 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
733 }
734
735 /* setup the pulse eater */
736 etnaviv_gpu_setup_pulse_eater(gpu);
737
738 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
739 }
740
etnaviv_gpu_init(struct etnaviv_gpu * gpu)741 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
742 {
743 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
744 int ret, i;
745
746 ret = pm_runtime_get_sync(gpu->dev);
747 if (ret < 0) {
748 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
749 goto pm_put;
750 }
751
752 etnaviv_hw_identify(gpu);
753
754 if (gpu->identity.model == 0) {
755 dev_err(gpu->dev, "Unknown GPU model\n");
756 ret = -ENXIO;
757 goto fail;
758 }
759
760 /* Exclude VG cores with FE2.0 */
761 if (gpu->identity.features & chipFeatures_PIPE_VG &&
762 gpu->identity.features & chipFeatures_FE20) {
763 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
764 ret = -ENXIO;
765 goto fail;
766 }
767
768 /*
769 * On cores with security features supported, we claim control over the
770 * security states.
771 */
772 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
773 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
774 gpu->sec_mode = ETNA_SEC_KERNEL;
775
776 ret = etnaviv_hw_reset(gpu);
777 if (ret) {
778 dev_err(gpu->dev, "GPU reset failed\n");
779 goto fail;
780 }
781
782 ret = etnaviv_iommu_global_init(gpu);
783 if (ret)
784 goto fail;
785
786 /*
787 * Set the GPU linear window to be at the end of the DMA window, where
788 * the CMA area is likely to reside. This ensures that we are able to
789 * map the command buffers while having the linear window overlap as
790 * much RAM as possible, so we can optimize mappings for other buffers.
791 *
792 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
793 * to different views of the memory on the individual engines.
794 */
795 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
796 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
797 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
798 if (dma_mask < PHYS_OFFSET + SZ_2G)
799 priv->mmu_global->memory_base = PHYS_OFFSET;
800 else
801 priv->mmu_global->memory_base = dma_mask - SZ_2G + 1;
802 } else if (PHYS_OFFSET >= SZ_2G) {
803 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
804 priv->mmu_global->memory_base = PHYS_OFFSET;
805 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
806 }
807
808 /*
809 * If the GPU is part of a system with DMA addressing limitations,
810 * request pages for our SHM backend buffers from the DMA32 zone to
811 * hopefully avoid performance killing SWIOTLB bounce buffering.
812 */
813 if (dma_addressing_limited(gpu->dev))
814 priv->shm_gfp_mask |= GFP_DMA32;
815
816 /* Create buffer: */
817 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
818 PAGE_SIZE);
819 if (ret) {
820 dev_err(gpu->dev, "could not create command buffer\n");
821 goto fail;
822 }
823
824 /* Setup event management */
825 spin_lock_init(&gpu->event_spinlock);
826 init_completion(&gpu->event_free);
827 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
828 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
829 complete(&gpu->event_free);
830
831 /* Now program the hardware */
832 mutex_lock(&gpu->lock);
833 etnaviv_gpu_hw_init(gpu);
834 mutex_unlock(&gpu->lock);
835
836 pm_runtime_mark_last_busy(gpu->dev);
837 pm_runtime_put_autosuspend(gpu->dev);
838
839 gpu->initialized = true;
840
841 return 0;
842
843 fail:
844 pm_runtime_mark_last_busy(gpu->dev);
845 pm_put:
846 pm_runtime_put_autosuspend(gpu->dev);
847
848 return ret;
849 }
850
851 #ifdef CONFIG_DEBUG_FS
852 struct dma_debug {
853 u32 address[2];
854 u32 state[2];
855 };
856
verify_dma(struct etnaviv_gpu * gpu,struct dma_debug * debug)857 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
858 {
859 u32 i;
860
861 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
862 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
863
864 for (i = 0; i < 500; i++) {
865 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
866 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
867
868 if (debug->address[0] != debug->address[1])
869 break;
870
871 if (debug->state[0] != debug->state[1])
872 break;
873 }
874 }
875
etnaviv_gpu_debugfs(struct etnaviv_gpu * gpu,struct seq_file * m)876 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
877 {
878 struct dma_debug debug;
879 u32 dma_lo, dma_hi, axi, idle;
880 int ret;
881
882 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
883
884 ret = pm_runtime_get_sync(gpu->dev);
885 if (ret < 0)
886 goto pm_put;
887
888 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
889 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
890 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
891 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
892
893 verify_dma(gpu, &debug);
894
895 seq_puts(m, "\tidentity\n");
896 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
897 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
898 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
899 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
900 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
901
902 seq_puts(m, "\tfeatures\n");
903 seq_printf(m, "\t major_features: 0x%08x\n",
904 gpu->identity.features);
905 seq_printf(m, "\t minor_features0: 0x%08x\n",
906 gpu->identity.minor_features0);
907 seq_printf(m, "\t minor_features1: 0x%08x\n",
908 gpu->identity.minor_features1);
909 seq_printf(m, "\t minor_features2: 0x%08x\n",
910 gpu->identity.minor_features2);
911 seq_printf(m, "\t minor_features3: 0x%08x\n",
912 gpu->identity.minor_features3);
913 seq_printf(m, "\t minor_features4: 0x%08x\n",
914 gpu->identity.minor_features4);
915 seq_printf(m, "\t minor_features5: 0x%08x\n",
916 gpu->identity.minor_features5);
917 seq_printf(m, "\t minor_features6: 0x%08x\n",
918 gpu->identity.minor_features6);
919 seq_printf(m, "\t minor_features7: 0x%08x\n",
920 gpu->identity.minor_features7);
921 seq_printf(m, "\t minor_features8: 0x%08x\n",
922 gpu->identity.minor_features8);
923 seq_printf(m, "\t minor_features9: 0x%08x\n",
924 gpu->identity.minor_features9);
925 seq_printf(m, "\t minor_features10: 0x%08x\n",
926 gpu->identity.minor_features10);
927 seq_printf(m, "\t minor_features11: 0x%08x\n",
928 gpu->identity.minor_features11);
929
930 seq_puts(m, "\tspecs\n");
931 seq_printf(m, "\t stream_count: %d\n",
932 gpu->identity.stream_count);
933 seq_printf(m, "\t register_max: %d\n",
934 gpu->identity.register_max);
935 seq_printf(m, "\t thread_count: %d\n",
936 gpu->identity.thread_count);
937 seq_printf(m, "\t vertex_cache_size: %d\n",
938 gpu->identity.vertex_cache_size);
939 seq_printf(m, "\t shader_core_count: %d\n",
940 gpu->identity.shader_core_count);
941 seq_printf(m, "\t pixel_pipes: %d\n",
942 gpu->identity.pixel_pipes);
943 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
944 gpu->identity.vertex_output_buffer_size);
945 seq_printf(m, "\t buffer_size: %d\n",
946 gpu->identity.buffer_size);
947 seq_printf(m, "\t instruction_count: %d\n",
948 gpu->identity.instruction_count);
949 seq_printf(m, "\t num_constants: %d\n",
950 gpu->identity.num_constants);
951 seq_printf(m, "\t varyings_count: %d\n",
952 gpu->identity.varyings_count);
953
954 seq_printf(m, "\taxi: 0x%08x\n", axi);
955 seq_printf(m, "\tidle: 0x%08x\n", idle);
956 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
957 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
958 seq_puts(m, "\t FE is not idle\n");
959 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
960 seq_puts(m, "\t DE is not idle\n");
961 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
962 seq_puts(m, "\t PE is not idle\n");
963 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
964 seq_puts(m, "\t SH is not idle\n");
965 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
966 seq_puts(m, "\t PA is not idle\n");
967 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
968 seq_puts(m, "\t SE is not idle\n");
969 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
970 seq_puts(m, "\t RA is not idle\n");
971 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
972 seq_puts(m, "\t TX is not idle\n");
973 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
974 seq_puts(m, "\t VG is not idle\n");
975 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
976 seq_puts(m, "\t IM is not idle\n");
977 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
978 seq_puts(m, "\t FP is not idle\n");
979 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
980 seq_puts(m, "\t TS is not idle\n");
981 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
982 seq_puts(m, "\t BL is not idle\n");
983 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
984 seq_puts(m, "\t ASYNCFE is not idle\n");
985 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
986 seq_puts(m, "\t MC is not idle\n");
987 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
988 seq_puts(m, "\t PPA is not idle\n");
989 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
990 seq_puts(m, "\t WD is not idle\n");
991 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
992 seq_puts(m, "\t NN is not idle\n");
993 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
994 seq_puts(m, "\t TP is not idle\n");
995 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
996 seq_puts(m, "\t AXI low power mode\n");
997
998 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
999 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1000 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1001 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1002
1003 seq_puts(m, "\tMC\n");
1004 seq_printf(m, "\t read0: 0x%08x\n", read0);
1005 seq_printf(m, "\t read1: 0x%08x\n", read1);
1006 seq_printf(m, "\t write: 0x%08x\n", write);
1007 }
1008
1009 seq_puts(m, "\tDMA ");
1010
1011 if (debug.address[0] == debug.address[1] &&
1012 debug.state[0] == debug.state[1]) {
1013 seq_puts(m, "seems to be stuck\n");
1014 } else if (debug.address[0] == debug.address[1]) {
1015 seq_puts(m, "address is constant\n");
1016 } else {
1017 seq_puts(m, "is running\n");
1018 }
1019
1020 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1021 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1022 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1023 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1024 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1025 dma_lo, dma_hi);
1026
1027 ret = 0;
1028
1029 pm_runtime_mark_last_busy(gpu->dev);
1030 pm_put:
1031 pm_runtime_put_autosuspend(gpu->dev);
1032
1033 return ret;
1034 }
1035 #endif
1036
etnaviv_gpu_recover_hang(struct etnaviv_gpu * gpu)1037 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
1038 {
1039 unsigned int i = 0;
1040
1041 dev_err(gpu->dev, "recover hung GPU!\n");
1042
1043 if (pm_runtime_get_sync(gpu->dev) < 0)
1044 goto pm_put;
1045
1046 mutex_lock(&gpu->lock);
1047
1048 etnaviv_hw_reset(gpu);
1049
1050 /* complete all events, the GPU won't do it after the reset */
1051 spin_lock(&gpu->event_spinlock);
1052 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1053 complete(&gpu->event_free);
1054 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
1055 spin_unlock(&gpu->event_spinlock);
1056
1057 etnaviv_gpu_hw_init(gpu);
1058
1059 mutex_unlock(&gpu->lock);
1060 pm_runtime_mark_last_busy(gpu->dev);
1061 pm_put:
1062 pm_runtime_put_autosuspend(gpu->dev);
1063 }
1064
1065 /* fence object management */
1066 struct etnaviv_fence {
1067 struct etnaviv_gpu *gpu;
1068 struct dma_fence base;
1069 };
1070
to_etnaviv_fence(struct dma_fence * fence)1071 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1072 {
1073 return container_of(fence, struct etnaviv_fence, base);
1074 }
1075
etnaviv_fence_get_driver_name(struct dma_fence * fence)1076 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1077 {
1078 return "etnaviv";
1079 }
1080
etnaviv_fence_get_timeline_name(struct dma_fence * fence)1081 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1082 {
1083 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1084
1085 return dev_name(f->gpu->dev);
1086 }
1087
etnaviv_fence_signaled(struct dma_fence * fence)1088 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1089 {
1090 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1091
1092 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1093 }
1094
etnaviv_fence_release(struct dma_fence * fence)1095 static void etnaviv_fence_release(struct dma_fence *fence)
1096 {
1097 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1098
1099 kfree_rcu(f, base.rcu);
1100 }
1101
1102 static const struct dma_fence_ops etnaviv_fence_ops = {
1103 .get_driver_name = etnaviv_fence_get_driver_name,
1104 .get_timeline_name = etnaviv_fence_get_timeline_name,
1105 .signaled = etnaviv_fence_signaled,
1106 .release = etnaviv_fence_release,
1107 };
1108
etnaviv_gpu_fence_alloc(struct etnaviv_gpu * gpu)1109 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1110 {
1111 struct etnaviv_fence *f;
1112
1113 /*
1114 * GPU lock must already be held, otherwise fence completion order might
1115 * not match the seqno order assigned here.
1116 */
1117 lockdep_assert_held(&gpu->lock);
1118
1119 f = kzalloc(sizeof(*f), GFP_KERNEL);
1120 if (!f)
1121 return NULL;
1122
1123 f->gpu = gpu;
1124
1125 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1126 gpu->fence_context, ++gpu->next_fence);
1127
1128 return &f->base;
1129 }
1130
1131 /* returns true if fence a comes after fence b */
fence_after(u32 a,u32 b)1132 static inline bool fence_after(u32 a, u32 b)
1133 {
1134 return (s32)(a - b) > 0;
1135 }
1136
1137 /*
1138 * event management:
1139 */
1140
event_alloc(struct etnaviv_gpu * gpu,unsigned nr_events,unsigned int * events)1141 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1142 unsigned int *events)
1143 {
1144 unsigned long timeout = msecs_to_jiffies(10 * 10000);
1145 unsigned i, acquired = 0;
1146
1147 for (i = 0; i < nr_events; i++) {
1148 unsigned long ret;
1149
1150 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1151
1152 if (!ret) {
1153 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1154 goto out;
1155 }
1156
1157 acquired++;
1158 timeout = ret;
1159 }
1160
1161 spin_lock(&gpu->event_spinlock);
1162
1163 for (i = 0; i < nr_events; i++) {
1164 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1165
1166 events[i] = event;
1167 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1168 set_bit(event, gpu->event_bitmap);
1169 }
1170
1171 spin_unlock(&gpu->event_spinlock);
1172
1173 return 0;
1174
1175 out:
1176 for (i = 0; i < acquired; i++)
1177 complete(&gpu->event_free);
1178
1179 return -EBUSY;
1180 }
1181
event_free(struct etnaviv_gpu * gpu,unsigned int event)1182 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1183 {
1184 if (!test_bit(event, gpu->event_bitmap)) {
1185 dev_warn(gpu->dev, "event %u is already marked as free",
1186 event);
1187 } else {
1188 clear_bit(event, gpu->event_bitmap);
1189 complete(&gpu->event_free);
1190 }
1191 }
1192
1193 /*
1194 * Cmdstream submission/retirement:
1195 */
etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu * gpu,u32 id,struct drm_etnaviv_timespec * timeout)1196 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1197 u32 id, struct drm_etnaviv_timespec *timeout)
1198 {
1199 struct dma_fence *fence;
1200 int ret;
1201
1202 /*
1203 * Look up the fence and take a reference. We might still find a fence
1204 * whose refcount has already dropped to zero. dma_fence_get_rcu
1205 * pretends we didn't find a fence in that case.
1206 */
1207 rcu_read_lock();
1208 fence = idr_find(&gpu->fence_idr, id);
1209 if (fence)
1210 fence = dma_fence_get_rcu(fence);
1211 rcu_read_unlock();
1212
1213 if (!fence)
1214 return 0;
1215
1216 if (!timeout) {
1217 /* No timeout was requested: just test for completion */
1218 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1219 } else {
1220 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1221
1222 ret = dma_fence_wait_timeout(fence, true, remaining);
1223 if (ret == 0)
1224 ret = -ETIMEDOUT;
1225 else if (ret != -ERESTARTSYS)
1226 ret = 0;
1227
1228 }
1229
1230 dma_fence_put(fence);
1231 return ret;
1232 }
1233
1234 /*
1235 * Wait for an object to become inactive. This, on it's own, is not race
1236 * free: the object is moved by the scheduler off the active list, and
1237 * then the iova is put. Moreover, the object could be re-submitted just
1238 * after we notice that it's become inactive.
1239 *
1240 * Although the retirement happens under the gpu lock, we don't want to hold
1241 * that lock in this function while waiting.
1242 */
etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu * gpu,struct etnaviv_gem_object * etnaviv_obj,struct drm_etnaviv_timespec * timeout)1243 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1244 struct etnaviv_gem_object *etnaviv_obj,
1245 struct drm_etnaviv_timespec *timeout)
1246 {
1247 unsigned long remaining;
1248 long ret;
1249
1250 if (!timeout)
1251 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1252
1253 remaining = etnaviv_timeout_to_jiffies(timeout);
1254
1255 ret = wait_event_interruptible_timeout(gpu->fence_event,
1256 !is_active(etnaviv_obj),
1257 remaining);
1258 if (ret > 0)
1259 return 0;
1260 else if (ret == -ERESTARTSYS)
1261 return -ERESTARTSYS;
1262 else
1263 return -ETIMEDOUT;
1264 }
1265
sync_point_perfmon_sample(struct etnaviv_gpu * gpu,struct etnaviv_event * event,unsigned int flags)1266 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1267 struct etnaviv_event *event, unsigned int flags)
1268 {
1269 const struct etnaviv_gem_submit *submit = event->submit;
1270 unsigned int i;
1271
1272 for (i = 0; i < submit->nr_pmrs; i++) {
1273 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1274
1275 if (pmr->flags == flags)
1276 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1277 }
1278 }
1279
sync_point_perfmon_sample_pre(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1280 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1281 struct etnaviv_event *event)
1282 {
1283 u32 val;
1284
1285 /* disable clock gating */
1286 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1287 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1288 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1289
1290 /* enable debug register */
1291 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1292 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1293 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1294
1295 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1296 }
1297
sync_point_perfmon_sample_post(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1298 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1299 struct etnaviv_event *event)
1300 {
1301 const struct etnaviv_gem_submit *submit = event->submit;
1302 unsigned int i;
1303 u32 val;
1304
1305 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1306
1307 for (i = 0; i < submit->nr_pmrs; i++) {
1308 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1309
1310 *pmr->bo_vma = pmr->sequence;
1311 }
1312
1313 /* disable debug register */
1314 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1315 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1316 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1317
1318 /* enable clock gating */
1319 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1320 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1321 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1322 }
1323
1324
1325 /* add bo's to gpu's ring, and kick gpu: */
etnaviv_gpu_submit(struct etnaviv_gem_submit * submit)1326 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1327 {
1328 struct etnaviv_gpu *gpu = submit->gpu;
1329 struct dma_fence *gpu_fence;
1330 unsigned int i, nr_events = 1, event[3];
1331 int ret;
1332
1333 if (!submit->runtime_resumed) {
1334 ret = pm_runtime_get_sync(gpu->dev);
1335 if (ret < 0) {
1336 pm_runtime_put_noidle(gpu->dev);
1337 return NULL;
1338 }
1339 submit->runtime_resumed = true;
1340 }
1341
1342 /*
1343 * if there are performance monitor requests we need to have
1344 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1345 * requests.
1346 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1347 * and update the sequence number for userspace.
1348 */
1349 if (submit->nr_pmrs)
1350 nr_events = 3;
1351
1352 ret = event_alloc(gpu, nr_events, event);
1353 if (ret) {
1354 DRM_ERROR("no free events\n");
1355 pm_runtime_put_noidle(gpu->dev);
1356 return NULL;
1357 }
1358
1359 mutex_lock(&gpu->lock);
1360
1361 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1362 if (!gpu_fence) {
1363 for (i = 0; i < nr_events; i++)
1364 event_free(gpu, event[i]);
1365
1366 goto out_unlock;
1367 }
1368
1369 if (!gpu->fe_running)
1370 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1371
1372 if (submit->prev_mmu_context)
1373 etnaviv_iommu_context_put(submit->prev_mmu_context);
1374 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1375
1376 if (submit->nr_pmrs) {
1377 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1378 kref_get(&submit->refcount);
1379 gpu->event[event[1]].submit = submit;
1380 etnaviv_sync_point_queue(gpu, event[1]);
1381 }
1382
1383 gpu->event[event[0]].fence = gpu_fence;
1384 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1385 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1386 event[0], &submit->cmdbuf);
1387
1388 if (submit->nr_pmrs) {
1389 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1390 kref_get(&submit->refcount);
1391 gpu->event[event[2]].submit = submit;
1392 etnaviv_sync_point_queue(gpu, event[2]);
1393 }
1394
1395 out_unlock:
1396 mutex_unlock(&gpu->lock);
1397
1398 return gpu_fence;
1399 }
1400
sync_point_worker(struct work_struct * work)1401 static void sync_point_worker(struct work_struct *work)
1402 {
1403 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1404 sync_point_work);
1405 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1406 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1407
1408 event->sync_point(gpu, event);
1409 etnaviv_submit_put(event->submit);
1410 event_free(gpu, gpu->sync_point_event);
1411
1412 /* restart FE last to avoid GPU and IRQ racing against this worker */
1413 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1414 }
1415
dump_mmu_fault(struct etnaviv_gpu * gpu)1416 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1417 {
1418 u32 status_reg, status;
1419 int i;
1420
1421 if (gpu->sec_mode == ETNA_SEC_NONE)
1422 status_reg = VIVS_MMUv2_STATUS;
1423 else
1424 status_reg = VIVS_MMUv2_SEC_STATUS;
1425
1426 status = gpu_read(gpu, status_reg);
1427 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1428
1429 for (i = 0; i < 4; i++) {
1430 u32 address_reg;
1431
1432 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1433 continue;
1434
1435 if (gpu->sec_mode == ETNA_SEC_NONE)
1436 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1437 else
1438 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1439
1440 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1441 gpu_read(gpu, address_reg));
1442 }
1443 }
1444
irq_handler(int irq,void * data)1445 static irqreturn_t irq_handler(int irq, void *data)
1446 {
1447 struct etnaviv_gpu *gpu = data;
1448 irqreturn_t ret = IRQ_NONE;
1449
1450 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1451
1452 if (intr != 0) {
1453 int event;
1454
1455 pm_runtime_mark_last_busy(gpu->dev);
1456
1457 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1458
1459 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1460 dev_err(gpu->dev, "AXI bus error\n");
1461 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1462 }
1463
1464 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1465 dump_mmu_fault(gpu);
1466 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1467 }
1468
1469 while ((event = ffs(intr)) != 0) {
1470 struct dma_fence *fence;
1471
1472 event -= 1;
1473
1474 intr &= ~(1 << event);
1475
1476 dev_dbg(gpu->dev, "event %u\n", event);
1477
1478 if (gpu->event[event].sync_point) {
1479 gpu->sync_point_event = event;
1480 queue_work(gpu->wq, &gpu->sync_point_work);
1481 }
1482
1483 fence = gpu->event[event].fence;
1484 if (!fence)
1485 continue;
1486
1487 gpu->event[event].fence = NULL;
1488
1489 /*
1490 * Events can be processed out of order. Eg,
1491 * - allocate and queue event 0
1492 * - allocate event 1
1493 * - event 0 completes, we process it
1494 * - allocate and queue event 0
1495 * - event 1 and event 0 complete
1496 * we can end up processing event 0 first, then 1.
1497 */
1498 if (fence_after(fence->seqno, gpu->completed_fence))
1499 gpu->completed_fence = fence->seqno;
1500 dma_fence_signal(fence);
1501
1502 event_free(gpu, event);
1503 }
1504
1505 ret = IRQ_HANDLED;
1506 }
1507
1508 return ret;
1509 }
1510
etnaviv_gpu_clk_enable(struct etnaviv_gpu * gpu)1511 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1512 {
1513 int ret;
1514
1515 ret = clk_prepare_enable(gpu->clk_reg);
1516 if (ret)
1517 return ret;
1518
1519 ret = clk_prepare_enable(gpu->clk_bus);
1520 if (ret)
1521 goto disable_clk_reg;
1522
1523 ret = clk_prepare_enable(gpu->clk_core);
1524 if (ret)
1525 goto disable_clk_bus;
1526
1527 ret = clk_prepare_enable(gpu->clk_shader);
1528 if (ret)
1529 goto disable_clk_core;
1530
1531 return 0;
1532
1533 disable_clk_core:
1534 clk_disable_unprepare(gpu->clk_core);
1535 disable_clk_bus:
1536 clk_disable_unprepare(gpu->clk_bus);
1537 disable_clk_reg:
1538 clk_disable_unprepare(gpu->clk_reg);
1539
1540 return ret;
1541 }
1542
etnaviv_gpu_clk_disable(struct etnaviv_gpu * gpu)1543 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1544 {
1545 clk_disable_unprepare(gpu->clk_shader);
1546 clk_disable_unprepare(gpu->clk_core);
1547 clk_disable_unprepare(gpu->clk_bus);
1548 clk_disable_unprepare(gpu->clk_reg);
1549
1550 return 0;
1551 }
1552
etnaviv_gpu_wait_idle(struct etnaviv_gpu * gpu,unsigned int timeout_ms)1553 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1554 {
1555 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1556
1557 do {
1558 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1559
1560 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1561 return 0;
1562
1563 if (time_is_before_jiffies(timeout)) {
1564 dev_warn(gpu->dev,
1565 "timed out waiting for idle: idle=0x%x\n",
1566 idle);
1567 return -ETIMEDOUT;
1568 }
1569
1570 udelay(5);
1571 } while (1);
1572 }
1573
etnaviv_gpu_hw_suspend(struct etnaviv_gpu * gpu)1574 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1575 {
1576 if (gpu->initialized && gpu->fe_running) {
1577 /* Replace the last WAIT with END */
1578 mutex_lock(&gpu->lock);
1579 etnaviv_buffer_end(gpu);
1580 mutex_unlock(&gpu->lock);
1581
1582 /*
1583 * We know that only the FE is busy here, this should
1584 * happen quickly (as the WAIT is only 200 cycles). If
1585 * we fail, just warn and continue.
1586 */
1587 etnaviv_gpu_wait_idle(gpu, 100);
1588
1589 gpu->fe_running = false;
1590 }
1591
1592 gpu->exec_state = -1;
1593
1594 return etnaviv_gpu_clk_disable(gpu);
1595 }
1596
1597 #ifdef CONFIG_PM
etnaviv_gpu_hw_resume(struct etnaviv_gpu * gpu)1598 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1599 {
1600 int ret;
1601
1602 ret = mutex_lock_killable(&gpu->lock);
1603 if (ret)
1604 return ret;
1605
1606 etnaviv_gpu_update_clock(gpu);
1607 etnaviv_gpu_hw_init(gpu);
1608
1609 mutex_unlock(&gpu->lock);
1610
1611 return 0;
1612 }
1613 #endif
1614
1615 static int
etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device * cdev,unsigned long * state)1616 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1617 unsigned long *state)
1618 {
1619 *state = 6;
1620
1621 return 0;
1622 }
1623
1624 static int
etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device * cdev,unsigned long * state)1625 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1626 unsigned long *state)
1627 {
1628 struct etnaviv_gpu *gpu = cdev->devdata;
1629
1630 *state = gpu->freq_scale;
1631
1632 return 0;
1633 }
1634
1635 static int
etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device * cdev,unsigned long state)1636 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1637 unsigned long state)
1638 {
1639 struct etnaviv_gpu *gpu = cdev->devdata;
1640
1641 mutex_lock(&gpu->lock);
1642 gpu->freq_scale = state;
1643 if (!pm_runtime_suspended(gpu->dev))
1644 etnaviv_gpu_update_clock(gpu);
1645 mutex_unlock(&gpu->lock);
1646
1647 return 0;
1648 }
1649
1650 static struct thermal_cooling_device_ops cooling_ops = {
1651 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1652 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1653 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1654 };
1655
etnaviv_gpu_bind(struct device * dev,struct device * master,void * data)1656 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1657 void *data)
1658 {
1659 struct drm_device *drm = data;
1660 struct etnaviv_drm_private *priv = drm->dev_private;
1661 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1662 int ret;
1663
1664 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1665 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1666 (char *)dev_name(dev), gpu, &cooling_ops);
1667 if (IS_ERR(gpu->cooling))
1668 return PTR_ERR(gpu->cooling);
1669 }
1670
1671 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1672 if (!gpu->wq) {
1673 ret = -ENOMEM;
1674 goto out_thermal;
1675 }
1676
1677 ret = etnaviv_sched_init(gpu);
1678 if (ret)
1679 goto out_workqueue;
1680
1681 #ifdef CONFIG_PM
1682 ret = pm_runtime_get_sync(gpu->dev);
1683 #else
1684 ret = etnaviv_gpu_clk_enable(gpu);
1685 #endif
1686 if (ret < 0)
1687 goto out_sched;
1688
1689
1690 gpu->drm = drm;
1691 gpu->fence_context = dma_fence_context_alloc(1);
1692 idr_init(&gpu->fence_idr);
1693 spin_lock_init(&gpu->fence_spinlock);
1694
1695 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1696 init_waitqueue_head(&gpu->fence_event);
1697
1698 priv->gpu[priv->num_gpus++] = gpu;
1699
1700 pm_runtime_mark_last_busy(gpu->dev);
1701 pm_runtime_put_autosuspend(gpu->dev);
1702
1703 return 0;
1704
1705 out_sched:
1706 etnaviv_sched_fini(gpu);
1707
1708 out_workqueue:
1709 destroy_workqueue(gpu->wq);
1710
1711 out_thermal:
1712 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1713 thermal_cooling_device_unregister(gpu->cooling);
1714
1715 return ret;
1716 }
1717
etnaviv_gpu_unbind(struct device * dev,struct device * master,void * data)1718 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1719 void *data)
1720 {
1721 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1722
1723 DBG("%s", dev_name(gpu->dev));
1724
1725 flush_workqueue(gpu->wq);
1726 destroy_workqueue(gpu->wq);
1727
1728 etnaviv_sched_fini(gpu);
1729
1730 #ifdef CONFIG_PM
1731 pm_runtime_get_sync(gpu->dev);
1732 pm_runtime_put_sync_suspend(gpu->dev);
1733 #else
1734 etnaviv_gpu_hw_suspend(gpu);
1735 #endif
1736
1737 if (gpu->mmu_context)
1738 etnaviv_iommu_context_put(gpu->mmu_context);
1739
1740 if (gpu->initialized) {
1741 etnaviv_cmdbuf_free(&gpu->buffer);
1742 etnaviv_iommu_global_fini(gpu);
1743 gpu->initialized = false;
1744 }
1745
1746 gpu->drm = NULL;
1747 idr_destroy(&gpu->fence_idr);
1748
1749 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1750 thermal_cooling_device_unregister(gpu->cooling);
1751 gpu->cooling = NULL;
1752 }
1753
1754 static const struct component_ops gpu_ops = {
1755 .bind = etnaviv_gpu_bind,
1756 .unbind = etnaviv_gpu_unbind,
1757 };
1758
1759 static const struct of_device_id etnaviv_gpu_match[] = {
1760 {
1761 .compatible = "vivante,gc"
1762 },
1763 { /* sentinel */ }
1764 };
1765 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1766
etnaviv_gpu_platform_probe(struct platform_device * pdev)1767 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1768 {
1769 struct device *dev = &pdev->dev;
1770 struct etnaviv_gpu *gpu;
1771 int err;
1772
1773 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1774 if (!gpu)
1775 return -ENOMEM;
1776
1777 gpu->dev = &pdev->dev;
1778 mutex_init(&gpu->lock);
1779 mutex_init(&gpu->fence_lock);
1780
1781 /* Map registers: */
1782 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1783 if (IS_ERR(gpu->mmio))
1784 return PTR_ERR(gpu->mmio);
1785
1786 /* Get Interrupt: */
1787 gpu->irq = platform_get_irq(pdev, 0);
1788 if (gpu->irq < 0) {
1789 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1790 return gpu->irq;
1791 }
1792
1793 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1794 dev_name(gpu->dev), gpu);
1795 if (err) {
1796 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1797 return err;
1798 }
1799
1800 /* Get Clocks: */
1801 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1802 DBG("clk_reg: %p", gpu->clk_reg);
1803 if (IS_ERR(gpu->clk_reg))
1804 return PTR_ERR(gpu->clk_reg);
1805
1806 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1807 DBG("clk_bus: %p", gpu->clk_bus);
1808 if (IS_ERR(gpu->clk_bus))
1809 return PTR_ERR(gpu->clk_bus);
1810
1811 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1812 DBG("clk_core: %p", gpu->clk_core);
1813 if (IS_ERR(gpu->clk_core))
1814 return PTR_ERR(gpu->clk_core);
1815 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1816
1817 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1818 DBG("clk_shader: %p", gpu->clk_shader);
1819 if (IS_ERR(gpu->clk_shader))
1820 return PTR_ERR(gpu->clk_shader);
1821 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1822
1823 /* TODO: figure out max mapped size */
1824 dev_set_drvdata(dev, gpu);
1825
1826 /*
1827 * We treat the device as initially suspended. The runtime PM
1828 * autosuspend delay is rather arbitary: no measurements have
1829 * yet been performed to determine an appropriate value.
1830 */
1831 pm_runtime_use_autosuspend(gpu->dev);
1832 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1833 pm_runtime_enable(gpu->dev);
1834
1835 err = component_add(&pdev->dev, &gpu_ops);
1836 if (err < 0) {
1837 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1838 return err;
1839 }
1840
1841 return 0;
1842 }
1843
etnaviv_gpu_platform_remove(struct platform_device * pdev)1844 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1845 {
1846 component_del(&pdev->dev, &gpu_ops);
1847 pm_runtime_disable(&pdev->dev);
1848 return 0;
1849 }
1850
1851 #ifdef CONFIG_PM
etnaviv_gpu_rpm_suspend(struct device * dev)1852 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1853 {
1854 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1855 u32 idle, mask;
1856
1857 /* If there are any jobs in the HW queue, we're not idle */
1858 if (atomic_read(&gpu->sched.hw_rq_count))
1859 return -EBUSY;
1860
1861 /* Check whether the hardware (except FE and MC) is idle */
1862 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1863 VIVS_HI_IDLE_STATE_MC);
1864 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1865 if (idle != mask) {
1866 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1867 idle);
1868 return -EBUSY;
1869 }
1870
1871 return etnaviv_gpu_hw_suspend(gpu);
1872 }
1873
etnaviv_gpu_rpm_resume(struct device * dev)1874 static int etnaviv_gpu_rpm_resume(struct device *dev)
1875 {
1876 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1877 int ret;
1878
1879 ret = etnaviv_gpu_clk_enable(gpu);
1880 if (ret)
1881 return ret;
1882
1883 /* Re-initialise the basic hardware state */
1884 if (gpu->drm && gpu->initialized) {
1885 ret = etnaviv_gpu_hw_resume(gpu);
1886 if (ret) {
1887 etnaviv_gpu_clk_disable(gpu);
1888 return ret;
1889 }
1890 }
1891
1892 return 0;
1893 }
1894 #endif
1895
1896 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1897 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1898 NULL)
1899 };
1900
1901 struct platform_driver etnaviv_gpu_driver = {
1902 .driver = {
1903 .name = "etnaviv-gpu",
1904 .owner = THIS_MODULE,
1905 .pm = &etnaviv_gpu_pm_ops,
1906 .of_match_table = etnaviv_gpu_match,
1907 },
1908 .probe = etnaviv_gpu_platform_probe,
1909 .remove = etnaviv_gpu_platform_remove,
1910 .id_table = gpu_ids,
1911 };
1912