1 /*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6 #include <linux/irq.h>
7 #include <linux/irqchip.h>
8 #include <linux/irqdesc.h>
9 #include <linux/irqchip/chained_irq.h>
10 #include "dpu_kms.h"
11
12 #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
13
14 #define HW_REV 0x0
15 #define HW_INTR_STATUS 0x0010
16
17 #define UBWC_STATIC 0x144
18 #define UBWC_CTRL_2 0x150
19 #define UBWC_PREDICTION_MODE 0x154
20
21 /* Max BW defined in KBps */
22 #define MAX_BW 6800000
23
24 struct dpu_irq_controller {
25 unsigned long enabled_mask;
26 struct irq_domain *domain;
27 };
28
29 struct dpu_mdss {
30 struct msm_mdss base;
31 void __iomem *mmio;
32 struct dss_module_power mp;
33 struct dpu_irq_controller irq_controller;
34 };
35
dpu_mdss_irq(struct irq_desc * desc)36 static void dpu_mdss_irq(struct irq_desc *desc)
37 {
38 struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
39 struct irq_chip *chip = irq_desc_get_chip(desc);
40 u32 interrupts;
41
42 chained_irq_enter(chip, desc);
43
44 interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
45
46 while (interrupts) {
47 irq_hw_number_t hwirq = fls(interrupts) - 1;
48 unsigned int mapping;
49 int rc;
50
51 mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
52 hwirq);
53 if (mapping == 0) {
54 DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
55 break;
56 }
57
58 rc = generic_handle_irq(mapping);
59 if (rc < 0) {
60 DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
61 hwirq, mapping, rc);
62 break;
63 }
64
65 interrupts &= ~(1 << hwirq);
66 }
67
68 chained_irq_exit(chip, desc);
69 }
70
dpu_mdss_irq_mask(struct irq_data * irqd)71 static void dpu_mdss_irq_mask(struct irq_data *irqd)
72 {
73 struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
74
75 /* memory barrier */
76 smp_mb__before_atomic();
77 clear_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
78 /* memory barrier */
79 smp_mb__after_atomic();
80 }
81
dpu_mdss_irq_unmask(struct irq_data * irqd)82 static void dpu_mdss_irq_unmask(struct irq_data *irqd)
83 {
84 struct dpu_mdss *dpu_mdss = irq_data_get_irq_chip_data(irqd);
85
86 /* memory barrier */
87 smp_mb__before_atomic();
88 set_bit(irqd->hwirq, &dpu_mdss->irq_controller.enabled_mask);
89 /* memory barrier */
90 smp_mb__after_atomic();
91 }
92
93 static struct irq_chip dpu_mdss_irq_chip = {
94 .name = "dpu_mdss",
95 .irq_mask = dpu_mdss_irq_mask,
96 .irq_unmask = dpu_mdss_irq_unmask,
97 };
98
99 static struct lock_class_key dpu_mdss_lock_key, dpu_mdss_request_key;
100
dpu_mdss_irqdomain_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)101 static int dpu_mdss_irqdomain_map(struct irq_domain *domain,
102 unsigned int irq, irq_hw_number_t hwirq)
103 {
104 struct dpu_mdss *dpu_mdss = domain->host_data;
105
106 irq_set_lockdep_class(irq, &dpu_mdss_lock_key, &dpu_mdss_request_key);
107 irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
108 return irq_set_chip_data(irq, dpu_mdss);
109 }
110
111 static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
112 .map = dpu_mdss_irqdomain_map,
113 .xlate = irq_domain_xlate_onecell,
114 };
115
_dpu_mdss_irq_domain_add(struct dpu_mdss * dpu_mdss)116 static int _dpu_mdss_irq_domain_add(struct dpu_mdss *dpu_mdss)
117 {
118 struct device *dev;
119 struct irq_domain *domain;
120
121 dev = dpu_mdss->base.dev->dev;
122
123 domain = irq_domain_add_linear(dev->of_node, 32,
124 &dpu_mdss_irqdomain_ops, dpu_mdss);
125 if (!domain) {
126 DPU_ERROR("failed to add irq_domain\n");
127 return -EINVAL;
128 }
129
130 dpu_mdss->irq_controller.enabled_mask = 0;
131 dpu_mdss->irq_controller.domain = domain;
132
133 return 0;
134 }
135
_dpu_mdss_irq_domain_fini(struct dpu_mdss * dpu_mdss)136 static void _dpu_mdss_irq_domain_fini(struct dpu_mdss *dpu_mdss)
137 {
138 if (dpu_mdss->irq_controller.domain) {
139 irq_domain_remove(dpu_mdss->irq_controller.domain);
140 dpu_mdss->irq_controller.domain = NULL;
141 }
142 }
dpu_mdss_enable(struct msm_mdss * mdss)143 static int dpu_mdss_enable(struct msm_mdss *mdss)
144 {
145 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
146 struct dss_module_power *mp = &dpu_mdss->mp;
147 int ret;
148
149 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
150 if (ret) {
151 DPU_ERROR("clock enable failed, ret:%d\n", ret);
152 return ret;
153 }
154
155 /*
156 * ubwc config is part of the "mdss" region which is not accessible
157 * from the rest of the driver. hardcode known configurations here
158 */
159 switch (readl_relaxed(dpu_mdss->mmio + HW_REV)) {
160 case DPU_HW_VER_500:
161 case DPU_HW_VER_501:
162 writel_relaxed(0x420, dpu_mdss->mmio + UBWC_STATIC);
163 break;
164 case DPU_HW_VER_600:
165 /* TODO: 0x102e for LP_DDR4 */
166 writel_relaxed(0x103e, dpu_mdss->mmio + UBWC_STATIC);
167 writel_relaxed(2, dpu_mdss->mmio + UBWC_CTRL_2);
168 writel_relaxed(1, dpu_mdss->mmio + UBWC_PREDICTION_MODE);
169 break;
170 case DPU_HW_VER_620:
171 writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC);
172 break;
173 }
174
175 return ret;
176 }
177
dpu_mdss_disable(struct msm_mdss * mdss)178 static int dpu_mdss_disable(struct msm_mdss *mdss)
179 {
180 struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
181 struct dss_module_power *mp = &dpu_mdss->mp;
182 int ret;
183
184 ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
185 if (ret)
186 DPU_ERROR("clock disable failed, ret:%d\n", ret);
187
188 return ret;
189 }
190
dpu_mdss_destroy(struct drm_device * dev)191 static void dpu_mdss_destroy(struct drm_device *dev)
192 {
193 struct platform_device *pdev = to_platform_device(dev->dev);
194 struct msm_drm_private *priv = dev->dev_private;
195 struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
196 struct dss_module_power *mp = &dpu_mdss->mp;
197 int irq;
198
199 pm_runtime_suspend(dev->dev);
200 pm_runtime_disable(dev->dev);
201 _dpu_mdss_irq_domain_fini(dpu_mdss);
202 irq = platform_get_irq(pdev, 0);
203 irq_set_chained_handler_and_data(irq, NULL, NULL);
204 msm_dss_put_clk(mp->clk_config, mp->num_clk);
205 devm_kfree(&pdev->dev, mp->clk_config);
206
207 if (dpu_mdss->mmio)
208 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
209 dpu_mdss->mmio = NULL;
210 priv->mdss = NULL;
211 }
212
213 static const struct msm_mdss_funcs mdss_funcs = {
214 .enable = dpu_mdss_enable,
215 .disable = dpu_mdss_disable,
216 .destroy = dpu_mdss_destroy,
217 };
218
dpu_mdss_init(struct drm_device * dev)219 int dpu_mdss_init(struct drm_device *dev)
220 {
221 struct platform_device *pdev = to_platform_device(dev->dev);
222 struct msm_drm_private *priv = dev->dev_private;
223 struct dpu_mdss *dpu_mdss;
224 struct dss_module_power *mp;
225 int ret;
226 int irq;
227
228 dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
229 if (!dpu_mdss)
230 return -ENOMEM;
231
232 dpu_mdss->mmio = msm_ioremap(pdev, "mdss", "mdss");
233 if (IS_ERR(dpu_mdss->mmio))
234 return PTR_ERR(dpu_mdss->mmio);
235
236 DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
237
238 mp = &dpu_mdss->mp;
239 ret = msm_dss_parse_clock(pdev, mp);
240 if (ret) {
241 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
242 goto clk_parse_err;
243 }
244
245 dpu_mdss->base.dev = dev;
246 dpu_mdss->base.funcs = &mdss_funcs;
247
248 ret = _dpu_mdss_irq_domain_add(dpu_mdss);
249 if (ret)
250 goto irq_domain_error;
251
252 irq = platform_get_irq(pdev, 0);
253 if (irq < 0) {
254 ret = irq;
255 goto irq_error;
256 }
257
258 irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
259 dpu_mdss);
260
261 priv->mdss = &dpu_mdss->base;
262
263 pm_runtime_enable(dev->dev);
264
265 return 0;
266
267 irq_error:
268 _dpu_mdss_irq_domain_fini(dpu_mdss);
269 irq_domain_error:
270 msm_dss_put_clk(mp->clk_config, mp->num_clk);
271 clk_parse_err:
272 devm_kfree(&pdev->dev, mp->clk_config);
273 if (dpu_mdss->mmio)
274 devm_iounmap(&pdev->dev, dpu_mdss->mmio);
275 dpu_mdss->mmio = NULL;
276 return ret;
277 }
278