1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Aspeed 24XX/25XX I2C Controller.
4 *
5 * Copyright (C) 2012-2017 ASPEED Technology Inc.
6 * Copyright 2017 IBM Corporation
7 * Copyright 2017 Google, Inc.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/irqchip/chained_irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/reset.h>
28 #include <linux/slab.h>
29
30 /* I2C Register */
31 #define ASPEED_I2C_FUN_CTRL_REG 0x00
32 #define ASPEED_I2C_AC_TIMING_REG1 0x04
33 #define ASPEED_I2C_AC_TIMING_REG2 0x08
34 #define ASPEED_I2C_INTR_CTRL_REG 0x0c
35 #define ASPEED_I2C_INTR_STS_REG 0x10
36 #define ASPEED_I2C_CMD_REG 0x14
37 #define ASPEED_I2C_DEV_ADDR_REG 0x18
38 #define ASPEED_I2C_BYTE_BUF_REG 0x20
39
40 /* Global Register Definition */
41 /* 0x00 : I2C Interrupt Status Register */
42 /* 0x08 : I2C Interrupt Target Assignment */
43
44 /* Device Register Definition */
45 /* 0x00 : I2CD Function Control Register */
46 #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
47 #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
48 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
49 #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
50 #define ASPEED_I2CD_SLAVE_EN BIT(1)
51 #define ASPEED_I2CD_MASTER_EN BIT(0)
52
53 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
54 #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28)
55 #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24)
56 #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20)
57 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16
58 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16)
59 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12
60 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12)
61 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0)
62 #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0)
63 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
64 #define ASPEED_NO_TIMEOUT_CTRL 0
65
66 /* 0x0c : I2CD Interrupt Control Register &
67 * 0x10 : I2CD Interrupt Status Register
68 *
69 * These share bit definitions, so use the same values for the enable &
70 * status bits.
71 */
72 #define ASPEED_I2CD_INTR_RECV_MASK 0xf000ffff
73 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
74 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
75 #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
76 #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
77 #define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
78 #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
79 #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
80 #define ASPEED_I2CD_INTR_RX_DONE BIT(2)
81 #define ASPEED_I2CD_INTR_TX_NAK BIT(1)
82 #define ASPEED_I2CD_INTR_TX_ACK BIT(0)
83 #define ASPEED_I2CD_INTR_MASTER_ERRORS \
84 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
85 ASPEED_I2CD_INTR_SCL_TIMEOUT | \
86 ASPEED_I2CD_INTR_ABNORMAL | \
87 ASPEED_I2CD_INTR_ARBIT_LOSS)
88 #define ASPEED_I2CD_INTR_ALL \
89 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
90 ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \
91 ASPEED_I2CD_INTR_SCL_TIMEOUT | \
92 ASPEED_I2CD_INTR_ABNORMAL | \
93 ASPEED_I2CD_INTR_NORMAL_STOP | \
94 ASPEED_I2CD_INTR_ARBIT_LOSS | \
95 ASPEED_I2CD_INTR_RX_DONE | \
96 ASPEED_I2CD_INTR_TX_NAK | \
97 ASPEED_I2CD_INTR_TX_ACK)
98
99 /* 0x14 : I2CD Command/Status Register */
100 #define ASPEED_I2CD_SCL_LINE_STS BIT(18)
101 #define ASPEED_I2CD_SDA_LINE_STS BIT(17)
102 #define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
103 #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
104
105 /* Command Bit */
106 #define ASPEED_I2CD_M_STOP_CMD BIT(5)
107 #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
108 #define ASPEED_I2CD_M_RX_CMD BIT(3)
109 #define ASPEED_I2CD_S_TX_CMD BIT(2)
110 #define ASPEED_I2CD_M_TX_CMD BIT(1)
111 #define ASPEED_I2CD_M_START_CMD BIT(0)
112 #define ASPEED_I2CD_MASTER_CMDS_MASK \
113 (ASPEED_I2CD_M_STOP_CMD | \
114 ASPEED_I2CD_M_S_RX_CMD_LAST | \
115 ASPEED_I2CD_M_RX_CMD | \
116 ASPEED_I2CD_M_TX_CMD | \
117 ASPEED_I2CD_M_START_CMD)
118
119 /* 0x18 : I2CD Slave Device Address Register */
120 #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
121
122 enum aspeed_i2c_master_state {
123 ASPEED_I2C_MASTER_INACTIVE,
124 ASPEED_I2C_MASTER_PENDING,
125 ASPEED_I2C_MASTER_START,
126 ASPEED_I2C_MASTER_TX_FIRST,
127 ASPEED_I2C_MASTER_TX,
128 ASPEED_I2C_MASTER_RX_FIRST,
129 ASPEED_I2C_MASTER_RX,
130 ASPEED_I2C_MASTER_STOP,
131 };
132
133 enum aspeed_i2c_slave_state {
134 ASPEED_I2C_SLAVE_INACTIVE,
135 ASPEED_I2C_SLAVE_START,
136 ASPEED_I2C_SLAVE_READ_REQUESTED,
137 ASPEED_I2C_SLAVE_READ_PROCESSED,
138 ASPEED_I2C_SLAVE_WRITE_REQUESTED,
139 ASPEED_I2C_SLAVE_WRITE_RECEIVED,
140 ASPEED_I2C_SLAVE_STOP,
141 };
142
143 struct aspeed_i2c_bus {
144 struct i2c_adapter adap;
145 struct device *dev;
146 void __iomem *base;
147 struct reset_control *rst;
148 /* Synchronizes I/O mem access to base. */
149 spinlock_t lock;
150 struct completion cmd_complete;
151 u32 (*get_clk_reg_val)(struct device *dev,
152 u32 divisor);
153 unsigned long parent_clk_frequency;
154 u32 bus_frequency;
155 /* Transaction state. */
156 enum aspeed_i2c_master_state master_state;
157 struct i2c_msg *msgs;
158 size_t buf_index;
159 size_t msgs_index;
160 size_t msgs_count;
161 bool send_stop;
162 int cmd_err;
163 /* Protected only by i2c_lock_bus */
164 int master_xfer_result;
165 /* Multi-master */
166 bool multi_master;
167 #if IS_ENABLED(CONFIG_I2C_SLAVE)
168 struct i2c_client *slave;
169 enum aspeed_i2c_slave_state slave_state;
170 #endif /* CONFIG_I2C_SLAVE */
171 };
172
173 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
174
aspeed_i2c_recover_bus(struct aspeed_i2c_bus * bus)175 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
176 {
177 unsigned long time_left, flags;
178 int ret = 0;
179 u32 command;
180
181 spin_lock_irqsave(&bus->lock, flags);
182 command = readl(bus->base + ASPEED_I2C_CMD_REG);
183
184 if (command & ASPEED_I2CD_SDA_LINE_STS) {
185 /* Bus is idle: no recovery needed. */
186 if (command & ASPEED_I2CD_SCL_LINE_STS)
187 goto out;
188 dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
189 command);
190
191 reinit_completion(&bus->cmd_complete);
192 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
193 spin_unlock_irqrestore(&bus->lock, flags);
194
195 time_left = wait_for_completion_timeout(
196 &bus->cmd_complete, bus->adap.timeout);
197
198 spin_lock_irqsave(&bus->lock, flags);
199 if (time_left == 0)
200 goto reset_out;
201 else if (bus->cmd_err)
202 goto reset_out;
203 /* Recovery failed. */
204 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
205 ASPEED_I2CD_SCL_LINE_STS))
206 goto reset_out;
207 /* Bus error. */
208 } else {
209 dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
210 command);
211
212 reinit_completion(&bus->cmd_complete);
213 /* Writes 1 to 8 SCL clock cycles until SDA is released. */
214 writel(ASPEED_I2CD_BUS_RECOVER_CMD,
215 bus->base + ASPEED_I2C_CMD_REG);
216 spin_unlock_irqrestore(&bus->lock, flags);
217
218 time_left = wait_for_completion_timeout(
219 &bus->cmd_complete, bus->adap.timeout);
220
221 spin_lock_irqsave(&bus->lock, flags);
222 if (time_left == 0)
223 goto reset_out;
224 else if (bus->cmd_err)
225 goto reset_out;
226 /* Recovery failed. */
227 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
228 ASPEED_I2CD_SDA_LINE_STS))
229 goto reset_out;
230 }
231
232 out:
233 spin_unlock_irqrestore(&bus->lock, flags);
234
235 return ret;
236
237 reset_out:
238 spin_unlock_irqrestore(&bus->lock, flags);
239
240 return aspeed_i2c_reset(bus);
241 }
242
243 #if IS_ENABLED(CONFIG_I2C_SLAVE)
aspeed_i2c_slave_irq(struct aspeed_i2c_bus * bus,u32 irq_status)244 static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
245 {
246 u32 command, irq_handled = 0;
247 struct i2c_client *slave = bus->slave;
248 u8 value;
249
250 if (!slave)
251 return 0;
252
253 /*
254 * Handle stop conditions early, prior to SLAVE_MATCH. Some masters may drive
255 * transfers with low enough latency between the nak/stop phase of the current
256 * command and the start/address phase of the following command that the
257 * interrupts are coalesced by the time we process them.
258 */
259 if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
260 irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
261 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
262 }
263
264 if (irq_status & ASPEED_I2CD_INTR_TX_NAK &&
265 bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {
266 irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
267 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
268 }
269
270 /* Propagate any stop conditions to the slave implementation. */
271 if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) {
272 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
273 bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
274 }
275
276 /*
277 * Now that we've dealt with any potentially coalesced stop conditions,
278 * address any start conditions.
279 */
280 if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
281 irq_handled |= ASPEED_I2CD_INTR_SLAVE_MATCH;
282 bus->slave_state = ASPEED_I2C_SLAVE_START;
283 }
284
285 /*
286 * If the slave has been stopped and not started then slave interrupt
287 * handling is complete.
288 */
289 if (bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
290 return irq_handled;
291
292 command = readl(bus->base + ASPEED_I2C_CMD_REG);
293 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
294 irq_status, command);
295
296 /* Slave was sent something. */
297 if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
298 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
299 /* Handle address frame. */
300 if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
301 if (value & 0x1)
302 bus->slave_state =
303 ASPEED_I2C_SLAVE_READ_REQUESTED;
304 else
305 bus->slave_state =
306 ASPEED_I2C_SLAVE_WRITE_REQUESTED;
307 }
308 irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
309 }
310
311 switch (bus->slave_state) {
312 case ASPEED_I2C_SLAVE_READ_REQUESTED:
313 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_ACK))
314 dev_err(bus->dev, "Unexpected ACK on read request.\n");
315 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
316 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
317 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
318 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
319 break;
320 case ASPEED_I2C_SLAVE_READ_PROCESSED:
321 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
322 dev_err(bus->dev,
323 "Expected ACK after processed read.\n");
324 break;
325 }
326 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
327 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
328 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
329 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
330 break;
331 case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
332 bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
333 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
334 break;
335 case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
336 i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
337 break;
338 case ASPEED_I2C_SLAVE_STOP:
339 /* Stop event handling is done early. Unreachable. */
340 break;
341 case ASPEED_I2C_SLAVE_START:
342 /* Slave was just started. Waiting for the next event. */;
343 break;
344 default:
345 dev_err(bus->dev, "unknown slave_state: %d\n",
346 bus->slave_state);
347 bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
348 break;
349 }
350
351 return irq_handled;
352 }
353 #endif /* CONFIG_I2C_SLAVE */
354
355 /* precondition: bus.lock has been acquired. */
aspeed_i2c_do_start(struct aspeed_i2c_bus * bus)356 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
357 {
358 u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
359 struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
360 u8 slave_addr = i2c_8bit_addr_from_msg(msg);
361
362 #if IS_ENABLED(CONFIG_I2C_SLAVE)
363 /*
364 * If it's requested in the middle of a slave session, set the master
365 * state to 'pending' then H/W will continue handling this master
366 * command when the bus comes back to the idle state.
367 */
368 if (bus->slave_state != ASPEED_I2C_SLAVE_INACTIVE) {
369 bus->master_state = ASPEED_I2C_MASTER_PENDING;
370 return;
371 }
372 #endif /* CONFIG_I2C_SLAVE */
373
374 bus->master_state = ASPEED_I2C_MASTER_START;
375 bus->buf_index = 0;
376
377 if (msg->flags & I2C_M_RD) {
378 command |= ASPEED_I2CD_M_RX_CMD;
379 /* Need to let the hardware know to NACK after RX. */
380 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
381 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
382 }
383
384 writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
385 writel(command, bus->base + ASPEED_I2C_CMD_REG);
386 }
387
388 /* precondition: bus.lock has been acquired. */
aspeed_i2c_do_stop(struct aspeed_i2c_bus * bus)389 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
390 {
391 bus->master_state = ASPEED_I2C_MASTER_STOP;
392 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
393 }
394
395 /* precondition: bus.lock has been acquired. */
aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus * bus)396 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
397 {
398 if (bus->msgs_index + 1 < bus->msgs_count) {
399 bus->msgs_index++;
400 aspeed_i2c_do_start(bus);
401 } else {
402 aspeed_i2c_do_stop(bus);
403 }
404 }
405
aspeed_i2c_is_irq_error(u32 irq_status)406 static int aspeed_i2c_is_irq_error(u32 irq_status)
407 {
408 if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
409 return -EAGAIN;
410 if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
411 ASPEED_I2CD_INTR_SCL_TIMEOUT))
412 return -EBUSY;
413 if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
414 return -EPROTO;
415
416 return 0;
417 }
418
aspeed_i2c_master_irq(struct aspeed_i2c_bus * bus,u32 irq_status)419 static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
420 {
421 u32 irq_handled = 0, command = 0;
422 struct i2c_msg *msg;
423 u8 recv_byte;
424 int ret;
425
426 if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
427 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
428 irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
429 goto out_complete;
430 }
431
432 /*
433 * We encountered an interrupt that reports an error: the hardware
434 * should clear the command queue effectively taking us back to the
435 * INACTIVE state.
436 */
437 ret = aspeed_i2c_is_irq_error(irq_status);
438 if (ret) {
439 dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
440 irq_status);
441 irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
442 if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
443 bus->cmd_err = ret;
444 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
445 goto out_complete;
446 }
447 }
448
449 /* Master is not currently active, irq was for someone else. */
450 if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE ||
451 bus->master_state == ASPEED_I2C_MASTER_PENDING)
452 goto out_no_complete;
453
454 /* We are in an invalid state; reset bus to a known state. */
455 if (!bus->msgs) {
456 dev_err(bus->dev, "bus in unknown state. irq_status: 0x%x\n",
457 irq_status);
458 bus->cmd_err = -EIO;
459 if (bus->master_state != ASPEED_I2C_MASTER_STOP &&
460 bus->master_state != ASPEED_I2C_MASTER_INACTIVE)
461 aspeed_i2c_do_stop(bus);
462 goto out_no_complete;
463 }
464 msg = &bus->msgs[bus->msgs_index];
465
466 /*
467 * START is a special case because we still have to handle a subsequent
468 * TX or RX immediately after we handle it, so we handle it here and
469 * then update the state and handle the new state below.
470 */
471 if (bus->master_state == ASPEED_I2C_MASTER_START) {
472 #if IS_ENABLED(CONFIG_I2C_SLAVE)
473 /*
474 * If a peer master starts a xfer immediately after it queues a
475 * master command, clear the queued master command and change
476 * its state to 'pending'. To simplify handling of pending
477 * cases, it uses S/W solution instead of H/W command queue
478 * handling.
479 */
480 if (unlikely(irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH)) {
481 writel(readl(bus->base + ASPEED_I2C_CMD_REG) &
482 ~ASPEED_I2CD_MASTER_CMDS_MASK,
483 bus->base + ASPEED_I2C_CMD_REG);
484 bus->master_state = ASPEED_I2C_MASTER_PENDING;
485 dev_dbg(bus->dev,
486 "master goes pending due to a slave start\n");
487 goto out_no_complete;
488 }
489 #endif /* CONFIG_I2C_SLAVE */
490 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
491 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
492 bus->cmd_err = -ENXIO;
493 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
494 goto out_complete;
495 }
496 pr_devel("no slave present at %02x\n", msg->addr);
497 irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
498 bus->cmd_err = -ENXIO;
499 aspeed_i2c_do_stop(bus);
500 goto out_no_complete;
501 }
502 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
503 if (msg->len == 0) { /* SMBUS_QUICK */
504 aspeed_i2c_do_stop(bus);
505 goto out_no_complete;
506 }
507 if (msg->flags & I2C_M_RD)
508 bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
509 else
510 bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
511 }
512
513 switch (bus->master_state) {
514 case ASPEED_I2C_MASTER_TX:
515 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
516 dev_dbg(bus->dev, "slave NACKed TX\n");
517 irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
518 goto error_and_stop;
519 } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
520 dev_err(bus->dev, "slave failed to ACK TX\n");
521 goto error_and_stop;
522 }
523 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
524 fallthrough;
525 case ASPEED_I2C_MASTER_TX_FIRST:
526 if (bus->buf_index < msg->len) {
527 bus->master_state = ASPEED_I2C_MASTER_TX;
528 writel(msg->buf[bus->buf_index++],
529 bus->base + ASPEED_I2C_BYTE_BUF_REG);
530 writel(ASPEED_I2CD_M_TX_CMD,
531 bus->base + ASPEED_I2C_CMD_REG);
532 } else {
533 aspeed_i2c_next_msg_or_stop(bus);
534 }
535 goto out_no_complete;
536 case ASPEED_I2C_MASTER_RX_FIRST:
537 /* RX may not have completed yet (only address cycle) */
538 if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
539 goto out_no_complete;
540 fallthrough;
541 case ASPEED_I2C_MASTER_RX:
542 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
543 dev_err(bus->dev, "master failed to RX\n");
544 goto error_and_stop;
545 }
546 irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
547
548 recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
549 msg->buf[bus->buf_index++] = recv_byte;
550
551 if (msg->flags & I2C_M_RECV_LEN) {
552 if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
553 bus->cmd_err = -EPROTO;
554 aspeed_i2c_do_stop(bus);
555 goto out_no_complete;
556 }
557 msg->len = recv_byte +
558 ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
559 msg->flags &= ~I2C_M_RECV_LEN;
560 }
561
562 if (bus->buf_index < msg->len) {
563 bus->master_state = ASPEED_I2C_MASTER_RX;
564 command = ASPEED_I2CD_M_RX_CMD;
565 if (bus->buf_index + 1 == msg->len)
566 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
567 writel(command, bus->base + ASPEED_I2C_CMD_REG);
568 } else {
569 aspeed_i2c_next_msg_or_stop(bus);
570 }
571 goto out_no_complete;
572 case ASPEED_I2C_MASTER_STOP:
573 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
574 dev_err(bus->dev,
575 "master failed to STOP. irq_status:0x%x\n",
576 irq_status);
577 bus->cmd_err = -EIO;
578 /* Do not STOP as we have already tried. */
579 } else {
580 irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
581 }
582
583 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
584 goto out_complete;
585 case ASPEED_I2C_MASTER_INACTIVE:
586 dev_err(bus->dev,
587 "master received interrupt 0x%08x, but is inactive\n",
588 irq_status);
589 bus->cmd_err = -EIO;
590 /* Do not STOP as we should be inactive. */
591 goto out_complete;
592 default:
593 WARN(1, "unknown master state\n");
594 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
595 bus->cmd_err = -EINVAL;
596 goto out_complete;
597 }
598 error_and_stop:
599 bus->cmd_err = -EIO;
600 aspeed_i2c_do_stop(bus);
601 goto out_no_complete;
602 out_complete:
603 bus->msgs = NULL;
604 if (bus->cmd_err)
605 bus->master_xfer_result = bus->cmd_err;
606 else
607 bus->master_xfer_result = bus->msgs_index + 1;
608 complete(&bus->cmd_complete);
609 out_no_complete:
610 return irq_handled;
611 }
612
aspeed_i2c_bus_irq(int irq,void * dev_id)613 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
614 {
615 struct aspeed_i2c_bus *bus = dev_id;
616 u32 irq_received, irq_remaining, irq_handled;
617
618 spin_lock(&bus->lock);
619 irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
620 /* Ack all interrupts except for Rx done */
621 writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
622 bus->base + ASPEED_I2C_INTR_STS_REG);
623 readl(bus->base + ASPEED_I2C_INTR_STS_REG);
624 irq_received &= ASPEED_I2CD_INTR_RECV_MASK;
625 irq_remaining = irq_received;
626
627 #if IS_ENABLED(CONFIG_I2C_SLAVE)
628 /*
629 * In most cases, interrupt bits will be set one by one, although
630 * multiple interrupt bits could be set at the same time. It's also
631 * possible that master interrupt bits could be set along with slave
632 * interrupt bits. Each case needs to be handled using corresponding
633 * handlers depending on the current state.
634 */
635 if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE &&
636 bus->master_state != ASPEED_I2C_MASTER_PENDING) {
637 irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
638 irq_remaining &= ~irq_handled;
639 if (irq_remaining)
640 irq_handled |= aspeed_i2c_slave_irq(bus, irq_remaining);
641 } else {
642 irq_handled = aspeed_i2c_slave_irq(bus, irq_remaining);
643 irq_remaining &= ~irq_handled;
644 if (irq_remaining)
645 irq_handled |= aspeed_i2c_master_irq(bus,
646 irq_remaining);
647 }
648
649 /*
650 * Start a pending master command at here if a slave operation is
651 * completed.
652 */
653 if (bus->master_state == ASPEED_I2C_MASTER_PENDING &&
654 bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE)
655 aspeed_i2c_do_start(bus);
656 #else
657 irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
658 #endif /* CONFIG_I2C_SLAVE */
659
660 irq_remaining &= ~irq_handled;
661 if (irq_remaining)
662 dev_err(bus->dev,
663 "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
664 irq_received, irq_handled);
665
666 /* Ack Rx done */
667 if (irq_received & ASPEED_I2CD_INTR_RX_DONE) {
668 writel(ASPEED_I2CD_INTR_RX_DONE,
669 bus->base + ASPEED_I2C_INTR_STS_REG);
670 readl(bus->base + ASPEED_I2C_INTR_STS_REG);
671 }
672 spin_unlock(&bus->lock);
673 return irq_remaining ? IRQ_NONE : IRQ_HANDLED;
674 }
675
aspeed_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)676 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
677 struct i2c_msg *msgs, int num)
678 {
679 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
680 unsigned long time_left, flags;
681
682 spin_lock_irqsave(&bus->lock, flags);
683 bus->cmd_err = 0;
684
685 /* If bus is busy in a single master environment, attempt recovery. */
686 if (!bus->multi_master &&
687 (readl(bus->base + ASPEED_I2C_CMD_REG) &
688 ASPEED_I2CD_BUS_BUSY_STS)) {
689 int ret;
690
691 spin_unlock_irqrestore(&bus->lock, flags);
692 ret = aspeed_i2c_recover_bus(bus);
693 if (ret)
694 return ret;
695 spin_lock_irqsave(&bus->lock, flags);
696 }
697
698 bus->cmd_err = 0;
699 bus->msgs = msgs;
700 bus->msgs_index = 0;
701 bus->msgs_count = num;
702
703 reinit_completion(&bus->cmd_complete);
704 aspeed_i2c_do_start(bus);
705 spin_unlock_irqrestore(&bus->lock, flags);
706
707 time_left = wait_for_completion_timeout(&bus->cmd_complete,
708 bus->adap.timeout);
709
710 if (time_left == 0) {
711 /*
712 * In a multi-master setup, if a timeout occurs, attempt
713 * recovery. But if the bus is idle, we still need to reset the
714 * i2c controller to clear the remaining interrupts.
715 */
716 if (bus->multi_master &&
717 (readl(bus->base + ASPEED_I2C_CMD_REG) &
718 ASPEED_I2CD_BUS_BUSY_STS))
719 aspeed_i2c_recover_bus(bus);
720 else
721 aspeed_i2c_reset(bus);
722
723 /*
724 * If timed out and the state is still pending, drop the pending
725 * master command.
726 */
727 spin_lock_irqsave(&bus->lock, flags);
728 if (bus->master_state == ASPEED_I2C_MASTER_PENDING)
729 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
730 spin_unlock_irqrestore(&bus->lock, flags);
731
732 return -ETIMEDOUT;
733 }
734
735 return bus->master_xfer_result;
736 }
737
aspeed_i2c_functionality(struct i2c_adapter * adap)738 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
739 {
740 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
741 }
742
743 #if IS_ENABLED(CONFIG_I2C_SLAVE)
744 /* precondition: bus.lock has been acquired. */
__aspeed_i2c_reg_slave(struct aspeed_i2c_bus * bus,u16 slave_addr)745 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
746 {
747 u32 addr_reg_val, func_ctrl_reg_val;
748
749 /* Set slave addr. */
750 addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG);
751 addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
752 addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
753 writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
754
755 /* Turn on slave mode. */
756 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
757 func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
758 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
759
760 bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE;
761 }
762
aspeed_i2c_reg_slave(struct i2c_client * client)763 static int aspeed_i2c_reg_slave(struct i2c_client *client)
764 {
765 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
766 unsigned long flags;
767
768 spin_lock_irqsave(&bus->lock, flags);
769 if (bus->slave) {
770 spin_unlock_irqrestore(&bus->lock, flags);
771 return -EINVAL;
772 }
773
774 __aspeed_i2c_reg_slave(bus, client->addr);
775
776 bus->slave = client;
777 spin_unlock_irqrestore(&bus->lock, flags);
778
779 return 0;
780 }
781
aspeed_i2c_unreg_slave(struct i2c_client * client)782 static int aspeed_i2c_unreg_slave(struct i2c_client *client)
783 {
784 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
785 u32 func_ctrl_reg_val;
786 unsigned long flags;
787
788 spin_lock_irqsave(&bus->lock, flags);
789 if (!bus->slave) {
790 spin_unlock_irqrestore(&bus->lock, flags);
791 return -EINVAL;
792 }
793
794 /* Turn off slave mode. */
795 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
796 func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
797 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
798
799 bus->slave = NULL;
800 spin_unlock_irqrestore(&bus->lock, flags);
801
802 return 0;
803 }
804 #endif /* CONFIG_I2C_SLAVE */
805
806 static const struct i2c_algorithm aspeed_i2c_algo = {
807 .master_xfer = aspeed_i2c_master_xfer,
808 .functionality = aspeed_i2c_functionality,
809 #if IS_ENABLED(CONFIG_I2C_SLAVE)
810 .reg_slave = aspeed_i2c_reg_slave,
811 .unreg_slave = aspeed_i2c_unreg_slave,
812 #endif /* CONFIG_I2C_SLAVE */
813 };
814
aspeed_i2c_get_clk_reg_val(struct device * dev,u32 clk_high_low_mask,u32 divisor)815 static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
816 u32 clk_high_low_mask,
817 u32 divisor)
818 {
819 u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
820
821 /*
822 * SCL_high and SCL_low represent a value 1 greater than what is stored
823 * since a zero divider is meaningless. Thus, the max value each can
824 * store is every bit set + 1. Since SCL_high and SCL_low are added
825 * together (see below), the max value of both is the max value of one
826 * them times two.
827 */
828 clk_high_low_max = (clk_high_low_mask + 1) * 2;
829
830 /*
831 * The actual clock frequency of SCL is:
832 * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
833 * = APB_freq / divisor
834 * where base_freq is a programmable clock divider; its value is
835 * base_freq = 1 << base_clk_divisor
836 * SCL_high is the number of base_freq clock cycles that SCL stays high
837 * and SCL_low is the number of base_freq clock cycles that SCL stays
838 * low for a period of SCL.
839 * The actual register has a minimum SCL_high and SCL_low minimum of 1;
840 * thus, they start counting at zero. So
841 * SCL_high = clk_high + 1
842 * SCL_low = clk_low + 1
843 * Thus,
844 * SCL_freq = APB_freq /
845 * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
846 * The documentation recommends clk_high >= clk_high_max / 2 and
847 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
848 * gives us the following solution:
849 */
850 base_clk_divisor = divisor > clk_high_low_max ?
851 ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
852
853 if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
854 base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
855 clk_low = clk_high_low_mask;
856 clk_high = clk_high_low_mask;
857 dev_err(dev,
858 "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
859 divisor, (1 << base_clk_divisor) * clk_high_low_max);
860 } else {
861 tmp = (divisor + (1 << base_clk_divisor) - 1)
862 >> base_clk_divisor;
863 clk_low = tmp / 2;
864 clk_high = tmp - clk_low;
865
866 if (clk_high)
867 clk_high--;
868
869 if (clk_low)
870 clk_low--;
871 }
872
873
874 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
875 & ASPEED_I2CD_TIME_SCL_HIGH_MASK)
876 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
877 & ASPEED_I2CD_TIME_SCL_LOW_MASK)
878 | (base_clk_divisor
879 & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
880 }
881
aspeed_i2c_24xx_get_clk_reg_val(struct device * dev,u32 divisor)882 static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
883 {
884 /*
885 * clk_high and clk_low are each 3 bits wide, so each can hold a max
886 * value of 8 giving a clk_high_low_max of 16.
887 */
888 return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
889 }
890
aspeed_i2c_25xx_get_clk_reg_val(struct device * dev,u32 divisor)891 static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
892 {
893 /*
894 * clk_high and clk_low are each 4 bits wide, so each can hold a max
895 * value of 16 giving a clk_high_low_max of 32.
896 */
897 return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
898 }
899
900 /* precondition: bus.lock has been acquired. */
aspeed_i2c_init_clk(struct aspeed_i2c_bus * bus)901 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
902 {
903 u32 divisor, clk_reg_val;
904
905 divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
906 clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
907 clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
908 ASPEED_I2CD_TIME_THDSTA_MASK |
909 ASPEED_I2CD_TIME_TACST_MASK);
910 clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
911 writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
912 writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
913
914 return 0;
915 }
916
917 /* precondition: bus.lock has been acquired. */
aspeed_i2c_init(struct aspeed_i2c_bus * bus,struct platform_device * pdev)918 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
919 struct platform_device *pdev)
920 {
921 u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
922 int ret;
923
924 /* Disable everything. */
925 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
926
927 ret = aspeed_i2c_init_clk(bus);
928 if (ret < 0)
929 return ret;
930
931 if (of_property_read_bool(pdev->dev.of_node, "multi-master"))
932 bus->multi_master = true;
933 else
934 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
935
936 /* Enable Master Mode */
937 writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
938 bus->base + ASPEED_I2C_FUN_CTRL_REG);
939
940 #if IS_ENABLED(CONFIG_I2C_SLAVE)
941 /* If slave has already been registered, re-enable it. */
942 if (bus->slave)
943 __aspeed_i2c_reg_slave(bus, bus->slave->addr);
944 #endif /* CONFIG_I2C_SLAVE */
945
946 /* Set interrupt generation of I2C controller */
947 writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
948
949 return 0;
950 }
951
aspeed_i2c_reset(struct aspeed_i2c_bus * bus)952 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
953 {
954 struct platform_device *pdev = to_platform_device(bus->dev);
955 unsigned long flags;
956 int ret;
957
958 spin_lock_irqsave(&bus->lock, flags);
959
960 /* Disable and ack all interrupts. */
961 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
962 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
963
964 ret = aspeed_i2c_init(bus, pdev);
965
966 spin_unlock_irqrestore(&bus->lock, flags);
967
968 return ret;
969 }
970
971 static const struct of_device_id aspeed_i2c_bus_of_table[] = {
972 {
973 .compatible = "aspeed,ast2400-i2c-bus",
974 .data = aspeed_i2c_24xx_get_clk_reg_val,
975 },
976 {
977 .compatible = "aspeed,ast2500-i2c-bus",
978 .data = aspeed_i2c_25xx_get_clk_reg_val,
979 },
980 {
981 .compatible = "aspeed,ast2600-i2c-bus",
982 .data = aspeed_i2c_25xx_get_clk_reg_val,
983 },
984 { },
985 };
986 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
987
aspeed_i2c_probe_bus(struct platform_device * pdev)988 static int aspeed_i2c_probe_bus(struct platform_device *pdev)
989 {
990 const struct of_device_id *match;
991 struct aspeed_i2c_bus *bus;
992 struct clk *parent_clk;
993 struct resource *res;
994 int irq, ret;
995
996 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
997 if (!bus)
998 return -ENOMEM;
999
1000 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001 bus->base = devm_ioremap_resource(&pdev->dev, res);
1002 if (IS_ERR(bus->base))
1003 return PTR_ERR(bus->base);
1004
1005 parent_clk = devm_clk_get(&pdev->dev, NULL);
1006 if (IS_ERR(parent_clk))
1007 return PTR_ERR(parent_clk);
1008 bus->parent_clk_frequency = clk_get_rate(parent_clk);
1009 /* We just need the clock rate, we don't actually use the clk object. */
1010 devm_clk_put(&pdev->dev, parent_clk);
1011
1012 bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
1013 if (IS_ERR(bus->rst)) {
1014 dev_err(&pdev->dev,
1015 "missing or invalid reset controller device tree entry\n");
1016 return PTR_ERR(bus->rst);
1017 }
1018 reset_control_deassert(bus->rst);
1019
1020 ret = of_property_read_u32(pdev->dev.of_node,
1021 "bus-frequency", &bus->bus_frequency);
1022 if (ret < 0) {
1023 dev_err(&pdev->dev,
1024 "Could not read bus-frequency property\n");
1025 bus->bus_frequency = I2C_MAX_STANDARD_MODE_FREQ;
1026 }
1027
1028 match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
1029 if (!match)
1030 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
1031 else
1032 bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
1033 match->data;
1034
1035 /* Initialize the I2C adapter */
1036 spin_lock_init(&bus->lock);
1037 init_completion(&bus->cmd_complete);
1038 bus->adap.owner = THIS_MODULE;
1039 bus->adap.retries = 0;
1040 bus->adap.algo = &aspeed_i2c_algo;
1041 bus->adap.dev.parent = &pdev->dev;
1042 bus->adap.dev.of_node = pdev->dev.of_node;
1043 strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
1044 i2c_set_adapdata(&bus->adap, bus);
1045
1046 bus->dev = &pdev->dev;
1047
1048 /* Clean up any left over interrupt state. */
1049 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
1050 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
1051 /*
1052 * bus.lock does not need to be held because the interrupt handler has
1053 * not been enabled yet.
1054 */
1055 ret = aspeed_i2c_init(bus, pdev);
1056 if (ret < 0)
1057 return ret;
1058
1059 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1060 ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
1061 0, dev_name(&pdev->dev), bus);
1062 if (ret < 0)
1063 return ret;
1064
1065 ret = i2c_add_adapter(&bus->adap);
1066 if (ret < 0)
1067 return ret;
1068
1069 platform_set_drvdata(pdev, bus);
1070
1071 dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
1072 bus->adap.nr, irq);
1073
1074 return 0;
1075 }
1076
aspeed_i2c_remove_bus(struct platform_device * pdev)1077 static int aspeed_i2c_remove_bus(struct platform_device *pdev)
1078 {
1079 struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
1080 unsigned long flags;
1081
1082 spin_lock_irqsave(&bus->lock, flags);
1083
1084 /* Disable everything. */
1085 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
1086 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
1087
1088 spin_unlock_irqrestore(&bus->lock, flags);
1089
1090 reset_control_assert(bus->rst);
1091
1092 i2c_del_adapter(&bus->adap);
1093
1094 return 0;
1095 }
1096
1097 static struct platform_driver aspeed_i2c_bus_driver = {
1098 .probe = aspeed_i2c_probe_bus,
1099 .remove = aspeed_i2c_remove_bus,
1100 .driver = {
1101 .name = "aspeed-i2c-bus",
1102 .of_match_table = aspeed_i2c_bus_of_table,
1103 },
1104 };
1105 module_platform_driver(aspeed_i2c_bus_driver);
1106
1107 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
1108 MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
1109 MODULE_LICENSE("GPL v2");
1110