1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 * Inspired from: fsl-imx25-tsadc
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdesc.h>
16 #include <linux/irqdomain.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24
25 #include "stm32-adc-core.h"
26
27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
28
29 /* SYSCFG registers */
30 #define STM32MP1_SYSCFG_PMCSETR 0x04
31 #define STM32MP1_SYSCFG_PMCCLRR 0x44
32
33 /* SYSCFG bit fields */
34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
35
36 /* SYSCFG capability flags */
37 #define HAS_VBOOSTER BIT(0)
38 #define HAS_ANASWVDD BIT(1)
39
40 /**
41 * struct stm32_adc_common_regs - stm32 common registers
42 * @csr: common status register offset
43 * @ccr: common control register offset
44 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
45 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
46 * @ier: interrupt enable register offset for each adc
47 * @eocie_msk: end of conversion interrupt enable mask in @ier
48 */
49 struct stm32_adc_common_regs {
50 u32 csr;
51 u32 ccr;
52 u32 eoc_msk[STM32_ADC_MAX_ADCS];
53 u32 ovr_msk[STM32_ADC_MAX_ADCS];
54 u32 ier;
55 u32 eocie_msk;
56 };
57
58 struct stm32_adc_priv;
59
60 /**
61 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
62 * @regs: common registers for all instances
63 * @clk_sel: clock selection routine
64 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
65 * @has_syscfg: SYSCFG capability flags
66 * @num_irqs: number of interrupt lines
67 * @num_adcs: maximum number of ADC instances in the common registers
68 */
69 struct stm32_adc_priv_cfg {
70 const struct stm32_adc_common_regs *regs;
71 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
72 u32 max_clk_rate_hz;
73 unsigned int has_syscfg;
74 unsigned int num_irqs;
75 unsigned int num_adcs;
76 };
77
78 /**
79 * struct stm32_adc_priv - stm32 ADC core private data
80 * @irq: irq(s) for ADC block
81 * @domain: irq domain reference
82 * @aclk: clock reference for the analog circuitry
83 * @bclk: bus clock common for all ADCs, depends on part used
84 * @max_clk_rate: desired maximum clock rate
85 * @booster: booster supply reference
86 * @vdd: vdd supply reference
87 * @vdda: vdda analog supply reference
88 * @vref: regulator reference
89 * @vdd_uv: vdd supply voltage (microvolts)
90 * @vdda_uv: vdda supply voltage (microvolts)
91 * @cfg: compatible configuration data
92 * @common: common data for all ADC instances
93 * @ccr_bak: backup CCR in low power mode
94 * @syscfg: reference to syscon, system control registers
95 */
96 struct stm32_adc_priv {
97 int irq[STM32_ADC_MAX_ADCS];
98 struct irq_domain *domain;
99 struct clk *aclk;
100 struct clk *bclk;
101 u32 max_clk_rate;
102 struct regulator *booster;
103 struct regulator *vdd;
104 struct regulator *vdda;
105 struct regulator *vref;
106 int vdd_uv;
107 int vdda_uv;
108 const struct stm32_adc_priv_cfg *cfg;
109 struct stm32_adc_common common;
110 u32 ccr_bak;
111 struct regmap *syscfg;
112 };
113
to_stm32_adc_priv(struct stm32_adc_common * com)114 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
115 {
116 return container_of(com, struct stm32_adc_priv, common);
117 }
118
119 /* STM32F4 ADC internal common clock prescaler division ratios */
120 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
121
122 /**
123 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
124 * @pdev: platform device
125 * @priv: stm32 ADC core private data
126 * Select clock prescaler used for analog conversions, before using ADC.
127 */
stm32f4_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)128 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
129 struct stm32_adc_priv *priv)
130 {
131 unsigned long rate;
132 u32 val;
133 int i;
134
135 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
136 if (!priv->aclk) {
137 dev_err(&pdev->dev, "No 'adc' clock found\n");
138 return -ENOENT;
139 }
140
141 rate = clk_get_rate(priv->aclk);
142 if (!rate) {
143 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
144 return -EINVAL;
145 }
146
147 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
148 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
149 break;
150 }
151 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
152 dev_err(&pdev->dev, "adc clk selection failed\n");
153 return -EINVAL;
154 }
155
156 priv->common.rate = rate / stm32f4_pclk_div[i];
157 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
158 val &= ~STM32F4_ADC_ADCPRE_MASK;
159 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
160 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
161
162 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
163 priv->common.rate / 1000);
164
165 return 0;
166 }
167
168 /**
169 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
170 * @ckmode: ADC clock mode, Async or sync with prescaler.
171 * @presc: prescaler bitfield for async clock mode
172 * @div: prescaler division ratio
173 */
174 struct stm32h7_adc_ck_spec {
175 u32 ckmode;
176 u32 presc;
177 int div;
178 };
179
180 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
181 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
182 { 0, 0, 1 },
183 { 0, 1, 2 },
184 { 0, 2, 4 },
185 { 0, 3, 6 },
186 { 0, 4, 8 },
187 { 0, 5, 10 },
188 { 0, 6, 12 },
189 { 0, 7, 16 },
190 { 0, 8, 32 },
191 { 0, 9, 64 },
192 { 0, 10, 128 },
193 { 0, 11, 256 },
194 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
195 { 1, 0, 1 },
196 { 2, 0, 2 },
197 { 3, 0, 4 },
198 };
199
stm32h7_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)200 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
201 struct stm32_adc_priv *priv)
202 {
203 u32 ckmode, presc, val;
204 unsigned long rate;
205 int i, div;
206
207 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
208 if (!priv->bclk) {
209 dev_err(&pdev->dev, "No 'bus' clock found\n");
210 return -ENOENT;
211 }
212
213 /*
214 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
215 * So, choice is to have bus clock mandatory and adc clock optional.
216 * If optional 'adc' clock has been found, then try to use it first.
217 */
218 if (priv->aclk) {
219 /*
220 * Asynchronous clock modes (e.g. ckmode == 0)
221 * From spec: PLL output musn't exceed max rate
222 */
223 rate = clk_get_rate(priv->aclk);
224 if (!rate) {
225 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
226 return -EINVAL;
227 }
228
229 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
230 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
231 presc = stm32h7_adc_ckmodes_spec[i].presc;
232 div = stm32h7_adc_ckmodes_spec[i].div;
233
234 if (ckmode)
235 continue;
236
237 if ((rate / div) <= priv->max_clk_rate)
238 goto out;
239 }
240 }
241
242 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
243 rate = clk_get_rate(priv->bclk);
244 if (!rate) {
245 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
246 return -EINVAL;
247 }
248
249 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
250 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
251 presc = stm32h7_adc_ckmodes_spec[i].presc;
252 div = stm32h7_adc_ckmodes_spec[i].div;
253
254 if (!ckmode)
255 continue;
256
257 if ((rate / div) <= priv->max_clk_rate)
258 goto out;
259 }
260
261 dev_err(&pdev->dev, "adc clk selection failed\n");
262 return -EINVAL;
263
264 out:
265 /* rate used later by each ADC instance to control BOOST mode */
266 priv->common.rate = rate / div;
267
268 /* Set common clock mode and prescaler */
269 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
270 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
271 val |= ckmode << STM32H7_CKMODE_SHIFT;
272 val |= presc << STM32H7_PRESC_SHIFT;
273 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
274
275 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
276 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
277
278 return 0;
279 }
280
281 /* STM32F4 common registers definitions */
282 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
283 .csr = STM32F4_ADC_CSR,
284 .ccr = STM32F4_ADC_CCR,
285 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
286 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
287 .ier = STM32F4_ADC_CR1,
288 .eocie_msk = STM32F4_EOCIE,
289 };
290
291 /* STM32H7 common registers definitions */
292 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
293 .csr = STM32H7_ADC_CSR,
294 .ccr = STM32H7_ADC_CCR,
295 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
296 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
297 .ier = STM32H7_ADC_IER,
298 .eocie_msk = STM32H7_EOCIE,
299 };
300
301 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
302 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
303 };
304
stm32_adc_eoc_enabled(struct stm32_adc_priv * priv,unsigned int adc)305 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
306 unsigned int adc)
307 {
308 u32 ier, offset = stm32_adc_offset[adc];
309
310 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
311
312 return ier & priv->cfg->regs->eocie_msk;
313 }
314
315 /* ADC common interrupt for all instances */
stm32_adc_irq_handler(struct irq_desc * desc)316 static void stm32_adc_irq_handler(struct irq_desc *desc)
317 {
318 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
319 struct irq_chip *chip = irq_desc_get_chip(desc);
320 int i;
321 u32 status;
322
323 chained_irq_enter(chip, desc);
324 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
325
326 /*
327 * End of conversion may be handled by using IRQ or DMA. There may be a
328 * race here when two conversions complete at the same time on several
329 * ADCs. EOC may be read 'set' for several ADCs, with:
330 * - an ADC configured to use DMA (EOC triggers the DMA request, and
331 * is then automatically cleared by DR read in hardware)
332 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
333 * be called in this case)
334 * So both EOC status bit in CSR and EOCIE control bit must be checked
335 * before invoking the interrupt handler (e.g. call ISR only for
336 * IRQ-enabled ADCs).
337 */
338 for (i = 0; i < priv->cfg->num_adcs; i++) {
339 if ((status & priv->cfg->regs->eoc_msk[i] &&
340 stm32_adc_eoc_enabled(priv, i)) ||
341 (status & priv->cfg->regs->ovr_msk[i]))
342 generic_handle_irq(irq_find_mapping(priv->domain, i));
343 }
344
345 chained_irq_exit(chip, desc);
346 };
347
stm32_adc_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)348 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
349 irq_hw_number_t hwirq)
350 {
351 irq_set_chip_data(irq, d->host_data);
352 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
353
354 return 0;
355 }
356
stm32_adc_domain_unmap(struct irq_domain * d,unsigned int irq)357 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
358 {
359 irq_set_chip_and_handler(irq, NULL, NULL);
360 irq_set_chip_data(irq, NULL);
361 }
362
363 static const struct irq_domain_ops stm32_adc_domain_ops = {
364 .map = stm32_adc_domain_map,
365 .unmap = stm32_adc_domain_unmap,
366 .xlate = irq_domain_xlate_onecell,
367 };
368
stm32_adc_irq_probe(struct platform_device * pdev,struct stm32_adc_priv * priv)369 static int stm32_adc_irq_probe(struct platform_device *pdev,
370 struct stm32_adc_priv *priv)
371 {
372 struct device_node *np = pdev->dev.of_node;
373 unsigned int i;
374
375 /*
376 * Interrupt(s) must be provided, depending on the compatible:
377 * - stm32f4/h7 shares a common interrupt line.
378 * - stm32mp1, has one line per ADC
379 */
380 for (i = 0; i < priv->cfg->num_irqs; i++) {
381 priv->irq[i] = platform_get_irq(pdev, i);
382 if (priv->irq[i] < 0)
383 return priv->irq[i];
384 }
385
386 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
387 &stm32_adc_domain_ops,
388 priv);
389 if (!priv->domain) {
390 dev_err(&pdev->dev, "Failed to add irq domain\n");
391 return -ENOMEM;
392 }
393
394 for (i = 0; i < priv->cfg->num_irqs; i++) {
395 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
396 irq_set_handler_data(priv->irq[i], priv);
397 }
398
399 return 0;
400 }
401
stm32_adc_irq_remove(struct platform_device * pdev,struct stm32_adc_priv * priv)402 static void stm32_adc_irq_remove(struct platform_device *pdev,
403 struct stm32_adc_priv *priv)
404 {
405 int hwirq;
406 unsigned int i;
407
408 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
409 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
410 irq_domain_remove(priv->domain);
411
412 for (i = 0; i < priv->cfg->num_irqs; i++)
413 irq_set_chained_handler(priv->irq[i], NULL);
414 }
415
stm32_adc_core_switches_supply_en(struct stm32_adc_priv * priv,struct device * dev)416 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
417 struct device *dev)
418 {
419 int ret;
420
421 /*
422 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
423 * switches (via PCSEL) which have reduced performances when their
424 * supply is below 2.7V (vdda by default):
425 * - Voltage booster can be used, to get full ADC performances
426 * (increases power consumption).
427 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
428 *
429 * Recommended settings for ANASWVDD and EN_BOOSTER:
430 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
431 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
432 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
433 */
434 if (priv->vdda_uv < 2700000) {
435 if (priv->syscfg && priv->vdd_uv > 2700000) {
436 ret = regulator_enable(priv->vdd);
437 if (ret < 0) {
438 dev_err(dev, "vdd enable failed %d\n", ret);
439 return ret;
440 }
441
442 ret = regmap_write(priv->syscfg,
443 STM32MP1_SYSCFG_PMCSETR,
444 STM32MP1_SYSCFG_ANASWVDD_MASK);
445 if (ret < 0) {
446 regulator_disable(priv->vdd);
447 dev_err(dev, "vdd select failed, %d\n", ret);
448 return ret;
449 }
450 dev_dbg(dev, "analog switches supplied by vdd\n");
451
452 return 0;
453 }
454
455 if (priv->booster) {
456 /*
457 * This is optional, as this is a trade-off between
458 * analog performance and power consumption.
459 */
460 ret = regulator_enable(priv->booster);
461 if (ret < 0) {
462 dev_err(dev, "booster enable failed %d\n", ret);
463 return ret;
464 }
465 dev_dbg(dev, "analog switches supplied by booster\n");
466
467 return 0;
468 }
469 }
470
471 /* Fallback using vdda (default), nothing to do */
472 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
473 priv->vdda_uv);
474
475 return 0;
476 }
477
stm32_adc_core_switches_supply_dis(struct stm32_adc_priv * priv)478 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
479 {
480 if (priv->vdda_uv < 2700000) {
481 if (priv->syscfg && priv->vdd_uv > 2700000) {
482 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
483 STM32MP1_SYSCFG_ANASWVDD_MASK);
484 regulator_disable(priv->vdd);
485 return;
486 }
487 if (priv->booster)
488 regulator_disable(priv->booster);
489 }
490 }
491
stm32_adc_core_hw_start(struct device * dev)492 static int stm32_adc_core_hw_start(struct device *dev)
493 {
494 struct stm32_adc_common *common = dev_get_drvdata(dev);
495 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
496 int ret;
497
498 ret = regulator_enable(priv->vdda);
499 if (ret < 0) {
500 dev_err(dev, "vdda enable failed %d\n", ret);
501 return ret;
502 }
503
504 ret = regulator_get_voltage(priv->vdda);
505 if (ret < 0) {
506 dev_err(dev, "vdda get voltage failed, %d\n", ret);
507 goto err_vdda_disable;
508 }
509 priv->vdda_uv = ret;
510
511 ret = stm32_adc_core_switches_supply_en(priv, dev);
512 if (ret < 0)
513 goto err_vdda_disable;
514
515 ret = regulator_enable(priv->vref);
516 if (ret < 0) {
517 dev_err(dev, "vref enable failed\n");
518 goto err_switches_dis;
519 }
520
521 if (priv->bclk) {
522 ret = clk_prepare_enable(priv->bclk);
523 if (ret < 0) {
524 dev_err(dev, "bus clk enable failed\n");
525 goto err_regulator_disable;
526 }
527 }
528
529 if (priv->aclk) {
530 ret = clk_prepare_enable(priv->aclk);
531 if (ret < 0) {
532 dev_err(dev, "adc clk enable failed\n");
533 goto err_bclk_disable;
534 }
535 }
536
537 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
538
539 return 0;
540
541 err_bclk_disable:
542 if (priv->bclk)
543 clk_disable_unprepare(priv->bclk);
544 err_regulator_disable:
545 regulator_disable(priv->vref);
546 err_switches_dis:
547 stm32_adc_core_switches_supply_dis(priv);
548 err_vdda_disable:
549 regulator_disable(priv->vdda);
550
551 return ret;
552 }
553
stm32_adc_core_hw_stop(struct device * dev)554 static void stm32_adc_core_hw_stop(struct device *dev)
555 {
556 struct stm32_adc_common *common = dev_get_drvdata(dev);
557 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
558
559 /* Backup CCR that may be lost (depends on power state to achieve) */
560 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
561 if (priv->aclk)
562 clk_disable_unprepare(priv->aclk);
563 if (priv->bclk)
564 clk_disable_unprepare(priv->bclk);
565 regulator_disable(priv->vref);
566 stm32_adc_core_switches_supply_dis(priv);
567 regulator_disable(priv->vdda);
568 }
569
stm32_adc_core_switches_probe(struct device * dev,struct stm32_adc_priv * priv)570 static int stm32_adc_core_switches_probe(struct device *dev,
571 struct stm32_adc_priv *priv)
572 {
573 struct device_node *np = dev->of_node;
574 int ret;
575
576 /* Analog switches supply can be controlled by syscfg (optional) */
577 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
578 if (IS_ERR(priv->syscfg)) {
579 ret = PTR_ERR(priv->syscfg);
580 if (ret != -ENODEV)
581 return dev_err_probe(dev, ret, "Can't probe syscfg\n");
582
583 priv->syscfg = NULL;
584 }
585
586 /* Booster can be used to supply analog switches (optional) */
587 if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
588 of_property_read_bool(np, "booster-supply")) {
589 priv->booster = devm_regulator_get_optional(dev, "booster");
590 if (IS_ERR(priv->booster)) {
591 ret = PTR_ERR(priv->booster);
592 if (ret != -ENODEV)
593 return dev_err_probe(dev, ret, "can't get booster\n");
594
595 priv->booster = NULL;
596 }
597 }
598
599 /* Vdd can be used to supply analog switches (optional) */
600 if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
601 of_property_read_bool(np, "vdd-supply")) {
602 priv->vdd = devm_regulator_get_optional(dev, "vdd");
603 if (IS_ERR(priv->vdd)) {
604 ret = PTR_ERR(priv->vdd);
605 if (ret != -ENODEV)
606 return dev_err_probe(dev, ret, "can't get vdd\n");
607
608 priv->vdd = NULL;
609 }
610 }
611
612 if (priv->vdd) {
613 ret = regulator_enable(priv->vdd);
614 if (ret < 0) {
615 dev_err(dev, "vdd enable failed %d\n", ret);
616 return ret;
617 }
618
619 ret = regulator_get_voltage(priv->vdd);
620 if (ret < 0) {
621 dev_err(dev, "vdd get voltage failed %d\n", ret);
622 regulator_disable(priv->vdd);
623 return ret;
624 }
625 priv->vdd_uv = ret;
626
627 regulator_disable(priv->vdd);
628 }
629
630 return 0;
631 }
632
stm32_adc_probe(struct platform_device * pdev)633 static int stm32_adc_probe(struct platform_device *pdev)
634 {
635 struct stm32_adc_priv *priv;
636 struct device *dev = &pdev->dev;
637 struct device_node *np = pdev->dev.of_node;
638 struct resource *res;
639 u32 max_rate;
640 int ret;
641
642 if (!pdev->dev.of_node)
643 return -ENODEV;
644
645 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
646 if (!priv)
647 return -ENOMEM;
648 platform_set_drvdata(pdev, &priv->common);
649
650 priv->cfg = (const struct stm32_adc_priv_cfg *)
651 of_match_device(dev->driver->of_match_table, dev)->data;
652
653 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
654 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
655 if (IS_ERR(priv->common.base))
656 return PTR_ERR(priv->common.base);
657 priv->common.phys_base = res->start;
658
659 priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
660 if (IS_ERR(priv->vdda))
661 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
662 "vdda get failed\n");
663
664 priv->vref = devm_regulator_get(&pdev->dev, "vref");
665 if (IS_ERR(priv->vref))
666 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
667 "vref get failed\n");
668
669 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
670 if (IS_ERR(priv->aclk))
671 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
672 "Can't get 'adc' clock\n");
673
674 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
675 if (IS_ERR(priv->bclk))
676 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
677 "Can't get 'bus' clock\n");
678
679 ret = stm32_adc_core_switches_probe(dev, priv);
680 if (ret)
681 return ret;
682
683 pm_runtime_get_noresume(dev);
684 pm_runtime_set_active(dev);
685 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
686 pm_runtime_use_autosuspend(dev);
687 pm_runtime_enable(dev);
688
689 ret = stm32_adc_core_hw_start(dev);
690 if (ret)
691 goto err_pm_stop;
692
693 ret = regulator_get_voltage(priv->vref);
694 if (ret < 0) {
695 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
696 goto err_hw_stop;
697 }
698 priv->common.vref_mv = ret / 1000;
699 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
700
701 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
702 &max_rate);
703 if (!ret)
704 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
705 else
706 priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
707
708 ret = priv->cfg->clk_sel(pdev, priv);
709 if (ret < 0)
710 goto err_hw_stop;
711
712 ret = stm32_adc_irq_probe(pdev, priv);
713 if (ret < 0)
714 goto err_hw_stop;
715
716 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
717 if (ret < 0) {
718 dev_err(&pdev->dev, "failed to populate DT children\n");
719 goto err_irq_remove;
720 }
721
722 pm_runtime_mark_last_busy(dev);
723 pm_runtime_put_autosuspend(dev);
724
725 return 0;
726
727 err_irq_remove:
728 stm32_adc_irq_remove(pdev, priv);
729 err_hw_stop:
730 stm32_adc_core_hw_stop(dev);
731 err_pm_stop:
732 pm_runtime_disable(dev);
733 pm_runtime_set_suspended(dev);
734 pm_runtime_put_noidle(dev);
735
736 return ret;
737 }
738
stm32_adc_remove(struct platform_device * pdev)739 static int stm32_adc_remove(struct platform_device *pdev)
740 {
741 struct stm32_adc_common *common = platform_get_drvdata(pdev);
742 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
743
744 pm_runtime_get_sync(&pdev->dev);
745 of_platform_depopulate(&pdev->dev);
746 stm32_adc_irq_remove(pdev, priv);
747 stm32_adc_core_hw_stop(&pdev->dev);
748 pm_runtime_disable(&pdev->dev);
749 pm_runtime_set_suspended(&pdev->dev);
750 pm_runtime_put_noidle(&pdev->dev);
751
752 return 0;
753 }
754
755 #if defined(CONFIG_PM)
stm32_adc_core_runtime_suspend(struct device * dev)756 static int stm32_adc_core_runtime_suspend(struct device *dev)
757 {
758 stm32_adc_core_hw_stop(dev);
759
760 return 0;
761 }
762
stm32_adc_core_runtime_resume(struct device * dev)763 static int stm32_adc_core_runtime_resume(struct device *dev)
764 {
765 return stm32_adc_core_hw_start(dev);
766 }
767
stm32_adc_core_runtime_idle(struct device * dev)768 static int stm32_adc_core_runtime_idle(struct device *dev)
769 {
770 pm_runtime_mark_last_busy(dev);
771
772 return 0;
773 }
774 #endif
775
776 static const struct dev_pm_ops stm32_adc_core_pm_ops = {
777 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
778 pm_runtime_force_resume)
779 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
780 stm32_adc_core_runtime_resume,
781 stm32_adc_core_runtime_idle)
782 };
783
784 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
785 .regs = &stm32f4_adc_common_regs,
786 .clk_sel = stm32f4_adc_clk_sel,
787 .max_clk_rate_hz = 36000000,
788 .num_irqs = 1,
789 .num_adcs = 3,
790 };
791
792 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
793 .regs = &stm32h7_adc_common_regs,
794 .clk_sel = stm32h7_adc_clk_sel,
795 .max_clk_rate_hz = 36000000,
796 .has_syscfg = HAS_VBOOSTER,
797 .num_irqs = 1,
798 .num_adcs = 2,
799 };
800
801 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
802 .regs = &stm32h7_adc_common_regs,
803 .clk_sel = stm32h7_adc_clk_sel,
804 .max_clk_rate_hz = 36000000,
805 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
806 .num_irqs = 2,
807 .num_adcs = 2,
808 };
809
810 static const struct of_device_id stm32_adc_of_match[] = {
811 {
812 .compatible = "st,stm32f4-adc-core",
813 .data = (void *)&stm32f4_adc_priv_cfg
814 }, {
815 .compatible = "st,stm32h7-adc-core",
816 .data = (void *)&stm32h7_adc_priv_cfg
817 }, {
818 .compatible = "st,stm32mp1-adc-core",
819 .data = (void *)&stm32mp1_adc_priv_cfg
820 }, {
821 },
822 };
823 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
824
825 static struct platform_driver stm32_adc_driver = {
826 .probe = stm32_adc_probe,
827 .remove = stm32_adc_remove,
828 .driver = {
829 .name = "stm32-adc-core",
830 .of_match_table = stm32_adc_of_match,
831 .pm = &stm32_adc_core_pm_ops,
832 },
833 };
834 module_platform_driver(stm32_adc_driver);
835
836 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
837 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
838 MODULE_LICENSE("GPL v2");
839 MODULE_ALIAS("platform:stm32-adc-core");
840