1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/hwspinlock.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/syscore_ops.h>
22
23 #include <dt-bindings/interrupt-controller/arm-gic.h>
24
25 #define IRQS_PER_BANK 32
26
27 #define HWSPNLCK_TIMEOUT 1000 /* usec */
28
29 struct stm32_exti_bank {
30 u32 imr_ofst;
31 u32 emr_ofst;
32 u32 rtsr_ofst;
33 u32 ftsr_ofst;
34 u32 swier_ofst;
35 u32 rpr_ofst;
36 u32 fpr_ofst;
37 };
38
39 #define UNDEF_REG ~0
40
41 struct stm32_desc_irq {
42 u32 exti;
43 u32 irq_parent;
44 struct irq_chip *chip;
45 };
46
47 struct stm32_exti_drv_data {
48 const struct stm32_exti_bank **exti_banks;
49 const struct stm32_desc_irq *desc_irqs;
50 u32 bank_nr;
51 u32 irq_nr;
52 };
53
54 struct stm32_exti_chip_data {
55 struct stm32_exti_host_data *host_data;
56 const struct stm32_exti_bank *reg_bank;
57 struct raw_spinlock rlock;
58 u32 wake_active;
59 u32 mask_cache;
60 u32 rtsr_cache;
61 u32 ftsr_cache;
62 };
63
64 struct stm32_exti_host_data {
65 void __iomem *base;
66 struct stm32_exti_chip_data *chips_data;
67 const struct stm32_exti_drv_data *drv_data;
68 struct hwspinlock *hwlock;
69 };
70
71 static struct stm32_exti_host_data *stm32_host_data;
72
73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
74 .imr_ofst = 0x00,
75 .emr_ofst = 0x04,
76 .rtsr_ofst = 0x08,
77 .ftsr_ofst = 0x0C,
78 .swier_ofst = 0x10,
79 .rpr_ofst = 0x14,
80 .fpr_ofst = UNDEF_REG,
81 };
82
83 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
84 &stm32f4xx_exti_b1,
85 };
86
87 static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
88 .exti_banks = stm32f4xx_exti_banks,
89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
90 };
91
92 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
93 .imr_ofst = 0x80,
94 .emr_ofst = 0x84,
95 .rtsr_ofst = 0x00,
96 .ftsr_ofst = 0x04,
97 .swier_ofst = 0x08,
98 .rpr_ofst = 0x88,
99 .fpr_ofst = UNDEF_REG,
100 };
101
102 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
103 .imr_ofst = 0x90,
104 .emr_ofst = 0x94,
105 .rtsr_ofst = 0x20,
106 .ftsr_ofst = 0x24,
107 .swier_ofst = 0x28,
108 .rpr_ofst = 0x98,
109 .fpr_ofst = UNDEF_REG,
110 };
111
112 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
113 .imr_ofst = 0xA0,
114 .emr_ofst = 0xA4,
115 .rtsr_ofst = 0x40,
116 .ftsr_ofst = 0x44,
117 .swier_ofst = 0x48,
118 .rpr_ofst = 0xA8,
119 .fpr_ofst = UNDEF_REG,
120 };
121
122 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
123 &stm32h7xx_exti_b1,
124 &stm32h7xx_exti_b2,
125 &stm32h7xx_exti_b3,
126 };
127
128 static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
129 .exti_banks = stm32h7xx_exti_banks,
130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
131 };
132
133 static const struct stm32_exti_bank stm32mp1_exti_b1 = {
134 .imr_ofst = 0x80,
135 .emr_ofst = 0x84,
136 .rtsr_ofst = 0x00,
137 .ftsr_ofst = 0x04,
138 .swier_ofst = 0x08,
139 .rpr_ofst = 0x0C,
140 .fpr_ofst = 0x10,
141 };
142
143 static const struct stm32_exti_bank stm32mp1_exti_b2 = {
144 .imr_ofst = 0x90,
145 .emr_ofst = 0x94,
146 .rtsr_ofst = 0x20,
147 .ftsr_ofst = 0x24,
148 .swier_ofst = 0x28,
149 .rpr_ofst = 0x2C,
150 .fpr_ofst = 0x30,
151 };
152
153 static const struct stm32_exti_bank stm32mp1_exti_b3 = {
154 .imr_ofst = 0xA0,
155 .emr_ofst = 0xA4,
156 .rtsr_ofst = 0x40,
157 .ftsr_ofst = 0x44,
158 .swier_ofst = 0x48,
159 .rpr_ofst = 0x4C,
160 .fpr_ofst = 0x50,
161 };
162
163 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
164 &stm32mp1_exti_b1,
165 &stm32mp1_exti_b2,
166 &stm32mp1_exti_b3,
167 };
168
169 static struct irq_chip stm32_exti_h_chip;
170 static struct irq_chip stm32_exti_h_chip_direct;
171
172 static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
173 { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
174 { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
175 { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
176 { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
177 { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
178 { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
179 { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
180 { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
181 { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
182 { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
183 { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
184 { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
185 { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
186 { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
187 { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
188 { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
189 { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
190 { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
191 { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
192 { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
193 { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
194 { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
195 { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
196 { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
197 { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
198 { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
199 { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
200 { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
201 { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
202 { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
203 { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
204 { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
205 { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
206 { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
207 { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
208 };
209
210 static const struct stm32_exti_drv_data stm32mp1_drv_data = {
211 .exti_banks = stm32mp1_exti_banks,
212 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
213 .desc_irqs = stm32mp1_desc_irq,
214 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
215 };
216
217 static const struct
stm32_exti_get_desc(const struct stm32_exti_drv_data * drv_data,irq_hw_number_t hwirq)218 stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
219 irq_hw_number_t hwirq)
220 {
221 const struct stm32_desc_irq *desc = NULL;
222 int i;
223
224 if (!drv_data->desc_irqs)
225 return NULL;
226
227 for (i = 0; i < drv_data->irq_nr; i++) {
228 desc = &drv_data->desc_irqs[i];
229 if (desc->exti == hwirq)
230 break;
231 }
232
233 return desc;
234 }
235
stm32_exti_pending(struct irq_chip_generic * gc)236 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
237 {
238 struct stm32_exti_chip_data *chip_data = gc->private;
239 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
240 unsigned long pending;
241
242 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
243 if (stm32_bank->fpr_ofst != UNDEF_REG)
244 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
245
246 return pending;
247 }
248
stm32_irq_handler(struct irq_desc * desc)249 static void stm32_irq_handler(struct irq_desc *desc)
250 {
251 struct irq_domain *domain = irq_desc_get_handler_data(desc);
252 struct irq_chip *chip = irq_desc_get_chip(desc);
253 unsigned int virq, nbanks = domain->gc->num_chips;
254 struct irq_chip_generic *gc;
255 unsigned long pending;
256 int n, i, irq_base = 0;
257
258 chained_irq_enter(chip, desc);
259
260 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
261 gc = irq_get_domain_generic_chip(domain, irq_base);
262
263 while ((pending = stm32_exti_pending(gc))) {
264 for_each_set_bit(n, &pending, IRQS_PER_BANK) {
265 virq = irq_find_mapping(domain, irq_base + n);
266 generic_handle_irq(virq);
267 }
268 }
269 }
270
271 chained_irq_exit(chip, desc);
272 }
273
stm32_exti_set_type(struct irq_data * d,unsigned int type,u32 * rtsr,u32 * ftsr)274 static int stm32_exti_set_type(struct irq_data *d,
275 unsigned int type, u32 *rtsr, u32 *ftsr)
276 {
277 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
278
279 switch (type) {
280 case IRQ_TYPE_EDGE_RISING:
281 *rtsr |= mask;
282 *ftsr &= ~mask;
283 break;
284 case IRQ_TYPE_EDGE_FALLING:
285 *rtsr &= ~mask;
286 *ftsr |= mask;
287 break;
288 case IRQ_TYPE_EDGE_BOTH:
289 *rtsr |= mask;
290 *ftsr |= mask;
291 break;
292 default:
293 return -EINVAL;
294 }
295
296 return 0;
297 }
298
stm32_irq_set_type(struct irq_data * d,unsigned int type)299 static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
300 {
301 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
302 struct stm32_exti_chip_data *chip_data = gc->private;
303 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
304 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
305 u32 rtsr, ftsr;
306 int err;
307
308 irq_gc_lock(gc);
309
310 if (hwlock) {
311 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
312 if (err) {
313 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
314 goto unlock;
315 }
316 }
317
318 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
319 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
320
321 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
322 if (err)
323 goto unspinlock;
324
325 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
326 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
327
328 unspinlock:
329 if (hwlock)
330 hwspin_unlock_in_atomic(hwlock);
331 unlock:
332 irq_gc_unlock(gc);
333
334 return err;
335 }
336
stm32_chip_suspend(struct stm32_exti_chip_data * chip_data,u32 wake_active)337 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
338 u32 wake_active)
339 {
340 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
341 void __iomem *base = chip_data->host_data->base;
342
343 /* save rtsr, ftsr registers */
344 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
345 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
346
347 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
348 }
349
stm32_chip_resume(struct stm32_exti_chip_data * chip_data,u32 mask_cache)350 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
351 u32 mask_cache)
352 {
353 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
354 void __iomem *base = chip_data->host_data->base;
355
356 /* restore rtsr, ftsr, registers */
357 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
358 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
359
360 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
361 }
362
stm32_irq_suspend(struct irq_chip_generic * gc)363 static void stm32_irq_suspend(struct irq_chip_generic *gc)
364 {
365 struct stm32_exti_chip_data *chip_data = gc->private;
366
367 irq_gc_lock(gc);
368 stm32_chip_suspend(chip_data, gc->wake_active);
369 irq_gc_unlock(gc);
370 }
371
stm32_irq_resume(struct irq_chip_generic * gc)372 static void stm32_irq_resume(struct irq_chip_generic *gc)
373 {
374 struct stm32_exti_chip_data *chip_data = gc->private;
375
376 irq_gc_lock(gc);
377 stm32_chip_resume(chip_data, gc->mask_cache);
378 irq_gc_unlock(gc);
379 }
380
stm32_exti_alloc(struct irq_domain * d,unsigned int virq,unsigned int nr_irqs,void * data)381 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
382 unsigned int nr_irqs, void *data)
383 {
384 struct irq_fwspec *fwspec = data;
385 irq_hw_number_t hwirq;
386
387 hwirq = fwspec->param[0];
388
389 irq_map_generic_chip(d, virq, hwirq);
390
391 return 0;
392 }
393
stm32_exti_free(struct irq_domain * d,unsigned int virq,unsigned int nr_irqs)394 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
395 unsigned int nr_irqs)
396 {
397 struct irq_data *data = irq_domain_get_irq_data(d, virq);
398
399 irq_domain_reset_irq_data(data);
400 }
401
402 static const struct irq_domain_ops irq_exti_domain_ops = {
403 .map = irq_map_generic_chip,
404 .alloc = stm32_exti_alloc,
405 .free = stm32_exti_free,
406 .xlate = irq_domain_xlate_twocell,
407 };
408
stm32_irq_ack(struct irq_data * d)409 static void stm32_irq_ack(struct irq_data *d)
410 {
411 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
412 struct stm32_exti_chip_data *chip_data = gc->private;
413 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
414
415 irq_gc_lock(gc);
416
417 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
418 if (stm32_bank->fpr_ofst != UNDEF_REG)
419 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
420
421 irq_gc_unlock(gc);
422 }
423
424 /* directly set the target bit without reading first. */
stm32_exti_write_bit(struct irq_data * d,u32 reg)425 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
426 {
427 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
428 void __iomem *base = chip_data->host_data->base;
429 u32 val = BIT(d->hwirq % IRQS_PER_BANK);
430
431 writel_relaxed(val, base + reg);
432 }
433
stm32_exti_set_bit(struct irq_data * d,u32 reg)434 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
435 {
436 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
437 void __iomem *base = chip_data->host_data->base;
438 u32 val;
439
440 val = readl_relaxed(base + reg);
441 val |= BIT(d->hwirq % IRQS_PER_BANK);
442 writel_relaxed(val, base + reg);
443
444 return val;
445 }
446
stm32_exti_clr_bit(struct irq_data * d,u32 reg)447 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
448 {
449 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
450 void __iomem *base = chip_data->host_data->base;
451 u32 val;
452
453 val = readl_relaxed(base + reg);
454 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
455 writel_relaxed(val, base + reg);
456
457 return val;
458 }
459
stm32_exti_h_eoi(struct irq_data * d)460 static void stm32_exti_h_eoi(struct irq_data *d)
461 {
462 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
463 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
464
465 raw_spin_lock(&chip_data->rlock);
466
467 stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
468 if (stm32_bank->fpr_ofst != UNDEF_REG)
469 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
470
471 raw_spin_unlock(&chip_data->rlock);
472
473 if (d->parent_data->chip)
474 irq_chip_eoi_parent(d);
475 }
476
stm32_exti_h_mask(struct irq_data * d)477 static void stm32_exti_h_mask(struct irq_data *d)
478 {
479 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
480 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
481
482 raw_spin_lock(&chip_data->rlock);
483 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
484 raw_spin_unlock(&chip_data->rlock);
485
486 if (d->parent_data->chip)
487 irq_chip_mask_parent(d);
488 }
489
stm32_exti_h_unmask(struct irq_data * d)490 static void stm32_exti_h_unmask(struct irq_data *d)
491 {
492 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
493 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
494
495 raw_spin_lock(&chip_data->rlock);
496 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
497 raw_spin_unlock(&chip_data->rlock);
498
499 if (d->parent_data->chip)
500 irq_chip_unmask_parent(d);
501 }
502
stm32_exti_h_set_type(struct irq_data * d,unsigned int type)503 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
504 {
505 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
506 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
507 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
508 void __iomem *base = chip_data->host_data->base;
509 u32 rtsr, ftsr;
510 int err;
511
512 raw_spin_lock(&chip_data->rlock);
513
514 if (hwlock) {
515 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
516 if (err) {
517 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
518 goto unlock;
519 }
520 }
521
522 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
523 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
524
525 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
526 if (err)
527 goto unspinlock;
528
529 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
530 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
531
532 unspinlock:
533 if (hwlock)
534 hwspin_unlock_in_atomic(hwlock);
535 unlock:
536 raw_spin_unlock(&chip_data->rlock);
537
538 return err;
539 }
540
stm32_exti_h_set_wake(struct irq_data * d,unsigned int on)541 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
542 {
543 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
544 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
545
546 raw_spin_lock(&chip_data->rlock);
547
548 if (on)
549 chip_data->wake_active |= mask;
550 else
551 chip_data->wake_active &= ~mask;
552
553 raw_spin_unlock(&chip_data->rlock);
554
555 return 0;
556 }
557
stm32_exti_h_set_affinity(struct irq_data * d,const struct cpumask * dest,bool force)558 static int stm32_exti_h_set_affinity(struct irq_data *d,
559 const struct cpumask *dest, bool force)
560 {
561 if (d->parent_data->chip)
562 return irq_chip_set_affinity_parent(d, dest, force);
563
564 return -EINVAL;
565 }
566
stm32_exti_h_suspend(void)567 static int __maybe_unused stm32_exti_h_suspend(void)
568 {
569 struct stm32_exti_chip_data *chip_data;
570 int i;
571
572 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
573 chip_data = &stm32_host_data->chips_data[i];
574 raw_spin_lock(&chip_data->rlock);
575 stm32_chip_suspend(chip_data, chip_data->wake_active);
576 raw_spin_unlock(&chip_data->rlock);
577 }
578
579 return 0;
580 }
581
stm32_exti_h_resume(void)582 static void __maybe_unused stm32_exti_h_resume(void)
583 {
584 struct stm32_exti_chip_data *chip_data;
585 int i;
586
587 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
588 chip_data = &stm32_host_data->chips_data[i];
589 raw_spin_lock(&chip_data->rlock);
590 stm32_chip_resume(chip_data, chip_data->mask_cache);
591 raw_spin_unlock(&chip_data->rlock);
592 }
593 }
594
595 static struct syscore_ops stm32_exti_h_syscore_ops = {
596 #ifdef CONFIG_PM_SLEEP
597 .suspend = stm32_exti_h_suspend,
598 .resume = stm32_exti_h_resume,
599 #endif
600 };
601
stm32_exti_h_syscore_init(struct stm32_exti_host_data * host_data)602 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
603 {
604 stm32_host_data = host_data;
605 register_syscore_ops(&stm32_exti_h_syscore_ops);
606 }
607
stm32_exti_h_syscore_deinit(void)608 static void stm32_exti_h_syscore_deinit(void)
609 {
610 unregister_syscore_ops(&stm32_exti_h_syscore_ops);
611 }
612
stm32_exti_h_retrigger(struct irq_data * d)613 static int stm32_exti_h_retrigger(struct irq_data *d)
614 {
615 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
616 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
617 void __iomem *base = chip_data->host_data->base;
618 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
619
620 writel_relaxed(mask, base + stm32_bank->swier_ofst);
621
622 return 0;
623 }
624
625 static struct irq_chip stm32_exti_h_chip = {
626 .name = "stm32-exti-h",
627 .irq_eoi = stm32_exti_h_eoi,
628 .irq_mask = stm32_exti_h_mask,
629 .irq_unmask = stm32_exti_h_unmask,
630 .irq_retrigger = stm32_exti_h_retrigger,
631 .irq_set_type = stm32_exti_h_set_type,
632 .irq_set_wake = stm32_exti_h_set_wake,
633 .flags = IRQCHIP_MASK_ON_SUSPEND,
634 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
635 };
636
637 static struct irq_chip stm32_exti_h_chip_direct = {
638 .name = "stm32-exti-h-direct",
639 .irq_eoi = irq_chip_eoi_parent,
640 .irq_ack = irq_chip_ack_parent,
641 .irq_mask = irq_chip_mask_parent,
642 .irq_unmask = irq_chip_unmask_parent,
643 .irq_retrigger = irq_chip_retrigger_hierarchy,
644 .irq_set_type = irq_chip_set_type_parent,
645 .irq_set_wake = stm32_exti_h_set_wake,
646 .flags = IRQCHIP_MASK_ON_SUSPEND,
647 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
648 };
649
stm32_exti_h_domain_alloc(struct irq_domain * dm,unsigned int virq,unsigned int nr_irqs,void * data)650 static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
651 unsigned int virq,
652 unsigned int nr_irqs, void *data)
653 {
654 struct stm32_exti_host_data *host_data = dm->host_data;
655 struct stm32_exti_chip_data *chip_data;
656 const struct stm32_desc_irq *desc;
657 struct irq_fwspec *fwspec = data;
658 struct irq_fwspec p_fwspec;
659 irq_hw_number_t hwirq;
660 int bank;
661
662 hwirq = fwspec->param[0];
663 bank = hwirq / IRQS_PER_BANK;
664 chip_data = &host_data->chips_data[bank];
665
666
667 desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
668 if (!desc)
669 return -EINVAL;
670
671 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
672 chip_data);
673 if (desc->irq_parent) {
674 p_fwspec.fwnode = dm->parent->fwnode;
675 p_fwspec.param_count = 3;
676 p_fwspec.param[0] = GIC_SPI;
677 p_fwspec.param[1] = desc->irq_parent;
678 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
679
680 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
681 }
682
683 return 0;
684 }
685
686 static struct
stm32_exti_host_init(const struct stm32_exti_drv_data * dd,struct device_node * node)687 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
688 struct device_node *node)
689 {
690 struct stm32_exti_host_data *host_data;
691
692 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
693 if (!host_data)
694 return NULL;
695
696 host_data->drv_data = dd;
697 host_data->chips_data = kcalloc(dd->bank_nr,
698 sizeof(struct stm32_exti_chip_data),
699 GFP_KERNEL);
700 if (!host_data->chips_data)
701 goto free_host_data;
702
703 host_data->base = of_iomap(node, 0);
704 if (!host_data->base) {
705 pr_err("%pOF: Unable to map registers\n", node);
706 goto free_chips_data;
707 }
708
709 stm32_host_data = host_data;
710
711 return host_data;
712
713 free_chips_data:
714 kfree(host_data->chips_data);
715 free_host_data:
716 kfree(host_data);
717
718 return NULL;
719 }
720
721 static struct
stm32_exti_chip_init(struct stm32_exti_host_data * h_data,u32 bank_idx,struct device_node * node)722 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
723 u32 bank_idx,
724 struct device_node *node)
725 {
726 const struct stm32_exti_bank *stm32_bank;
727 struct stm32_exti_chip_data *chip_data;
728 void __iomem *base = h_data->base;
729
730 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
731 chip_data = &h_data->chips_data[bank_idx];
732 chip_data->host_data = h_data;
733 chip_data->reg_bank = stm32_bank;
734
735 raw_spin_lock_init(&chip_data->rlock);
736
737 /*
738 * This IP has no reset, so after hot reboot we should
739 * clear registers to avoid residue
740 */
741 writel_relaxed(0, base + stm32_bank->imr_ofst);
742 writel_relaxed(0, base + stm32_bank->emr_ofst);
743
744 pr_info("%pOF: bank%d\n", node, bank_idx);
745
746 return chip_data;
747 }
748
stm32_exti_init(const struct stm32_exti_drv_data * drv_data,struct device_node * node)749 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
750 struct device_node *node)
751 {
752 struct stm32_exti_host_data *host_data;
753 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
754 int nr_irqs, ret, i;
755 struct irq_chip_generic *gc;
756 struct irq_domain *domain;
757
758 host_data = stm32_exti_host_init(drv_data, node);
759 if (!host_data)
760 return -ENOMEM;
761
762 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
763 &irq_exti_domain_ops, NULL);
764 if (!domain) {
765 pr_err("%pOFn: Could not register interrupt domain.\n",
766 node);
767 ret = -ENOMEM;
768 goto out_unmap;
769 }
770
771 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
772 handle_edge_irq, clr, 0, 0);
773 if (ret) {
774 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
775 node);
776 goto out_free_domain;
777 }
778
779 for (i = 0; i < drv_data->bank_nr; i++) {
780 const struct stm32_exti_bank *stm32_bank;
781 struct stm32_exti_chip_data *chip_data;
782
783 stm32_bank = drv_data->exti_banks[i];
784 chip_data = stm32_exti_chip_init(host_data, i, node);
785
786 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
787
788 gc->reg_base = host_data->base;
789 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
790 gc->chip_types->chip.irq_ack = stm32_irq_ack;
791 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
792 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
793 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
794 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
795 gc->suspend = stm32_irq_suspend;
796 gc->resume = stm32_irq_resume;
797 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
798
799 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
800 gc->private = (void *)chip_data;
801 }
802
803 nr_irqs = of_irq_count(node);
804 for (i = 0; i < nr_irqs; i++) {
805 unsigned int irq = irq_of_parse_and_map(node, i);
806
807 irq_set_handler_data(irq, domain);
808 irq_set_chained_handler(irq, stm32_irq_handler);
809 }
810
811 return 0;
812
813 out_free_domain:
814 irq_domain_remove(domain);
815 out_unmap:
816 iounmap(host_data->base);
817 kfree(host_data->chips_data);
818 kfree(host_data);
819 return ret;
820 }
821
822 static const struct irq_domain_ops stm32_exti_h_domain_ops = {
823 .alloc = stm32_exti_h_domain_alloc,
824 .free = irq_domain_free_irqs_common,
825 .xlate = irq_domain_xlate_twocell,
826 };
827
stm32_exti_remove_irq(void * data)828 static void stm32_exti_remove_irq(void *data)
829 {
830 struct irq_domain *domain = data;
831
832 irq_domain_remove(domain);
833 }
834
stm32_exti_remove(struct platform_device * pdev)835 static int stm32_exti_remove(struct platform_device *pdev)
836 {
837 stm32_exti_h_syscore_deinit();
838 return 0;
839 }
840
stm32_exti_probe(struct platform_device * pdev)841 static int stm32_exti_probe(struct platform_device *pdev)
842 {
843 int ret, i;
844 struct device *dev = &pdev->dev;
845 struct device_node *np = dev->of_node;
846 struct irq_domain *parent_domain, *domain;
847 struct stm32_exti_host_data *host_data;
848 const struct stm32_exti_drv_data *drv_data;
849 struct resource *res;
850
851 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
852 if (!host_data)
853 return -ENOMEM;
854
855 /* check for optional hwspinlock which may be not available yet */
856 ret = of_hwspin_lock_get_id(np, 0);
857 if (ret == -EPROBE_DEFER)
858 /* hwspinlock framework not yet ready */
859 return ret;
860
861 if (ret >= 0) {
862 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
863 if (!host_data->hwlock) {
864 dev_err(dev, "Failed to request hwspinlock\n");
865 return -EINVAL;
866 }
867 } else if (ret != -ENOENT) {
868 /* note: ENOENT is a valid case (means 'no hwspinlock') */
869 dev_err(dev, "Failed to get hwspinlock\n");
870 return ret;
871 }
872
873 /* initialize host_data */
874 drv_data = of_device_get_match_data(dev);
875 if (!drv_data) {
876 dev_err(dev, "no of match data\n");
877 return -ENODEV;
878 }
879 host_data->drv_data = drv_data;
880
881 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
882 sizeof(*host_data->chips_data),
883 GFP_KERNEL);
884 if (!host_data->chips_data)
885 return -ENOMEM;
886
887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
888 host_data->base = devm_ioremap_resource(dev, res);
889 if (IS_ERR(host_data->base)) {
890 dev_err(dev, "Unable to map registers\n");
891 return PTR_ERR(host_data->base);
892 }
893
894 for (i = 0; i < drv_data->bank_nr; i++)
895 stm32_exti_chip_init(host_data, i, np);
896
897 parent_domain = irq_find_host(of_irq_find_parent(np));
898 if (!parent_domain) {
899 dev_err(dev, "GIC interrupt-parent not found\n");
900 return -EINVAL;
901 }
902
903 domain = irq_domain_add_hierarchy(parent_domain, 0,
904 drv_data->bank_nr * IRQS_PER_BANK,
905 np, &stm32_exti_h_domain_ops,
906 host_data);
907
908 if (!domain) {
909 dev_err(dev, "Could not register exti domain\n");
910 return -ENOMEM;
911 }
912
913 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
914 if (ret)
915 return ret;
916
917 stm32_exti_h_syscore_init(host_data);
918
919 return 0;
920 }
921
922 /* platform driver only for MP1 */
923 static const struct of_device_id stm32_exti_ids[] = {
924 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
925 {},
926 };
927 MODULE_DEVICE_TABLE(of, stm32_exti_ids);
928
929 static struct platform_driver stm32_exti_driver = {
930 .probe = stm32_exti_probe,
931 .remove = stm32_exti_remove,
932 .driver = {
933 .name = "stm32_exti",
934 .of_match_table = stm32_exti_ids,
935 },
936 };
937
stm32_exti_arch_init(void)938 static int __init stm32_exti_arch_init(void)
939 {
940 return platform_driver_register(&stm32_exti_driver);
941 }
942
stm32_exti_arch_exit(void)943 static void __exit stm32_exti_arch_exit(void)
944 {
945 return platform_driver_unregister(&stm32_exti_driver);
946 }
947
948 arch_initcall(stm32_exti_arch_init);
949 module_exit(stm32_exti_arch_exit);
950
951 /* no platform driver for F4 and H7 */
stm32f4_exti_of_init(struct device_node * np,struct device_node * parent)952 static int __init stm32f4_exti_of_init(struct device_node *np,
953 struct device_node *parent)
954 {
955 return stm32_exti_init(&stm32f4xx_drv_data, np);
956 }
957
958 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
959
stm32h7_exti_of_init(struct device_node * np,struct device_node * parent)960 static int __init stm32h7_exti_of_init(struct device_node *np,
961 struct device_node *parent)
962 {
963 return stm32_exti_init(&stm32h7xx_drv_data, np);
964 }
965
966 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
967