1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
3 */
4
5 #include <linux/clk-provider.h>
6 #include <linux/pci.h>
7 #include <linux/dmi.h>
8 #include "dwmac-intel.h"
9 #include "dwmac4.h"
10 #include "stmmac.h"
11
12 struct intel_priv_data {
13 int mdio_adhoc_addr; /* mdio address for serdes & etc */
14 };
15
16 /* This struct is used to associate PCI Function of MAC controller on a board,
17 * discovered via DMI, with the address of PHY connected to the MAC. The
18 * negative value of the address means that MAC controller is not connected
19 * with PHY.
20 */
21 struct stmmac_pci_func_data {
22 unsigned int func;
23 int phy_addr;
24 };
25
26 struct stmmac_pci_dmi_data {
27 const struct stmmac_pci_func_data *func;
28 size_t nfuncs;
29 };
30
31 struct stmmac_pci_info {
32 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
33 };
34
stmmac_pci_find_phy_addr(struct pci_dev * pdev,const struct dmi_system_id * dmi_list)35 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
36 const struct dmi_system_id *dmi_list)
37 {
38 const struct stmmac_pci_func_data *func_data;
39 const struct stmmac_pci_dmi_data *dmi_data;
40 const struct dmi_system_id *dmi_id;
41 int func = PCI_FUNC(pdev->devfn);
42 size_t n;
43
44 dmi_id = dmi_first_match(dmi_list);
45 if (!dmi_id)
46 return -ENODEV;
47
48 dmi_data = dmi_id->driver_data;
49 func_data = dmi_data->func;
50
51 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
52 if (func_data->func == func)
53 return func_data->phy_addr;
54
55 return -ENODEV;
56 }
57
serdes_status_poll(struct stmmac_priv * priv,int phyaddr,int phyreg,u32 mask,u32 val)58 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
59 int phyreg, u32 mask, u32 val)
60 {
61 unsigned int retries = 10;
62 int val_rd;
63
64 do {
65 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
66 if ((val_rd & mask) == (val & mask))
67 return 0;
68 udelay(POLL_DELAY_US);
69 } while (--retries);
70
71 return -ETIMEDOUT;
72 }
73
intel_serdes_powerup(struct net_device * ndev,void * priv_data)74 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
75 {
76 struct intel_priv_data *intel_priv = priv_data;
77 struct stmmac_priv *priv = netdev_priv(ndev);
78 int serdes_phy_addr = 0;
79 u32 data = 0;
80
81 if (!intel_priv->mdio_adhoc_addr)
82 return 0;
83
84 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
85
86 /* assert clk_req */
87 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
88 data |= SERDES_PLL_CLK;
89 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
90
91 /* check for clk_ack assertion */
92 data = serdes_status_poll(priv, serdes_phy_addr,
93 SERDES_GSR0,
94 SERDES_PLL_CLK,
95 SERDES_PLL_CLK);
96
97 if (data) {
98 dev_err(priv->device, "Serdes PLL clk request timeout\n");
99 return data;
100 }
101
102 /* assert lane reset */
103 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
104 data |= SERDES_RST;
105 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
106
107 /* check for assert lane reset reflection */
108 data = serdes_status_poll(priv, serdes_phy_addr,
109 SERDES_GSR0,
110 SERDES_RST,
111 SERDES_RST);
112
113 if (data) {
114 dev_err(priv->device, "Serdes assert lane reset timeout\n");
115 return data;
116 }
117
118 /* move power state to P0 */
119 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
120
121 data &= ~SERDES_PWR_ST_MASK;
122 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
123
124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
125
126 /* Check for P0 state */
127 data = serdes_status_poll(priv, serdes_phy_addr,
128 SERDES_GSR0,
129 SERDES_PWR_ST_MASK,
130 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
131
132 if (data) {
133 dev_err(priv->device, "Serdes power state P0 timeout.\n");
134 return data;
135 }
136
137 return 0;
138 }
139
intel_serdes_powerdown(struct net_device * ndev,void * intel_data)140 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
141 {
142 struct intel_priv_data *intel_priv = intel_data;
143 struct stmmac_priv *priv = netdev_priv(ndev);
144 int serdes_phy_addr = 0;
145 u32 data = 0;
146
147 if (!intel_priv->mdio_adhoc_addr)
148 return;
149
150 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
151
152 /* move power state to P3 */
153 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
154
155 data &= ~SERDES_PWR_ST_MASK;
156 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
157
158 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
159
160 /* Check for P3 state */
161 data = serdes_status_poll(priv, serdes_phy_addr,
162 SERDES_GSR0,
163 SERDES_PWR_ST_MASK,
164 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
165
166 if (data) {
167 dev_err(priv->device, "Serdes power state P3 timeout\n");
168 return;
169 }
170
171 /* de-assert clk_req */
172 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
173 data &= ~SERDES_PLL_CLK;
174 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
175
176 /* check for clk_ack de-assert */
177 data = serdes_status_poll(priv, serdes_phy_addr,
178 SERDES_GSR0,
179 SERDES_PLL_CLK,
180 (u32)~SERDES_PLL_CLK);
181
182 if (data) {
183 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
184 return;
185 }
186
187 /* de-assert lane reset */
188 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
189 data &= ~SERDES_RST;
190 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
191
192 /* check for de-assert lane reset reflection */
193 data = serdes_status_poll(priv, serdes_phy_addr,
194 SERDES_GSR0,
195 SERDES_RST,
196 (u32)~SERDES_RST);
197
198 if (data) {
199 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
200 return;
201 }
202 }
203
common_default_data(struct plat_stmmacenet_data * plat)204 static void common_default_data(struct plat_stmmacenet_data *plat)
205 {
206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
207 plat->has_gmac = 1;
208 plat->force_sf_dma_mode = 1;
209
210 plat->mdio_bus_data->needs_reset = true;
211
212 /* Set default value for multicast hash bins */
213 plat->multicast_filter_bins = HASH_TABLE_SIZE;
214
215 /* Set default value for unicast filter entries */
216 plat->unicast_filter_entries = 1;
217
218 /* Set the maxmtu to a default of JUMBO_LEN */
219 plat->maxmtu = JUMBO_LEN;
220
221 /* Set default number of RX and TX queues to use */
222 plat->tx_queues_to_use = 1;
223 plat->rx_queues_to_use = 1;
224
225 /* Disable Priority config by default */
226 plat->tx_queues_cfg[0].use_prio = false;
227 plat->rx_queues_cfg[0].use_prio = false;
228
229 /* Disable RX queues routing by default */
230 plat->rx_queues_cfg[0].pkt_route = 0x0;
231 }
232
intel_mgbe_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)233 static int intel_mgbe_common_data(struct pci_dev *pdev,
234 struct plat_stmmacenet_data *plat)
235 {
236 char clk_name[20];
237 int ret;
238 int i;
239
240 plat->phy_addr = -1;
241 plat->clk_csr = 5;
242 plat->has_gmac = 0;
243 plat->has_gmac4 = 1;
244 plat->force_sf_dma_mode = 0;
245 plat->tso_en = 1;
246 plat->sph_disable = 1;
247
248 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
249
250 for (i = 0; i < plat->rx_queues_to_use; i++) {
251 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
252 plat->rx_queues_cfg[i].chan = i;
253
254 /* Disable Priority config by default */
255 plat->rx_queues_cfg[i].use_prio = false;
256
257 /* Disable RX queues routing by default */
258 plat->rx_queues_cfg[i].pkt_route = 0x0;
259 }
260
261 for (i = 0; i < plat->tx_queues_to_use; i++) {
262 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
263
264 /* Disable Priority config by default */
265 plat->tx_queues_cfg[i].use_prio = false;
266 }
267
268 /* FIFO size is 4096 bytes for 1 tx/rx queue */
269 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
270 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
271
272 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
273 plat->tx_queues_cfg[0].weight = 0x09;
274 plat->tx_queues_cfg[1].weight = 0x0A;
275 plat->tx_queues_cfg[2].weight = 0x0B;
276 plat->tx_queues_cfg[3].weight = 0x0C;
277 plat->tx_queues_cfg[4].weight = 0x0D;
278 plat->tx_queues_cfg[5].weight = 0x0E;
279 plat->tx_queues_cfg[6].weight = 0x0F;
280 plat->tx_queues_cfg[7].weight = 0x10;
281
282 plat->dma_cfg->pbl = 32;
283 plat->dma_cfg->pblx8 = true;
284 plat->dma_cfg->fixed_burst = 0;
285 plat->dma_cfg->mixed_burst = 0;
286 plat->dma_cfg->aal = 0;
287
288 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
289 GFP_KERNEL);
290 if (!plat->axi)
291 return -ENOMEM;
292
293 plat->axi->axi_lpi_en = 0;
294 plat->axi->axi_xit_frm = 0;
295 plat->axi->axi_wr_osr_lmt = 1;
296 plat->axi->axi_rd_osr_lmt = 1;
297 plat->axi->axi_blen[0] = 4;
298 plat->axi->axi_blen[1] = 8;
299 plat->axi->axi_blen[2] = 16;
300
301 plat->ptp_max_adj = plat->clk_ptp_rate;
302 plat->eee_usecs_rate = plat->clk_ptp_rate;
303
304 /* Set system clock */
305 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
306
307 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
308 clk_name, NULL, 0,
309 plat->clk_ptp_rate);
310
311 if (IS_ERR(plat->stmmac_clk)) {
312 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
313 plat->stmmac_clk = NULL;
314 }
315
316 ret = clk_prepare_enable(plat->stmmac_clk);
317 if (ret) {
318 clk_unregister_fixed_rate(plat->stmmac_clk);
319 return ret;
320 }
321
322 /* Set default value for multicast hash bins */
323 plat->multicast_filter_bins = HASH_TABLE_SIZE;
324
325 /* Set default value for unicast filter entries */
326 plat->unicast_filter_entries = 1;
327
328 /* Set the maxmtu to a default of JUMBO_LEN */
329 plat->maxmtu = JUMBO_LEN;
330
331 plat->vlan_fail_q_en = true;
332
333 /* Use the last Rx queue */
334 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
335
336 return 0;
337 }
338
ehl_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)339 static int ehl_common_data(struct pci_dev *pdev,
340 struct plat_stmmacenet_data *plat)
341 {
342 plat->rx_queues_to_use = 8;
343 plat->tx_queues_to_use = 8;
344 plat->clk_ptp_rate = 200000000;
345
346 return intel_mgbe_common_data(pdev, plat);
347 }
348
ehl_sgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)349 static int ehl_sgmii_data(struct pci_dev *pdev,
350 struct plat_stmmacenet_data *plat)
351 {
352 plat->bus_id = 1;
353 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
354
355 plat->serdes_powerup = intel_serdes_powerup;
356 plat->serdes_powerdown = intel_serdes_powerdown;
357
358 return ehl_common_data(pdev, plat);
359 }
360
361 static struct stmmac_pci_info ehl_sgmii1g_info = {
362 .setup = ehl_sgmii_data,
363 };
364
ehl_rgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)365 static int ehl_rgmii_data(struct pci_dev *pdev,
366 struct plat_stmmacenet_data *plat)
367 {
368 plat->bus_id = 1;
369 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
370
371 return ehl_common_data(pdev, plat);
372 }
373
374 static struct stmmac_pci_info ehl_rgmii1g_info = {
375 .setup = ehl_rgmii_data,
376 };
377
ehl_pse0_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)378 static int ehl_pse0_common_data(struct pci_dev *pdev,
379 struct plat_stmmacenet_data *plat)
380 {
381 plat->bus_id = 2;
382 plat->addr64 = 32;
383 return ehl_common_data(pdev, plat);
384 }
385
ehl_pse0_rgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)386 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
387 struct plat_stmmacenet_data *plat)
388 {
389 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
390 return ehl_pse0_common_data(pdev, plat);
391 }
392
393 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
394 .setup = ehl_pse0_rgmii1g_data,
395 };
396
ehl_pse0_sgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)397 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
398 struct plat_stmmacenet_data *plat)
399 {
400 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
401 plat->serdes_powerup = intel_serdes_powerup;
402 plat->serdes_powerdown = intel_serdes_powerdown;
403 return ehl_pse0_common_data(pdev, plat);
404 }
405
406 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
407 .setup = ehl_pse0_sgmii1g_data,
408 };
409
ehl_pse1_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)410 static int ehl_pse1_common_data(struct pci_dev *pdev,
411 struct plat_stmmacenet_data *plat)
412 {
413 plat->bus_id = 3;
414 plat->addr64 = 32;
415 return ehl_common_data(pdev, plat);
416 }
417
ehl_pse1_rgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)418 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
419 struct plat_stmmacenet_data *plat)
420 {
421 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
422 return ehl_pse1_common_data(pdev, plat);
423 }
424
425 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
426 .setup = ehl_pse1_rgmii1g_data,
427 };
428
ehl_pse1_sgmii1g_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)429 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
430 struct plat_stmmacenet_data *plat)
431 {
432 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
433 plat->serdes_powerup = intel_serdes_powerup;
434 plat->serdes_powerdown = intel_serdes_powerdown;
435 return ehl_pse1_common_data(pdev, plat);
436 }
437
438 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
439 .setup = ehl_pse1_sgmii1g_data,
440 };
441
tgl_common_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)442 static int tgl_common_data(struct pci_dev *pdev,
443 struct plat_stmmacenet_data *plat)
444 {
445 plat->rx_queues_to_use = 6;
446 plat->tx_queues_to_use = 4;
447 plat->clk_ptp_rate = 200000000;
448
449 return intel_mgbe_common_data(pdev, plat);
450 }
451
tgl_sgmii_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)452 static int tgl_sgmii_data(struct pci_dev *pdev,
453 struct plat_stmmacenet_data *plat)
454 {
455 plat->bus_id = 1;
456 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
457 plat->serdes_powerup = intel_serdes_powerup;
458 plat->serdes_powerdown = intel_serdes_powerdown;
459 return tgl_common_data(pdev, plat);
460 }
461
462 static struct stmmac_pci_info tgl_sgmii1g_info = {
463 .setup = tgl_sgmii_data,
464 };
465
466 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
467 {
468 .func = 6,
469 .phy_addr = 1,
470 },
471 };
472
473 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
474 .func = galileo_stmmac_func_data,
475 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
476 };
477
478 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
479 {
480 .func = 6,
481 .phy_addr = 1,
482 },
483 {
484 .func = 7,
485 .phy_addr = 1,
486 },
487 };
488
489 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
490 .func = iot2040_stmmac_func_data,
491 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
492 };
493
494 static const struct dmi_system_id quark_pci_dmi[] = {
495 {
496 .matches = {
497 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
498 },
499 .driver_data = (void *)&galileo_stmmac_dmi_data,
500 },
501 {
502 .matches = {
503 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
504 },
505 .driver_data = (void *)&galileo_stmmac_dmi_data,
506 },
507 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
508 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
509 * has only one pci network device while other asset tags are
510 * for IOT2040 which has two.
511 */
512 {
513 .matches = {
514 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
515 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
516 "6ES7647-0AA00-0YA2"),
517 },
518 .driver_data = (void *)&galileo_stmmac_dmi_data,
519 },
520 {
521 .matches = {
522 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
523 },
524 .driver_data = (void *)&iot2040_stmmac_dmi_data,
525 },
526 {}
527 };
528
quark_default_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)529 static int quark_default_data(struct pci_dev *pdev,
530 struct plat_stmmacenet_data *plat)
531 {
532 int ret;
533
534 /* Set common default data first */
535 common_default_data(plat);
536
537 /* Refuse to load the driver and register net device if MAC controller
538 * does not connect to any PHY interface.
539 */
540 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
541 if (ret < 0) {
542 /* Return error to the caller on DMI enabled boards. */
543 if (dmi_get_system_info(DMI_BOARD_NAME))
544 return ret;
545
546 /* Galileo boards with old firmware don't support DMI. We always
547 * use 1 here as PHY address, so at least the first found MAC
548 * controller would be probed.
549 */
550 ret = 1;
551 }
552
553 plat->bus_id = pci_dev_id(pdev);
554 plat->phy_addr = ret;
555 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
556
557 plat->dma_cfg->pbl = 16;
558 plat->dma_cfg->pblx8 = true;
559 plat->dma_cfg->fixed_burst = 1;
560 /* AXI (TODO) */
561
562 return 0;
563 }
564
565 static const struct stmmac_pci_info quark_info = {
566 .setup = quark_default_data,
567 };
568
569 /**
570 * intel_eth_pci_probe
571 *
572 * @pdev: pci device pointer
573 * @id: pointer to table of device id/id's.
574 *
575 * Description: This probing function gets called for all PCI devices which
576 * match the ID table and are not "owned" by other driver yet. This function
577 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
578 * matches the device. The probe functions returns zero when the driver choose
579 * to take "ownership" of the device or an error code(-ve no) otherwise.
580 */
intel_eth_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)581 static int intel_eth_pci_probe(struct pci_dev *pdev,
582 const struct pci_device_id *id)
583 {
584 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
585 struct intel_priv_data *intel_priv;
586 struct plat_stmmacenet_data *plat;
587 struct stmmac_resources res;
588 int ret;
589
590 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
591 if (!intel_priv)
592 return -ENOMEM;
593
594 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
595 if (!plat)
596 return -ENOMEM;
597
598 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
599 sizeof(*plat->mdio_bus_data),
600 GFP_KERNEL);
601 if (!plat->mdio_bus_data)
602 return -ENOMEM;
603
604 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
605 GFP_KERNEL);
606 if (!plat->dma_cfg)
607 return -ENOMEM;
608
609 /* Enable pci device */
610 ret = pci_enable_device(pdev);
611 if (ret) {
612 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
613 __func__);
614 return ret;
615 }
616
617 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
618 if (ret)
619 return ret;
620
621 pci_set_master(pdev);
622
623 plat->bsp_priv = intel_priv;
624 intel_priv->mdio_adhoc_addr = 0x15;
625
626 ret = info->setup(pdev, plat);
627 if (ret)
628 return ret;
629
630 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
631 if (ret < 0)
632 return ret;
633
634 memset(&res, 0, sizeof(res));
635 res.addr = pcim_iomap_table(pdev)[0];
636 res.wol_irq = pci_irq_vector(pdev, 0);
637 res.irq = pci_irq_vector(pdev, 0);
638
639 if (plat->eee_usecs_rate > 0) {
640 u32 tx_lpi_usec;
641
642 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
643 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
644 }
645
646 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
647 if (ret) {
648 pci_free_irq_vectors(pdev);
649 clk_disable_unprepare(plat->stmmac_clk);
650 clk_unregister_fixed_rate(plat->stmmac_clk);
651 }
652
653 return ret;
654 }
655
656 /**
657 * intel_eth_pci_remove
658 *
659 * @pdev: platform device pointer
660 * Description: this function calls the main to free the net resources
661 * and releases the PCI resources.
662 */
intel_eth_pci_remove(struct pci_dev * pdev)663 static void intel_eth_pci_remove(struct pci_dev *pdev)
664 {
665 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
666 struct stmmac_priv *priv = netdev_priv(ndev);
667
668 stmmac_dvr_remove(&pdev->dev);
669
670 pci_free_irq_vectors(pdev);
671
672 clk_disable_unprepare(priv->plat->stmmac_clk);
673 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
674
675 pcim_iounmap_regions(pdev, BIT(0));
676
677 pci_disable_device(pdev);
678 }
679
intel_eth_pci_suspend(struct device * dev)680 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
681 {
682 struct pci_dev *pdev = to_pci_dev(dev);
683 int ret;
684
685 ret = stmmac_suspend(dev);
686 if (ret)
687 return ret;
688
689 ret = pci_save_state(pdev);
690 if (ret)
691 return ret;
692
693 pci_disable_device(pdev);
694 pci_wake_from_d3(pdev, true);
695 return 0;
696 }
697
intel_eth_pci_resume(struct device * dev)698 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
699 {
700 struct pci_dev *pdev = to_pci_dev(dev);
701 int ret;
702
703 pci_restore_state(pdev);
704 pci_set_power_state(pdev, PCI_D0);
705
706 ret = pci_enable_device(pdev);
707 if (ret)
708 return ret;
709
710 pci_set_master(pdev);
711
712 return stmmac_resume(dev);
713 }
714
715 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
716 intel_eth_pci_resume);
717
718 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
719 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30
720 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31
721 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32
722 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
723 * which are named PSE0 and PSE1
724 */
725 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0
726 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1
727 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2
728 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0
729 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1
730 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2
731 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac
732 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2
733 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
734
735 static const struct pci_device_id intel_eth_pci_id_table[] = {
736 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
737 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) },
738 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) },
739 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) },
740 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) },
741 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) },
742 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) },
743 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) },
744 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
745 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) },
746 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
747 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_info) },
748 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_info) },
749 {}
750 };
751 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
752
753 static struct pci_driver intel_eth_pci_driver = {
754 .name = "intel-eth-pci",
755 .id_table = intel_eth_pci_id_table,
756 .probe = intel_eth_pci_probe,
757 .remove = intel_eth_pci_remove,
758 .driver = {
759 .pm = &intel_eth_pm_ops,
760 },
761 };
762
763 module_pci_driver(intel_eth_pci_driver);
764
765 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
766 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
767 MODULE_LICENSE("GPL v2");
768