1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for the National Semiconductor DP83640 PHYTER
4 *
5 * Copyright (C) 2010 OMICRON electronics GmbH
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/crc32.h>
11 #include <linux/ethtool.h>
12 #include <linux/kernel.h>
13 #include <linux/list.h>
14 #include <linux/mii.h>
15 #include <linux/module.h>
16 #include <linux/net_tstamp.h>
17 #include <linux/netdevice.h>
18 #include <linux/if_vlan.h>
19 #include <linux/phy.h>
20 #include <linux/ptp_classify.h>
21 #include <linux/ptp_clock_kernel.h>
22
23 #include "dp83640_reg.h"
24
25 #define DP83640_PHY_ID 0x20005ce1
26 #define PAGESEL 0x13
27 #define MAX_RXTS 64
28 #define N_EXT_TS 6
29 #define N_PER_OUT 7
30 #define PSF_PTPVER 2
31 #define PSF_EVNT 0x4000
32 #define PSF_RX 0x2000
33 #define PSF_TX 0x1000
34 #define EXT_EVENT 1
35 #define CAL_EVENT 7
36 #define CAL_TRIGGER 1
37 #define DP83640_N_PINS 12
38
39 #define MII_DP83640_MICR 0x11
40 #define MII_DP83640_MISR 0x12
41
42 #define MII_DP83640_MICR_OE 0x1
43 #define MII_DP83640_MICR_IE 0x2
44
45 #define MII_DP83640_MISR_RHF_INT_EN 0x01
46 #define MII_DP83640_MISR_FHF_INT_EN 0x02
47 #define MII_DP83640_MISR_ANC_INT_EN 0x04
48 #define MII_DP83640_MISR_DUP_INT_EN 0x08
49 #define MII_DP83640_MISR_SPD_INT_EN 0x10
50 #define MII_DP83640_MISR_LINK_INT_EN 0x20
51 #define MII_DP83640_MISR_ED_INT_EN 0x40
52 #define MII_DP83640_MISR_LQ_INT_EN 0x80
53
54 /* phyter seems to miss the mark by 16 ns */
55 #define ADJTIME_FIX 16
56
57 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */
58
59 #if defined(__BIG_ENDIAN)
60 #define ENDIAN_FLAG 0
61 #elif defined(__LITTLE_ENDIAN)
62 #define ENDIAN_FLAG PSF_ENDIAN
63 #endif
64
65 struct dp83640_skb_info {
66 int ptp_type;
67 unsigned long tmo;
68 };
69
70 struct phy_rxts {
71 u16 ns_lo; /* ns[15:0] */
72 u16 ns_hi; /* overflow[1:0], ns[29:16] */
73 u16 sec_lo; /* sec[15:0] */
74 u16 sec_hi; /* sec[31:16] */
75 u16 seqid; /* sequenceId[15:0] */
76 u16 msgtype; /* messageType[3:0], hash[11:0] */
77 };
78
79 struct phy_txts {
80 u16 ns_lo; /* ns[15:0] */
81 u16 ns_hi; /* overflow[1:0], ns[29:16] */
82 u16 sec_lo; /* sec[15:0] */
83 u16 sec_hi; /* sec[31:16] */
84 };
85
86 struct rxts {
87 struct list_head list;
88 unsigned long tmo;
89 u64 ns;
90 u16 seqid;
91 u8 msgtype;
92 u16 hash;
93 };
94
95 struct dp83640_clock;
96
97 struct dp83640_private {
98 struct list_head list;
99 struct dp83640_clock *clock;
100 struct phy_device *phydev;
101 struct mii_timestamper mii_ts;
102 struct delayed_work ts_work;
103 int hwts_tx_en;
104 int hwts_rx_en;
105 int layer;
106 int version;
107 /* remember state of cfg0 during calibration */
108 int cfg0;
109 /* remember the last event time stamp */
110 struct phy_txts edata;
111 /* list of rx timestamps */
112 struct list_head rxts;
113 struct list_head rxpool;
114 struct rxts rx_pool_data[MAX_RXTS];
115 /* protects above three fields from concurrent access */
116 spinlock_t rx_lock;
117 /* queues of incoming and outgoing packets */
118 struct sk_buff_head rx_queue;
119 struct sk_buff_head tx_queue;
120 };
121
122 struct dp83640_clock {
123 /* keeps the instance in the 'phyter_clocks' list */
124 struct list_head list;
125 /* we create one clock instance per MII bus */
126 struct mii_bus *bus;
127 /* protects extended registers from concurrent access */
128 struct mutex extreg_lock;
129 /* remembers which page was last selected */
130 int page;
131 /* our advertised capabilities */
132 struct ptp_clock_info caps;
133 /* protects the three fields below from concurrent access */
134 struct mutex clock_lock;
135 /* the one phyter from which we shall read */
136 struct dp83640_private *chosen;
137 /* list of the other attached phyters, not chosen */
138 struct list_head phylist;
139 /* reference to our PTP hardware clock */
140 struct ptp_clock *ptp_clock;
141 };
142
143 /* globals */
144
145 enum {
146 CALIBRATE_GPIO,
147 PEROUT_GPIO,
148 EXTTS0_GPIO,
149 EXTTS1_GPIO,
150 EXTTS2_GPIO,
151 EXTTS3_GPIO,
152 EXTTS4_GPIO,
153 EXTTS5_GPIO,
154 GPIO_TABLE_SIZE
155 };
156
157 static int chosen_phy = -1;
158 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
159 1, 2, 3, 4, 8, 9, 10, 11
160 };
161
162 module_param(chosen_phy, int, 0444);
163 module_param_array(gpio_tab, ushort, NULL, 0444);
164
165 MODULE_PARM_DESC(chosen_phy, \
166 "The address of the PHY to use for the ancillary clock features");
167 MODULE_PARM_DESC(gpio_tab, \
168 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
169
dp83640_gpio_defaults(struct ptp_pin_desc * pd)170 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
171 {
172 int i, index;
173
174 for (i = 0; i < DP83640_N_PINS; i++) {
175 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
176 pd[i].index = i;
177 }
178
179 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
180 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
181 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
182 return;
183 }
184 }
185
186 index = gpio_tab[CALIBRATE_GPIO] - 1;
187 pd[index].func = PTP_PF_PHYSYNC;
188 pd[index].chan = 0;
189
190 index = gpio_tab[PEROUT_GPIO] - 1;
191 pd[index].func = PTP_PF_PEROUT;
192 pd[index].chan = 0;
193
194 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
195 index = gpio_tab[i] - 1;
196 pd[index].func = PTP_PF_EXTTS;
197 pd[index].chan = i - EXTTS0_GPIO;
198 }
199 }
200
201 /* a list of clocks and a mutex to protect it */
202 static LIST_HEAD(phyter_clocks);
203 static DEFINE_MUTEX(phyter_clocks_lock);
204
205 static void rx_timestamp_work(struct work_struct *work);
206
207 /* extended register access functions */
208
209 #define BROADCAST_ADDR 31
210
broadcast_write(struct phy_device * phydev,u32 regnum,u16 val)211 static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
212 u16 val)
213 {
214 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
215 }
216
217 /* Caller must hold extreg_lock. */
ext_read(struct phy_device * phydev,int page,u32 regnum)218 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
219 {
220 struct dp83640_private *dp83640 = phydev->priv;
221 int val;
222
223 if (dp83640->clock->page != page) {
224 broadcast_write(phydev, PAGESEL, page);
225 dp83640->clock->page = page;
226 }
227 val = phy_read(phydev, regnum);
228
229 return val;
230 }
231
232 /* Caller must hold extreg_lock. */
ext_write(int broadcast,struct phy_device * phydev,int page,u32 regnum,u16 val)233 static void ext_write(int broadcast, struct phy_device *phydev,
234 int page, u32 regnum, u16 val)
235 {
236 struct dp83640_private *dp83640 = phydev->priv;
237
238 if (dp83640->clock->page != page) {
239 broadcast_write(phydev, PAGESEL, page);
240 dp83640->clock->page = page;
241 }
242 if (broadcast)
243 broadcast_write(phydev, regnum, val);
244 else
245 phy_write(phydev, regnum, val);
246 }
247
248 /* Caller must hold extreg_lock. */
tdr_write(int bc,struct phy_device * dev,const struct timespec64 * ts,u16 cmd)249 static int tdr_write(int bc, struct phy_device *dev,
250 const struct timespec64 *ts, u16 cmd)
251 {
252 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
253 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
254 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
255 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
256
257 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
258
259 return 0;
260 }
261
262 /* convert phy timestamps into driver timestamps */
263
phy2rxts(struct phy_rxts * p,struct rxts * rxts)264 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
265 {
266 u32 sec;
267
268 sec = p->sec_lo;
269 sec |= p->sec_hi << 16;
270
271 rxts->ns = p->ns_lo;
272 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
273 rxts->ns += ((u64)sec) * 1000000000ULL;
274 rxts->seqid = p->seqid;
275 rxts->msgtype = (p->msgtype >> 12) & 0xf;
276 rxts->hash = p->msgtype & 0x0fff;
277 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
278 }
279
phy2txts(struct phy_txts * p)280 static u64 phy2txts(struct phy_txts *p)
281 {
282 u64 ns;
283 u32 sec;
284
285 sec = p->sec_lo;
286 sec |= p->sec_hi << 16;
287
288 ns = p->ns_lo;
289 ns |= (p->ns_hi & 0x3fff) << 16;
290 ns += ((u64)sec) * 1000000000ULL;
291
292 return ns;
293 }
294
periodic_output(struct dp83640_clock * clock,struct ptp_clock_request * clkreq,bool on,int trigger)295 static int periodic_output(struct dp83640_clock *clock,
296 struct ptp_clock_request *clkreq, bool on,
297 int trigger)
298 {
299 struct dp83640_private *dp83640 = clock->chosen;
300 struct phy_device *phydev = dp83640->phydev;
301 u32 sec, nsec, pwidth;
302 u16 gpio, ptp_trig, val;
303
304 if (on) {
305 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
306 trigger);
307 if (gpio < 1)
308 return -EINVAL;
309 } else {
310 gpio = 0;
311 }
312
313 ptp_trig = TRIG_WR |
314 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
315 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
316 TRIG_PER |
317 TRIG_PULSE;
318
319 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
320
321 if (!on) {
322 val |= TRIG_DIS;
323 mutex_lock(&clock->extreg_lock);
324 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
325 ext_write(0, phydev, PAGE4, PTP_CTL, val);
326 mutex_unlock(&clock->extreg_lock);
327 return 0;
328 }
329
330 sec = clkreq->perout.start.sec;
331 nsec = clkreq->perout.start.nsec;
332 pwidth = clkreq->perout.period.sec * 1000000000UL;
333 pwidth += clkreq->perout.period.nsec;
334 pwidth /= 2;
335
336 mutex_lock(&clock->extreg_lock);
337
338 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
339
340 /*load trigger*/
341 val |= TRIG_LOAD;
342 ext_write(0, phydev, PAGE4, PTP_CTL, val);
343 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
344 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
345 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
346 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
347 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
348 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
349 /* Triggers 0 and 1 has programmable pulsewidth2 */
350 if (trigger < 2) {
351 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
352 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
353 }
354
355 /*enable trigger*/
356 val &= ~TRIG_LOAD;
357 val |= TRIG_EN;
358 ext_write(0, phydev, PAGE4, PTP_CTL, val);
359
360 mutex_unlock(&clock->extreg_lock);
361 return 0;
362 }
363
364 /* ptp clock methods */
365
ptp_dp83640_adjfine(struct ptp_clock_info * ptp,long scaled_ppm)366 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
367 {
368 struct dp83640_clock *clock =
369 container_of(ptp, struct dp83640_clock, caps);
370 struct phy_device *phydev = clock->chosen->phydev;
371 u64 rate;
372 int neg_adj = 0;
373 u16 hi, lo;
374
375 if (scaled_ppm < 0) {
376 neg_adj = 1;
377 scaled_ppm = -scaled_ppm;
378 }
379 rate = scaled_ppm;
380 rate <<= 13;
381 rate = div_u64(rate, 15625);
382
383 hi = (rate >> 16) & PTP_RATE_HI_MASK;
384 if (neg_adj)
385 hi |= PTP_RATE_DIR;
386
387 lo = rate & 0xffff;
388
389 mutex_lock(&clock->extreg_lock);
390
391 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
392 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
393
394 mutex_unlock(&clock->extreg_lock);
395
396 return 0;
397 }
398
ptp_dp83640_adjtime(struct ptp_clock_info * ptp,s64 delta)399 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
400 {
401 struct dp83640_clock *clock =
402 container_of(ptp, struct dp83640_clock, caps);
403 struct phy_device *phydev = clock->chosen->phydev;
404 struct timespec64 ts;
405 int err;
406
407 delta += ADJTIME_FIX;
408
409 ts = ns_to_timespec64(delta);
410
411 mutex_lock(&clock->extreg_lock);
412
413 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
414
415 mutex_unlock(&clock->extreg_lock);
416
417 return err;
418 }
419
ptp_dp83640_gettime(struct ptp_clock_info * ptp,struct timespec64 * ts)420 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
421 struct timespec64 *ts)
422 {
423 struct dp83640_clock *clock =
424 container_of(ptp, struct dp83640_clock, caps);
425 struct phy_device *phydev = clock->chosen->phydev;
426 unsigned int val[4];
427
428 mutex_lock(&clock->extreg_lock);
429
430 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
431
432 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
433 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
434 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
435 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
436
437 mutex_unlock(&clock->extreg_lock);
438
439 ts->tv_nsec = val[0] | (val[1] << 16);
440 ts->tv_sec = val[2] | (val[3] << 16);
441
442 return 0;
443 }
444
ptp_dp83640_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)445 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
446 const struct timespec64 *ts)
447 {
448 struct dp83640_clock *clock =
449 container_of(ptp, struct dp83640_clock, caps);
450 struct phy_device *phydev = clock->chosen->phydev;
451 int err;
452
453 mutex_lock(&clock->extreg_lock);
454
455 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
456
457 mutex_unlock(&clock->extreg_lock);
458
459 return err;
460 }
461
ptp_dp83640_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)462 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
463 struct ptp_clock_request *rq, int on)
464 {
465 struct dp83640_clock *clock =
466 container_of(ptp, struct dp83640_clock, caps);
467 struct phy_device *phydev = clock->chosen->phydev;
468 unsigned int index;
469 u16 evnt, event_num, gpio_num;
470
471 switch (rq->type) {
472 case PTP_CLK_REQ_EXTTS:
473 /* Reject requests with unsupported flags */
474 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
475 PTP_RISING_EDGE |
476 PTP_FALLING_EDGE |
477 PTP_STRICT_FLAGS))
478 return -EOPNOTSUPP;
479
480 /* Reject requests to enable time stamping on both edges. */
481 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
482 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
483 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
484 return -EOPNOTSUPP;
485
486 index = rq->extts.index;
487 if (index >= N_EXT_TS)
488 return -EINVAL;
489 event_num = EXT_EVENT + index;
490 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
491 if (on) {
492 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
493 PTP_PF_EXTTS, index);
494 if (gpio_num < 1)
495 return -EINVAL;
496 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
497 if (rq->extts.flags & PTP_FALLING_EDGE)
498 evnt |= EVNT_FALL;
499 else
500 evnt |= EVNT_RISE;
501 }
502 mutex_lock(&clock->extreg_lock);
503 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
504 mutex_unlock(&clock->extreg_lock);
505 return 0;
506
507 case PTP_CLK_REQ_PEROUT:
508 /* Reject requests with unsupported flags */
509 if (rq->perout.flags)
510 return -EOPNOTSUPP;
511 if (rq->perout.index >= N_PER_OUT)
512 return -EINVAL;
513 return periodic_output(clock, rq, on, rq->perout.index);
514
515 default:
516 break;
517 }
518
519 return -EOPNOTSUPP;
520 }
521
ptp_dp83640_verify(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)522 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
523 enum ptp_pin_function func, unsigned int chan)
524 {
525 struct dp83640_clock *clock =
526 container_of(ptp, struct dp83640_clock, caps);
527
528 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
529 !list_empty(&clock->phylist))
530 return 1;
531
532 if (func == PTP_PF_PHYSYNC)
533 return 1;
534
535 return 0;
536 }
537
538 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
539 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
540
enable_status_frames(struct phy_device * phydev,bool on)541 static void enable_status_frames(struct phy_device *phydev, bool on)
542 {
543 struct dp83640_private *dp83640 = phydev->priv;
544 struct dp83640_clock *clock = dp83640->clock;
545 u16 cfg0 = 0, ver;
546
547 if (on)
548 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
549
550 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
551
552 mutex_lock(&clock->extreg_lock);
553
554 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
555 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
556
557 mutex_unlock(&clock->extreg_lock);
558
559 if (!phydev->attached_dev) {
560 phydev_warn(phydev,
561 "expected to find an attached netdevice\n");
562 return;
563 }
564
565 if (on) {
566 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
567 phydev_warn(phydev, "failed to add mc address\n");
568 } else {
569 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
570 phydev_warn(phydev, "failed to delete mc address\n");
571 }
572 }
573
is_status_frame(struct sk_buff * skb,int type)574 static bool is_status_frame(struct sk_buff *skb, int type)
575 {
576 struct ethhdr *h = eth_hdr(skb);
577
578 if (PTP_CLASS_V2_L2 == type &&
579 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
580 return true;
581 else
582 return false;
583 }
584
expired(struct rxts * rxts)585 static int expired(struct rxts *rxts)
586 {
587 return time_after(jiffies, rxts->tmo);
588 }
589
590 /* Caller must hold rx_lock. */
prune_rx_ts(struct dp83640_private * dp83640)591 static void prune_rx_ts(struct dp83640_private *dp83640)
592 {
593 struct list_head *this, *next;
594 struct rxts *rxts;
595
596 list_for_each_safe(this, next, &dp83640->rxts) {
597 rxts = list_entry(this, struct rxts, list);
598 if (expired(rxts)) {
599 list_del_init(&rxts->list);
600 list_add(&rxts->list, &dp83640->rxpool);
601 }
602 }
603 }
604
605 /* synchronize the phyters so they act as one clock */
606
enable_broadcast(struct phy_device * phydev,int init_page,int on)607 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
608 {
609 int val;
610 phy_write(phydev, PAGESEL, 0);
611 val = phy_read(phydev, PHYCR2);
612 if (on)
613 val |= BC_WRITE;
614 else
615 val &= ~BC_WRITE;
616 phy_write(phydev, PHYCR2, val);
617 phy_write(phydev, PAGESEL, init_page);
618 }
619
recalibrate(struct dp83640_clock * clock)620 static void recalibrate(struct dp83640_clock *clock)
621 {
622 s64 now, diff;
623 struct phy_txts event_ts;
624 struct timespec64 ts;
625 struct list_head *this;
626 struct dp83640_private *tmp;
627 struct phy_device *master = clock->chosen->phydev;
628 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
629
630 trigger = CAL_TRIGGER;
631 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
632 if (cal_gpio < 1) {
633 pr_err("PHY calibration pin not available - PHY is not calibrated.");
634 return;
635 }
636
637 mutex_lock(&clock->extreg_lock);
638
639 /*
640 * enable broadcast, disable status frames, enable ptp clock
641 */
642 list_for_each(this, &clock->phylist) {
643 tmp = list_entry(this, struct dp83640_private, list);
644 enable_broadcast(tmp->phydev, clock->page, 1);
645 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
646 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
647 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
648 }
649 enable_broadcast(master, clock->page, 1);
650 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
651 ext_write(0, master, PAGE5, PSF_CFG0, 0);
652 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
653
654 /*
655 * enable an event timestamp
656 */
657 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
658 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
659 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
660
661 list_for_each(this, &clock->phylist) {
662 tmp = list_entry(this, struct dp83640_private, list);
663 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
664 }
665 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
666
667 /*
668 * configure a trigger
669 */
670 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
671 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
672 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
673 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
674
675 /* load trigger */
676 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
677 val |= TRIG_LOAD;
678 ext_write(0, master, PAGE4, PTP_CTL, val);
679
680 /* enable trigger */
681 val &= ~TRIG_LOAD;
682 val |= TRIG_EN;
683 ext_write(0, master, PAGE4, PTP_CTL, val);
684
685 /* disable trigger */
686 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
687 val |= TRIG_DIS;
688 ext_write(0, master, PAGE4, PTP_CTL, val);
689
690 /*
691 * read out and correct offsets
692 */
693 val = ext_read(master, PAGE4, PTP_STS);
694 phydev_info(master, "master PTP_STS 0x%04hx\n", val);
695 val = ext_read(master, PAGE4, PTP_ESTS);
696 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
697 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
698 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
699 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
700 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
701 now = phy2txts(&event_ts);
702
703 list_for_each(this, &clock->phylist) {
704 tmp = list_entry(this, struct dp83640_private, list);
705 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
706 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
707 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
708 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
709 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
710 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
711 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
712 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
713 diff = now - (s64) phy2txts(&event_ts);
714 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
715 diff);
716 diff += ADJTIME_FIX;
717 ts = ns_to_timespec64(diff);
718 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
719 }
720
721 /*
722 * restore status frames
723 */
724 list_for_each(this, &clock->phylist) {
725 tmp = list_entry(this, struct dp83640_private, list);
726 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
727 }
728 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
729
730 mutex_unlock(&clock->extreg_lock);
731 }
732
733 /* time stamping methods */
734
exts_chan_to_edata(int ch)735 static inline u16 exts_chan_to_edata(int ch)
736 {
737 return 1 << ((ch + EXT_EVENT) * 2);
738 }
739
decode_evnt(struct dp83640_private * dp83640,void * data,int len,u16 ests)740 static int decode_evnt(struct dp83640_private *dp83640,
741 void *data, int len, u16 ests)
742 {
743 struct phy_txts *phy_txts;
744 struct ptp_clock_event event;
745 int i, parsed;
746 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
747 u16 ext_status = 0;
748
749 /* calculate length of the event timestamp status message */
750 if (ests & MULT_EVNT)
751 parsed = (words + 2) * sizeof(u16);
752 else
753 parsed = (words + 1) * sizeof(u16);
754
755 /* check if enough data is available */
756 if (len < parsed)
757 return len;
758
759 if (ests & MULT_EVNT) {
760 ext_status = *(u16 *) data;
761 data += sizeof(ext_status);
762 }
763
764 phy_txts = data;
765
766 switch (words) {
767 case 3:
768 dp83640->edata.sec_hi = phy_txts->sec_hi;
769 fallthrough;
770 case 2:
771 dp83640->edata.sec_lo = phy_txts->sec_lo;
772 fallthrough;
773 case 1:
774 dp83640->edata.ns_hi = phy_txts->ns_hi;
775 fallthrough;
776 case 0:
777 dp83640->edata.ns_lo = phy_txts->ns_lo;
778 }
779
780 if (!ext_status) {
781 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
782 ext_status = exts_chan_to_edata(i);
783 }
784
785 event.type = PTP_CLOCK_EXTTS;
786 event.timestamp = phy2txts(&dp83640->edata);
787
788 /* Compensate for input path and synchronization delays */
789 event.timestamp -= 35;
790
791 for (i = 0; i < N_EXT_TS; i++) {
792 if (ext_status & exts_chan_to_edata(i)) {
793 event.index = i;
794 ptp_clock_event(dp83640->clock->ptp_clock, &event);
795 }
796 }
797
798 return parsed;
799 }
800
801 #define DP83640_PACKET_HASH_LEN 10
802
match(struct sk_buff * skb,unsigned int type,struct rxts * rxts)803 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
804 {
805 struct ptp_header *hdr;
806 u8 msgtype;
807 u16 seqid;
808 u16 hash;
809
810 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
811
812 hdr = ptp_parse_header(skb, type);
813 if (!hdr)
814 return 0;
815
816 msgtype = ptp_get_msgtype(hdr, type);
817
818 if (rxts->msgtype != (msgtype & 0xf))
819 return 0;
820
821 seqid = be16_to_cpu(hdr->sequence_id);
822 if (rxts->seqid != seqid)
823 return 0;
824
825 hash = ether_crc(DP83640_PACKET_HASH_LEN,
826 (unsigned char *)&hdr->source_port_identity) >> 20;
827 if (rxts->hash != hash)
828 return 0;
829
830 return 1;
831 }
832
decode_rxts(struct dp83640_private * dp83640,struct phy_rxts * phy_rxts)833 static void decode_rxts(struct dp83640_private *dp83640,
834 struct phy_rxts *phy_rxts)
835 {
836 struct rxts *rxts;
837 struct skb_shared_hwtstamps *shhwtstamps = NULL;
838 struct sk_buff *skb;
839 unsigned long flags;
840 u8 overflow;
841
842 overflow = (phy_rxts->ns_hi >> 14) & 0x3;
843 if (overflow)
844 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
845
846 spin_lock_irqsave(&dp83640->rx_lock, flags);
847
848 prune_rx_ts(dp83640);
849
850 if (list_empty(&dp83640->rxpool)) {
851 pr_debug("rx timestamp pool is empty\n");
852 goto out;
853 }
854 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
855 list_del_init(&rxts->list);
856 phy2rxts(phy_rxts, rxts);
857
858 spin_lock(&dp83640->rx_queue.lock);
859 skb_queue_walk(&dp83640->rx_queue, skb) {
860 struct dp83640_skb_info *skb_info;
861
862 skb_info = (struct dp83640_skb_info *)skb->cb;
863 if (match(skb, skb_info->ptp_type, rxts)) {
864 __skb_unlink(skb, &dp83640->rx_queue);
865 shhwtstamps = skb_hwtstamps(skb);
866 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
867 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
868 list_add(&rxts->list, &dp83640->rxpool);
869 break;
870 }
871 }
872 spin_unlock(&dp83640->rx_queue.lock);
873
874 if (!shhwtstamps)
875 list_add_tail(&rxts->list, &dp83640->rxts);
876 out:
877 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
878
879 if (shhwtstamps)
880 netif_rx_ni(skb);
881 }
882
decode_txts(struct dp83640_private * dp83640,struct phy_txts * phy_txts)883 static void decode_txts(struct dp83640_private *dp83640,
884 struct phy_txts *phy_txts)
885 {
886 struct skb_shared_hwtstamps shhwtstamps;
887 struct dp83640_skb_info *skb_info;
888 struct sk_buff *skb;
889 u8 overflow;
890 u64 ns;
891
892 /* We must already have the skb that triggered this. */
893 again:
894 skb = skb_dequeue(&dp83640->tx_queue);
895 if (!skb) {
896 pr_debug("have timestamp but tx_queue empty\n");
897 return;
898 }
899
900 overflow = (phy_txts->ns_hi >> 14) & 0x3;
901 if (overflow) {
902 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
903 while (skb) {
904 kfree_skb(skb);
905 skb = skb_dequeue(&dp83640->tx_queue);
906 }
907 return;
908 }
909 skb_info = (struct dp83640_skb_info *)skb->cb;
910 if (time_after(jiffies, skb_info->tmo)) {
911 kfree_skb(skb);
912 goto again;
913 }
914
915 ns = phy2txts(phy_txts);
916 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
917 shhwtstamps.hwtstamp = ns_to_ktime(ns);
918 skb_complete_tx_timestamp(skb, &shhwtstamps);
919 }
920
decode_status_frame(struct dp83640_private * dp83640,struct sk_buff * skb)921 static void decode_status_frame(struct dp83640_private *dp83640,
922 struct sk_buff *skb)
923 {
924 struct phy_rxts *phy_rxts;
925 struct phy_txts *phy_txts;
926 u8 *ptr;
927 int len, size;
928 u16 ests, type;
929
930 ptr = skb->data + 2;
931
932 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
933
934 type = *(u16 *)ptr;
935 ests = type & 0x0fff;
936 type = type & 0xf000;
937 len -= sizeof(type);
938 ptr += sizeof(type);
939
940 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
941
942 phy_rxts = (struct phy_rxts *) ptr;
943 decode_rxts(dp83640, phy_rxts);
944 size = sizeof(*phy_rxts);
945
946 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
947
948 phy_txts = (struct phy_txts *) ptr;
949 decode_txts(dp83640, phy_txts);
950 size = sizeof(*phy_txts);
951
952 } else if (PSF_EVNT == type) {
953
954 size = decode_evnt(dp83640, ptr, len, ests);
955
956 } else {
957 size = 0;
958 break;
959 }
960 ptr += size;
961 }
962 }
963
is_sync(struct sk_buff * skb,int type)964 static int is_sync(struct sk_buff *skb, int type)
965 {
966 struct ptp_header *hdr;
967 u8 msgtype;
968
969 hdr = ptp_parse_header(skb, type);
970 if (!hdr)
971 return 0;
972
973 msgtype = ptp_get_msgtype(hdr, type);
974
975 return (msgtype & 0xf) == 0;
976 }
977
dp83640_free_clocks(void)978 static void dp83640_free_clocks(void)
979 {
980 struct dp83640_clock *clock;
981 struct list_head *this, *next;
982
983 mutex_lock(&phyter_clocks_lock);
984
985 list_for_each_safe(this, next, &phyter_clocks) {
986 clock = list_entry(this, struct dp83640_clock, list);
987 if (!list_empty(&clock->phylist)) {
988 pr_warn("phy list non-empty while unloading\n");
989 BUG();
990 }
991 list_del(&clock->list);
992 mutex_destroy(&clock->extreg_lock);
993 mutex_destroy(&clock->clock_lock);
994 put_device(&clock->bus->dev);
995 kfree(clock->caps.pin_config);
996 kfree(clock);
997 }
998
999 mutex_unlock(&phyter_clocks_lock);
1000 }
1001
dp83640_clock_init(struct dp83640_clock * clock,struct mii_bus * bus)1002 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1003 {
1004 INIT_LIST_HEAD(&clock->list);
1005 clock->bus = bus;
1006 mutex_init(&clock->extreg_lock);
1007 mutex_init(&clock->clock_lock);
1008 INIT_LIST_HEAD(&clock->phylist);
1009 clock->caps.owner = THIS_MODULE;
1010 sprintf(clock->caps.name, "dp83640 timer");
1011 clock->caps.max_adj = 1953124;
1012 clock->caps.n_alarm = 0;
1013 clock->caps.n_ext_ts = N_EXT_TS;
1014 clock->caps.n_per_out = N_PER_OUT;
1015 clock->caps.n_pins = DP83640_N_PINS;
1016 clock->caps.pps = 0;
1017 clock->caps.adjfine = ptp_dp83640_adjfine;
1018 clock->caps.adjtime = ptp_dp83640_adjtime;
1019 clock->caps.gettime64 = ptp_dp83640_gettime;
1020 clock->caps.settime64 = ptp_dp83640_settime;
1021 clock->caps.enable = ptp_dp83640_enable;
1022 clock->caps.verify = ptp_dp83640_verify;
1023 /*
1024 * Convert the module param defaults into a dynamic pin configuration.
1025 */
1026 dp83640_gpio_defaults(clock->caps.pin_config);
1027 /*
1028 * Get a reference to this bus instance.
1029 */
1030 get_device(&bus->dev);
1031 }
1032
choose_this_phy(struct dp83640_clock * clock,struct phy_device * phydev)1033 static int choose_this_phy(struct dp83640_clock *clock,
1034 struct phy_device *phydev)
1035 {
1036 if (chosen_phy == -1 && !clock->chosen)
1037 return 1;
1038
1039 if (chosen_phy == phydev->mdio.addr)
1040 return 1;
1041
1042 return 0;
1043 }
1044
dp83640_clock_get(struct dp83640_clock * clock)1045 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1046 {
1047 if (clock)
1048 mutex_lock(&clock->clock_lock);
1049 return clock;
1050 }
1051
1052 /*
1053 * Look up and lock a clock by bus instance.
1054 * If there is no clock for this bus, then create it first.
1055 */
dp83640_clock_get_bus(struct mii_bus * bus)1056 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1057 {
1058 struct dp83640_clock *clock = NULL, *tmp;
1059 struct list_head *this;
1060
1061 mutex_lock(&phyter_clocks_lock);
1062
1063 list_for_each(this, &phyter_clocks) {
1064 tmp = list_entry(this, struct dp83640_clock, list);
1065 if (tmp->bus == bus) {
1066 clock = tmp;
1067 break;
1068 }
1069 }
1070 if (clock)
1071 goto out;
1072
1073 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1074 if (!clock)
1075 goto out;
1076
1077 clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1078 sizeof(struct ptp_pin_desc),
1079 GFP_KERNEL);
1080 if (!clock->caps.pin_config) {
1081 kfree(clock);
1082 clock = NULL;
1083 goto out;
1084 }
1085 dp83640_clock_init(clock, bus);
1086 list_add_tail(&clock->list, &phyter_clocks);
1087 out:
1088 mutex_unlock(&phyter_clocks_lock);
1089
1090 return dp83640_clock_get(clock);
1091 }
1092
dp83640_clock_put(struct dp83640_clock * clock)1093 static void dp83640_clock_put(struct dp83640_clock *clock)
1094 {
1095 mutex_unlock(&clock->clock_lock);
1096 }
1097
dp83640_soft_reset(struct phy_device * phydev)1098 static int dp83640_soft_reset(struct phy_device *phydev)
1099 {
1100 int ret;
1101
1102 ret = genphy_soft_reset(phydev);
1103 if (ret < 0)
1104 return ret;
1105
1106 /* From DP83640 datasheet: "Software driver code must wait 3 us
1107 * following a software reset before allowing further serial MII
1108 * operations with the DP83640."
1109 */
1110 udelay(10); /* Taking udelay inaccuracy into account */
1111
1112 return 0;
1113 }
1114
dp83640_config_init(struct phy_device * phydev)1115 static int dp83640_config_init(struct phy_device *phydev)
1116 {
1117 struct dp83640_private *dp83640 = phydev->priv;
1118 struct dp83640_clock *clock = dp83640->clock;
1119
1120 if (clock->chosen && !list_empty(&clock->phylist))
1121 recalibrate(clock);
1122 else {
1123 mutex_lock(&clock->extreg_lock);
1124 enable_broadcast(phydev, clock->page, 1);
1125 mutex_unlock(&clock->extreg_lock);
1126 }
1127
1128 enable_status_frames(phydev, true);
1129
1130 mutex_lock(&clock->extreg_lock);
1131 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1132 mutex_unlock(&clock->extreg_lock);
1133
1134 return 0;
1135 }
1136
dp83640_ack_interrupt(struct phy_device * phydev)1137 static int dp83640_ack_interrupt(struct phy_device *phydev)
1138 {
1139 int err = phy_read(phydev, MII_DP83640_MISR);
1140
1141 if (err < 0)
1142 return err;
1143
1144 return 0;
1145 }
1146
dp83640_config_intr(struct phy_device * phydev)1147 static int dp83640_config_intr(struct phy_device *phydev)
1148 {
1149 int micr;
1150 int misr;
1151 int err;
1152
1153 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1154 misr = phy_read(phydev, MII_DP83640_MISR);
1155 if (misr < 0)
1156 return misr;
1157 misr |=
1158 (MII_DP83640_MISR_ANC_INT_EN |
1159 MII_DP83640_MISR_DUP_INT_EN |
1160 MII_DP83640_MISR_SPD_INT_EN |
1161 MII_DP83640_MISR_LINK_INT_EN);
1162 err = phy_write(phydev, MII_DP83640_MISR, misr);
1163 if (err < 0)
1164 return err;
1165
1166 micr = phy_read(phydev, MII_DP83640_MICR);
1167 if (micr < 0)
1168 return micr;
1169 micr |=
1170 (MII_DP83640_MICR_OE |
1171 MII_DP83640_MICR_IE);
1172 return phy_write(phydev, MII_DP83640_MICR, micr);
1173 } else {
1174 micr = phy_read(phydev, MII_DP83640_MICR);
1175 if (micr < 0)
1176 return micr;
1177 micr &=
1178 ~(MII_DP83640_MICR_OE |
1179 MII_DP83640_MICR_IE);
1180 err = phy_write(phydev, MII_DP83640_MICR, micr);
1181 if (err < 0)
1182 return err;
1183
1184 misr = phy_read(phydev, MII_DP83640_MISR);
1185 if (misr < 0)
1186 return misr;
1187 misr &=
1188 ~(MII_DP83640_MISR_ANC_INT_EN |
1189 MII_DP83640_MISR_DUP_INT_EN |
1190 MII_DP83640_MISR_SPD_INT_EN |
1191 MII_DP83640_MISR_LINK_INT_EN);
1192 return phy_write(phydev, MII_DP83640_MISR, misr);
1193 }
1194 }
1195
dp83640_hwtstamp(struct mii_timestamper * mii_ts,struct ifreq * ifr)1196 static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
1197 {
1198 struct dp83640_private *dp83640 =
1199 container_of(mii_ts, struct dp83640_private, mii_ts);
1200 struct hwtstamp_config cfg;
1201 u16 txcfg0, rxcfg0;
1202
1203 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1204 return -EFAULT;
1205
1206 if (cfg.flags) /* reserved for future extensions */
1207 return -EINVAL;
1208
1209 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1210 return -ERANGE;
1211
1212 dp83640->hwts_tx_en = cfg.tx_type;
1213
1214 switch (cfg.rx_filter) {
1215 case HWTSTAMP_FILTER_NONE:
1216 dp83640->hwts_rx_en = 0;
1217 dp83640->layer = 0;
1218 dp83640->version = 0;
1219 break;
1220 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1221 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1222 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1223 dp83640->hwts_rx_en = 1;
1224 dp83640->layer = PTP_CLASS_L4;
1225 dp83640->version = PTP_CLASS_V1;
1226 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1227 break;
1228 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1229 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1230 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1231 dp83640->hwts_rx_en = 1;
1232 dp83640->layer = PTP_CLASS_L4;
1233 dp83640->version = PTP_CLASS_V2;
1234 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
1235 break;
1236 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1237 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1238 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1239 dp83640->hwts_rx_en = 1;
1240 dp83640->layer = PTP_CLASS_L2;
1241 dp83640->version = PTP_CLASS_V2;
1242 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1243 break;
1244 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1245 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1246 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1247 dp83640->hwts_rx_en = 1;
1248 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1249 dp83640->version = PTP_CLASS_V2;
1250 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1251 break;
1252 default:
1253 return -ERANGE;
1254 }
1255
1256 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1257 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1258
1259 if (dp83640->layer & PTP_CLASS_L2) {
1260 txcfg0 |= TX_L2_EN;
1261 rxcfg0 |= RX_L2_EN;
1262 }
1263 if (dp83640->layer & PTP_CLASS_L4) {
1264 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1265 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1266 }
1267
1268 if (dp83640->hwts_tx_en)
1269 txcfg0 |= TX_TS_EN;
1270
1271 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1272 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1273
1274 if (dp83640->hwts_rx_en)
1275 rxcfg0 |= RX_TS_EN;
1276
1277 mutex_lock(&dp83640->clock->extreg_lock);
1278
1279 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);
1280 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1281
1282 mutex_unlock(&dp83640->clock->extreg_lock);
1283
1284 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1285 }
1286
rx_timestamp_work(struct work_struct * work)1287 static void rx_timestamp_work(struct work_struct *work)
1288 {
1289 struct dp83640_private *dp83640 =
1290 container_of(work, struct dp83640_private, ts_work.work);
1291 struct sk_buff *skb;
1292
1293 /* Deliver expired packets. */
1294 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1295 struct dp83640_skb_info *skb_info;
1296
1297 skb_info = (struct dp83640_skb_info *)skb->cb;
1298 if (!time_after(jiffies, skb_info->tmo)) {
1299 skb_queue_head(&dp83640->rx_queue, skb);
1300 break;
1301 }
1302
1303 netif_rx_ni(skb);
1304 }
1305
1306 if (!skb_queue_empty(&dp83640->rx_queue))
1307 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1308 }
1309
dp83640_rxtstamp(struct mii_timestamper * mii_ts,struct sk_buff * skb,int type)1310 static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts,
1311 struct sk_buff *skb, int type)
1312 {
1313 struct dp83640_private *dp83640 =
1314 container_of(mii_ts, struct dp83640_private, mii_ts);
1315 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1316 struct list_head *this, *next;
1317 struct rxts *rxts;
1318 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1319 unsigned long flags;
1320
1321 if (is_status_frame(skb, type)) {
1322 decode_status_frame(dp83640, skb);
1323 kfree_skb(skb);
1324 return true;
1325 }
1326
1327 if (!dp83640->hwts_rx_en)
1328 return false;
1329
1330 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1331 return false;
1332
1333 spin_lock_irqsave(&dp83640->rx_lock, flags);
1334 prune_rx_ts(dp83640);
1335 list_for_each_safe(this, next, &dp83640->rxts) {
1336 rxts = list_entry(this, struct rxts, list);
1337 if (match(skb, type, rxts)) {
1338 shhwtstamps = skb_hwtstamps(skb);
1339 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1340 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1341 list_del_init(&rxts->list);
1342 list_add(&rxts->list, &dp83640->rxpool);
1343 break;
1344 }
1345 }
1346 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1347
1348 if (!shhwtstamps) {
1349 skb_info->ptp_type = type;
1350 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1351 skb_queue_tail(&dp83640->rx_queue, skb);
1352 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1353 } else {
1354 netif_rx_ni(skb);
1355 }
1356
1357 return true;
1358 }
1359
dp83640_txtstamp(struct mii_timestamper * mii_ts,struct sk_buff * skb,int type)1360 static void dp83640_txtstamp(struct mii_timestamper *mii_ts,
1361 struct sk_buff *skb, int type)
1362 {
1363 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1364 struct dp83640_private *dp83640 =
1365 container_of(mii_ts, struct dp83640_private, mii_ts);
1366
1367 switch (dp83640->hwts_tx_en) {
1368
1369 case HWTSTAMP_TX_ONESTEP_SYNC:
1370 if (is_sync(skb, type)) {
1371 kfree_skb(skb);
1372 return;
1373 }
1374 fallthrough;
1375 case HWTSTAMP_TX_ON:
1376 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1377 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1378 skb_queue_tail(&dp83640->tx_queue, skb);
1379 break;
1380
1381 case HWTSTAMP_TX_OFF:
1382 default:
1383 kfree_skb(skb);
1384 break;
1385 }
1386 }
1387
dp83640_ts_info(struct mii_timestamper * mii_ts,struct ethtool_ts_info * info)1388 static int dp83640_ts_info(struct mii_timestamper *mii_ts,
1389 struct ethtool_ts_info *info)
1390 {
1391 struct dp83640_private *dp83640 =
1392 container_of(mii_ts, struct dp83640_private, mii_ts);
1393
1394 info->so_timestamping =
1395 SOF_TIMESTAMPING_TX_HARDWARE |
1396 SOF_TIMESTAMPING_RX_HARDWARE |
1397 SOF_TIMESTAMPING_RAW_HARDWARE;
1398 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1399 info->tx_types =
1400 (1 << HWTSTAMP_TX_OFF) |
1401 (1 << HWTSTAMP_TX_ON) |
1402 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1403 info->rx_filters =
1404 (1 << HWTSTAMP_FILTER_NONE) |
1405 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1406 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1407 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1408 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1409 return 0;
1410 }
1411
dp83640_probe(struct phy_device * phydev)1412 static int dp83640_probe(struct phy_device *phydev)
1413 {
1414 struct dp83640_clock *clock;
1415 struct dp83640_private *dp83640;
1416 int err = -ENOMEM, i;
1417
1418 if (phydev->mdio.addr == BROADCAST_ADDR)
1419 return 0;
1420
1421 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1422 if (!clock)
1423 goto no_clock;
1424
1425 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1426 if (!dp83640)
1427 goto no_memory;
1428
1429 dp83640->phydev = phydev;
1430 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp;
1431 dp83640->mii_ts.txtstamp = dp83640_txtstamp;
1432 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp;
1433 dp83640->mii_ts.ts_info = dp83640_ts_info;
1434
1435 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1436 INIT_LIST_HEAD(&dp83640->rxts);
1437 INIT_LIST_HEAD(&dp83640->rxpool);
1438 for (i = 0; i < MAX_RXTS; i++)
1439 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1440
1441 phydev->mii_ts = &dp83640->mii_ts;
1442 phydev->priv = dp83640;
1443
1444 spin_lock_init(&dp83640->rx_lock);
1445 skb_queue_head_init(&dp83640->rx_queue);
1446 skb_queue_head_init(&dp83640->tx_queue);
1447
1448 dp83640->clock = clock;
1449
1450 if (choose_this_phy(clock, phydev)) {
1451 clock->chosen = dp83640;
1452 clock->ptp_clock = ptp_clock_register(&clock->caps,
1453 &phydev->mdio.dev);
1454 if (IS_ERR(clock->ptp_clock)) {
1455 err = PTR_ERR(clock->ptp_clock);
1456 goto no_register;
1457 }
1458 } else
1459 list_add_tail(&dp83640->list, &clock->phylist);
1460
1461 dp83640_clock_put(clock);
1462 return 0;
1463
1464 no_register:
1465 clock->chosen = NULL;
1466 kfree(dp83640);
1467 no_memory:
1468 dp83640_clock_put(clock);
1469 no_clock:
1470 return err;
1471 }
1472
dp83640_remove(struct phy_device * phydev)1473 static void dp83640_remove(struct phy_device *phydev)
1474 {
1475 struct dp83640_clock *clock;
1476 struct list_head *this, *next;
1477 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1478
1479 if (phydev->mdio.addr == BROADCAST_ADDR)
1480 return;
1481
1482 phydev->mii_ts = NULL;
1483
1484 enable_status_frames(phydev, false);
1485 cancel_delayed_work_sync(&dp83640->ts_work);
1486
1487 skb_queue_purge(&dp83640->rx_queue);
1488 skb_queue_purge(&dp83640->tx_queue);
1489
1490 clock = dp83640_clock_get(dp83640->clock);
1491
1492 if (dp83640 == clock->chosen) {
1493 ptp_clock_unregister(clock->ptp_clock);
1494 clock->chosen = NULL;
1495 } else {
1496 list_for_each_safe(this, next, &clock->phylist) {
1497 tmp = list_entry(this, struct dp83640_private, list);
1498 if (tmp == dp83640) {
1499 list_del_init(&tmp->list);
1500 break;
1501 }
1502 }
1503 }
1504
1505 dp83640_clock_put(clock);
1506 kfree(dp83640);
1507 }
1508
1509 static struct phy_driver dp83640_driver = {
1510 .phy_id = DP83640_PHY_ID,
1511 .phy_id_mask = 0xfffffff0,
1512 .name = "NatSemi DP83640",
1513 /* PHY_BASIC_FEATURES */
1514 .probe = dp83640_probe,
1515 .remove = dp83640_remove,
1516 .soft_reset = dp83640_soft_reset,
1517 .config_init = dp83640_config_init,
1518 .ack_interrupt = dp83640_ack_interrupt,
1519 .config_intr = dp83640_config_intr,
1520 };
1521
dp83640_init(void)1522 static int __init dp83640_init(void)
1523 {
1524 return phy_driver_register(&dp83640_driver, THIS_MODULE);
1525 }
1526
dp83640_exit(void)1527 static void __exit dp83640_exit(void)
1528 {
1529 dp83640_free_clocks();
1530 phy_driver_unregister(&dp83640_driver);
1531 }
1532
1533 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1534 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1535 MODULE_LICENSE("GPL");
1536
1537 module_init(dp83640_init);
1538 module_exit(dp83640_exit);
1539
1540 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1541 { DP83640_PHY_ID, 0xfffffff0 },
1542 { }
1543 };
1544
1545 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
1546