1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Freescale QUICC Engine HDLC Device Driver
3 *
4 * Copyright 2016 Freescale Semiconductor Inc.
5 */
6
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/hdlc.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/skbuff.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/stddef.h>
26 #include <soc/fsl/qe/qe_tdm.h>
27 #include <uapi/linux/if_arp.h>
28
29 #include "fsl_ucc_hdlc.h"
30
31 #define DRV_DESC "Freescale QE UCC HDLC Driver"
32 #define DRV_NAME "ucc_hdlc"
33
34 #define TDM_PPPOHT_SLIC_MAXIN
35 #define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S)
36
37 static int uhdlc_close(struct net_device *dev);
38
39 static struct ucc_tdm_info utdm_primary_info = {
40 .uf_info = {
41 .tsa = 0,
42 .cdp = 0,
43 .cds = 1,
44 .ctsp = 1,
45 .ctss = 1,
46 .revd = 0,
47 .urfs = 256,
48 .utfs = 256,
49 .urfet = 128,
50 .urfset = 192,
51 .utfet = 128,
52 .utftt = 0x40,
53 .ufpt = 256,
54 .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
55 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
56 .tenc = UCC_FAST_TX_ENCODING_NRZ,
57 .renc = UCC_FAST_RX_ENCODING_NRZ,
58 .tcrc = UCC_FAST_16_BIT_CRC,
59 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
60 },
61
62 .si_info = {
63 #ifdef TDM_PPPOHT_SLIC_MAXIN
64 .simr_rfsd = 1,
65 .simr_tfsd = 2,
66 #else
67 .simr_rfsd = 0,
68 .simr_tfsd = 0,
69 #endif
70 .simr_crt = 0,
71 .simr_sl = 0,
72 .simr_ce = 1,
73 .simr_fe = 1,
74 .simr_gm = 0,
75 },
76 };
77
78 static struct ucc_tdm_info utdm_info[UCC_MAX_NUM];
79
uhdlc_init(struct ucc_hdlc_private * priv)80 static int uhdlc_init(struct ucc_hdlc_private *priv)
81 {
82 struct ucc_tdm_info *ut_info;
83 struct ucc_fast_info *uf_info;
84 u32 cecr_subblock;
85 u16 bd_status;
86 int ret, i;
87 void *bd_buffer;
88 dma_addr_t bd_dma_addr;
89 s32 riptr;
90 s32 tiptr;
91 u32 gumr;
92
93 ut_info = priv->ut_info;
94 uf_info = &ut_info->uf_info;
95
96 if (priv->tsa) {
97 uf_info->tsa = 1;
98 uf_info->ctsp = 1;
99 uf_info->cds = 1;
100 uf_info->ctss = 1;
101 } else {
102 uf_info->cds = 0;
103 uf_info->ctsp = 0;
104 uf_info->ctss = 0;
105 }
106
107 /* This sets HPM register in CMXUCR register which configures a
108 * open drain connected HDLC bus
109 */
110 if (priv->hdlc_bus)
111 uf_info->brkpt_support = 1;
112
113 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
114 UCC_HDLC_UCCE_TXB) << 16);
115
116 ret = ucc_fast_init(uf_info, &priv->uccf);
117 if (ret) {
118 dev_err(priv->dev, "Failed to init uccf.");
119 return ret;
120 }
121
122 priv->uf_regs = priv->uccf->uf_regs;
123 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
124
125 /* Loopback mode */
126 if (priv->loopback) {
127 dev_info(priv->dev, "Loopback Mode\n");
128 /* use the same clock when work in loopback */
129 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
130
131 gumr = ioread32be(&priv->uf_regs->gumr);
132 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
133 UCC_FAST_GUMR_TCI);
134 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
135 iowrite32be(gumr, &priv->uf_regs->gumr);
136 }
137
138 /* Initialize SI */
139 if (priv->tsa)
140 ucc_tdm_init(priv->utdm, priv->ut_info);
141
142 /* Write to QE CECR, UCCx channel to Stop Transmission */
143 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
144 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
145 QE_CR_PROTOCOL_UNSPECIFIED, 0);
146
147 /* Set UPSMR normal mode (need fixed)*/
148 iowrite32be(0, &priv->uf_regs->upsmr);
149
150 /* hdlc_bus mode */
151 if (priv->hdlc_bus) {
152 u32 upsmr;
153
154 dev_info(priv->dev, "HDLC bus Mode\n");
155 upsmr = ioread32be(&priv->uf_regs->upsmr);
156
157 /* bus mode and retransmit enable, with collision window
158 * set to 8 bytes
159 */
160 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
161 UCC_HDLC_UPSMR_CW8;
162 iowrite32be(upsmr, &priv->uf_regs->upsmr);
163
164 /* explicitly disable CDS & CTSP */
165 gumr = ioread32be(&priv->uf_regs->gumr);
166 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
167 /* set automatic sync to explicitly ignore CD signal */
168 gumr |= UCC_FAST_GUMR_SYNL_AUTO;
169 iowrite32be(gumr, &priv->uf_regs->gumr);
170 }
171
172 priv->rx_ring_size = RX_BD_RING_LEN;
173 priv->tx_ring_size = TX_BD_RING_LEN;
174 /* Alloc Rx BD */
175 priv->rx_bd_base = dma_alloc_coherent(priv->dev,
176 RX_BD_RING_LEN * sizeof(struct qe_bd),
177 &priv->dma_rx_bd, GFP_KERNEL);
178
179 if (!priv->rx_bd_base) {
180 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
181 ret = -ENOMEM;
182 goto free_uccf;
183 }
184
185 /* Alloc Tx BD */
186 priv->tx_bd_base = dma_alloc_coherent(priv->dev,
187 TX_BD_RING_LEN * sizeof(struct qe_bd),
188 &priv->dma_tx_bd, GFP_KERNEL);
189
190 if (!priv->tx_bd_base) {
191 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
192 ret = -ENOMEM;
193 goto free_rx_bd;
194 }
195
196 /* Alloc parameter ram for ucc hdlc */
197 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
198 ALIGNMENT_OF_UCC_HDLC_PRAM);
199
200 if (priv->ucc_pram_offset < 0) {
201 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
202 ret = -ENOMEM;
203 goto free_tx_bd;
204 }
205
206 priv->rx_skbuff = kcalloc(priv->rx_ring_size,
207 sizeof(*priv->rx_skbuff),
208 GFP_KERNEL);
209 if (!priv->rx_skbuff) {
210 ret = -ENOMEM;
211 goto free_ucc_pram;
212 }
213
214 priv->tx_skbuff = kcalloc(priv->tx_ring_size,
215 sizeof(*priv->tx_skbuff),
216 GFP_KERNEL);
217 if (!priv->tx_skbuff) {
218 ret = -ENOMEM;
219 goto free_rx_skbuff;
220 }
221
222 priv->skb_curtx = 0;
223 priv->skb_dirtytx = 0;
224 priv->curtx_bd = priv->tx_bd_base;
225 priv->dirty_tx = priv->tx_bd_base;
226 priv->currx_bd = priv->rx_bd_base;
227 priv->currx_bdnum = 0;
228
229 /* init parameter base */
230 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
231 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
232 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
233
234 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
235 qe_muram_addr(priv->ucc_pram_offset);
236
237 /* Zero out parameter ram */
238 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
239
240 /* Alloc riptr, tiptr */
241 riptr = qe_muram_alloc(32, 32);
242 if (riptr < 0) {
243 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
244 ret = -ENOMEM;
245 goto free_tx_skbuff;
246 }
247
248 tiptr = qe_muram_alloc(32, 32);
249 if (tiptr < 0) {
250 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
251 ret = -ENOMEM;
252 goto free_riptr;
253 }
254 if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
255 dev_err(priv->dev, "MURAM allocation out of addressable range\n");
256 ret = -ENOMEM;
257 goto free_tiptr;
258 }
259
260 /* Set RIPTR, TIPTR */
261 iowrite16be(riptr, &priv->ucc_pram->riptr);
262 iowrite16be(tiptr, &priv->ucc_pram->tiptr);
263
264 /* Set MRBLR */
265 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
266
267 /* Set RBASE, TBASE */
268 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
269 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
270
271 /* Set RSTATE, TSTATE */
272 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
273 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
274
275 /* Set C_MASK, C_PRES for 16bit CRC */
276 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
277 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
278
279 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
280 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
281 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
282 iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
283 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
284 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
285 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
286 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
287
288 /* Get BD buffer */
289 bd_buffer = dma_alloc_coherent(priv->dev,
290 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
291 &bd_dma_addr, GFP_KERNEL);
292
293 if (!bd_buffer) {
294 dev_err(priv->dev, "Could not allocate buffer descriptors\n");
295 ret = -ENOMEM;
296 goto free_tiptr;
297 }
298
299 priv->rx_buffer = bd_buffer;
300 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
301
302 priv->dma_rx_addr = bd_dma_addr;
303 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
304
305 for (i = 0; i < RX_BD_RING_LEN; i++) {
306 if (i < (RX_BD_RING_LEN - 1))
307 bd_status = R_E_S | R_I_S;
308 else
309 bd_status = R_E_S | R_I_S | R_W_S;
310
311 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
312 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
313 &priv->rx_bd_base[i].buf);
314 }
315
316 for (i = 0; i < TX_BD_RING_LEN; i++) {
317 if (i < (TX_BD_RING_LEN - 1))
318 bd_status = T_I_S | T_TC_S;
319 else
320 bd_status = T_I_S | T_TC_S | T_W_S;
321
322 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
323 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
324 &priv->tx_bd_base[i].buf);
325 }
326
327 return 0;
328
329 free_tiptr:
330 qe_muram_free(tiptr);
331 free_riptr:
332 qe_muram_free(riptr);
333 free_tx_skbuff:
334 kfree(priv->tx_skbuff);
335 free_rx_skbuff:
336 kfree(priv->rx_skbuff);
337 free_ucc_pram:
338 qe_muram_free(priv->ucc_pram_offset);
339 free_tx_bd:
340 dma_free_coherent(priv->dev,
341 TX_BD_RING_LEN * sizeof(struct qe_bd),
342 priv->tx_bd_base, priv->dma_tx_bd);
343 free_rx_bd:
344 dma_free_coherent(priv->dev,
345 RX_BD_RING_LEN * sizeof(struct qe_bd),
346 priv->rx_bd_base, priv->dma_rx_bd);
347 free_uccf:
348 ucc_fast_free(priv->uccf);
349
350 return ret;
351 }
352
ucc_hdlc_tx(struct sk_buff * skb,struct net_device * dev)353 static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
354 {
355 hdlc_device *hdlc = dev_to_hdlc(dev);
356 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
357 struct qe_bd __iomem *bd;
358 u16 bd_status;
359 unsigned long flags;
360 u16 *proto_head;
361
362 switch (dev->type) {
363 case ARPHRD_RAWHDLC:
364 if (skb_headroom(skb) < HDLC_HEAD_LEN) {
365 dev->stats.tx_dropped++;
366 dev_kfree_skb(skb);
367 netdev_err(dev, "No enough space for hdlc head\n");
368 return -ENOMEM;
369 }
370
371 skb_push(skb, HDLC_HEAD_LEN);
372
373 proto_head = (u16 *)skb->data;
374 *proto_head = htons(DEFAULT_HDLC_HEAD);
375
376 dev->stats.tx_bytes += skb->len;
377 break;
378
379 case ARPHRD_PPP:
380 proto_head = (u16 *)skb->data;
381 if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
382 dev->stats.tx_dropped++;
383 dev_kfree_skb(skb);
384 netdev_err(dev, "Wrong ppp header\n");
385 return -ENOMEM;
386 }
387
388 dev->stats.tx_bytes += skb->len;
389 break;
390
391 case ARPHRD_ETHER:
392 dev->stats.tx_bytes += skb->len;
393 break;
394
395 default:
396 dev->stats.tx_dropped++;
397 dev_kfree_skb(skb);
398 return -ENOMEM;
399 }
400 netdev_sent_queue(dev, skb->len);
401 spin_lock_irqsave(&priv->lock, flags);
402
403 /* Start from the next BD that should be filled */
404 bd = priv->curtx_bd;
405 bd_status = ioread16be(&bd->status);
406 /* Save the skb pointer so we can free it later */
407 priv->tx_skbuff[priv->skb_curtx] = skb;
408
409 /* Update the current skb pointer (wrapping if this was the last) */
410 priv->skb_curtx =
411 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
412
413 /* copy skb data to tx buffer for sdma processing */
414 memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
415 skb->data, skb->len);
416
417 /* set bd status and length */
418 bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
419
420 iowrite16be(skb->len, &bd->length);
421 iowrite16be(bd_status, &bd->status);
422
423 /* Move to next BD in the ring */
424 if (!(bd_status & T_W_S))
425 bd += 1;
426 else
427 bd = priv->tx_bd_base;
428
429 if (bd == priv->dirty_tx) {
430 if (!netif_queue_stopped(dev))
431 netif_stop_queue(dev);
432 }
433
434 priv->curtx_bd = bd;
435
436 spin_unlock_irqrestore(&priv->lock, flags);
437
438 return NETDEV_TX_OK;
439 }
440
hdlc_tx_restart(struct ucc_hdlc_private * priv)441 static int hdlc_tx_restart(struct ucc_hdlc_private *priv)
442 {
443 u32 cecr_subblock;
444
445 cecr_subblock =
446 ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num);
447
448 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
449 QE_CR_PROTOCOL_UNSPECIFIED, 0);
450 return 0;
451 }
452
hdlc_tx_done(struct ucc_hdlc_private * priv)453 static int hdlc_tx_done(struct ucc_hdlc_private *priv)
454 {
455 /* Start from the next BD that should be filled */
456 struct net_device *dev = priv->ndev;
457 unsigned int bytes_sent = 0;
458 int howmany = 0;
459 struct qe_bd *bd; /* BD pointer */
460 u16 bd_status;
461 int tx_restart = 0;
462
463 bd = priv->dirty_tx;
464 bd_status = ioread16be(&bd->status);
465
466 /* Normal processing. */
467 while ((bd_status & T_R_S) == 0) {
468 struct sk_buff *skb;
469
470 if (bd_status & T_UN_S) { /* Underrun */
471 dev->stats.tx_fifo_errors++;
472 tx_restart = 1;
473 }
474 if (bd_status & T_CT_S) { /* Carrier lost */
475 dev->stats.tx_carrier_errors++;
476 tx_restart = 1;
477 }
478
479 /* BD contains already transmitted buffer. */
480 /* Handle the transmitted buffer and release */
481 /* the BD to be used with the current frame */
482
483 skb = priv->tx_skbuff[priv->skb_dirtytx];
484 if (!skb)
485 break;
486 howmany++;
487 bytes_sent += skb->len;
488 dev->stats.tx_packets++;
489 memset(priv->tx_buffer +
490 (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
491 0, skb->len);
492 dev_consume_skb_irq(skb);
493
494 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
495 priv->skb_dirtytx =
496 (priv->skb_dirtytx +
497 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
498
499 /* We freed a buffer, so now we can restart transmission */
500 if (netif_queue_stopped(dev))
501 netif_wake_queue(dev);
502
503 /* Advance the confirmation BD pointer */
504 if (!(bd_status & T_W_S))
505 bd += 1;
506 else
507 bd = priv->tx_bd_base;
508 bd_status = ioread16be(&bd->status);
509 }
510 priv->dirty_tx = bd;
511
512 if (tx_restart)
513 hdlc_tx_restart(priv);
514
515 netdev_completed_queue(dev, howmany, bytes_sent);
516 return 0;
517 }
518
hdlc_rx_done(struct ucc_hdlc_private * priv,int rx_work_limit)519 static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
520 {
521 struct net_device *dev = priv->ndev;
522 struct sk_buff *skb = NULL;
523 hdlc_device *hdlc = dev_to_hdlc(dev);
524 struct qe_bd *bd;
525 u16 bd_status;
526 u16 length, howmany = 0;
527 u8 *bdbuffer;
528
529 bd = priv->currx_bd;
530 bd_status = ioread16be(&bd->status);
531
532 /* while there are received buffers and BD is full (~R_E) */
533 while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
534 if (bd_status & (RX_BD_ERRORS)) {
535 dev->stats.rx_errors++;
536
537 if (bd_status & R_CD_S)
538 dev->stats.collisions++;
539 if (bd_status & R_OV_S)
540 dev->stats.rx_fifo_errors++;
541 if (bd_status & R_CR_S)
542 dev->stats.rx_crc_errors++;
543 if (bd_status & R_AB_S)
544 dev->stats.rx_over_errors++;
545 if (bd_status & R_NO_S)
546 dev->stats.rx_frame_errors++;
547 if (bd_status & R_LG_S)
548 dev->stats.rx_length_errors++;
549
550 goto recycle;
551 }
552 bdbuffer = priv->rx_buffer +
553 (priv->currx_bdnum * MAX_RX_BUF_LENGTH);
554 length = ioread16be(&bd->length);
555
556 switch (dev->type) {
557 case ARPHRD_RAWHDLC:
558 bdbuffer += HDLC_HEAD_LEN;
559 length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE);
560
561 skb = dev_alloc_skb(length);
562 if (!skb) {
563 dev->stats.rx_dropped++;
564 return -ENOMEM;
565 }
566
567 skb_put(skb, length);
568 skb->len = length;
569 skb->dev = dev;
570 memcpy(skb->data, bdbuffer, length);
571 break;
572
573 case ARPHRD_PPP:
574 case ARPHRD_ETHER:
575 length -= HDLC_CRC_SIZE;
576
577 skb = dev_alloc_skb(length);
578 if (!skb) {
579 dev->stats.rx_dropped++;
580 return -ENOMEM;
581 }
582
583 skb_put(skb, length);
584 skb->len = length;
585 skb->dev = dev;
586 memcpy(skb->data, bdbuffer, length);
587 break;
588 }
589
590 dev->stats.rx_packets++;
591 dev->stats.rx_bytes += skb->len;
592 howmany++;
593 if (hdlc->proto)
594 skb->protocol = hdlc_type_trans(skb, dev);
595 netif_receive_skb(skb);
596
597 recycle:
598 iowrite16be((bd_status & R_W_S) | R_E_S | R_I_S, &bd->status);
599
600 /* update to point at the next bd */
601 if (bd_status & R_W_S) {
602 priv->currx_bdnum = 0;
603 bd = priv->rx_bd_base;
604 } else {
605 if (priv->currx_bdnum < (RX_BD_RING_LEN - 1))
606 priv->currx_bdnum += 1;
607 else
608 priv->currx_bdnum = RX_BD_RING_LEN - 1;
609
610 bd += 1;
611 }
612
613 bd_status = ioread16be(&bd->status);
614 }
615
616 priv->currx_bd = bd;
617 return howmany;
618 }
619
ucc_hdlc_poll(struct napi_struct * napi,int budget)620 static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
621 {
622 struct ucc_hdlc_private *priv = container_of(napi,
623 struct ucc_hdlc_private,
624 napi);
625 int howmany;
626
627 /* Tx event processing */
628 spin_lock(&priv->lock);
629 hdlc_tx_done(priv);
630 spin_unlock(&priv->lock);
631
632 howmany = 0;
633 howmany += hdlc_rx_done(priv, budget - howmany);
634
635 if (howmany < budget) {
636 napi_complete_done(napi, howmany);
637 qe_setbits_be32(priv->uccf->p_uccm,
638 (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
639 }
640
641 return howmany;
642 }
643
ucc_hdlc_irq_handler(int irq,void * dev_id)644 static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
645 {
646 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
647 struct net_device *dev = priv->ndev;
648 struct ucc_fast_private *uccf;
649 u32 ucce;
650 u32 uccm;
651
652 uccf = priv->uccf;
653
654 ucce = ioread32be(uccf->p_ucce);
655 uccm = ioread32be(uccf->p_uccm);
656 ucce &= uccm;
657 iowrite32be(ucce, uccf->p_ucce);
658 if (!ucce)
659 return IRQ_NONE;
660
661 if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) {
662 if (napi_schedule_prep(&priv->napi)) {
663 uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)
664 << 16);
665 iowrite32be(uccm, uccf->p_uccm);
666 __napi_schedule(&priv->napi);
667 }
668 }
669
670 /* Errors and other events */
671 if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
672 dev->stats.rx_missed_errors++;
673 if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
674 dev->stats.tx_errors++;
675
676 return IRQ_HANDLED;
677 }
678
uhdlc_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)679 static int uhdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
680 {
681 const size_t size = sizeof(te1_settings);
682 te1_settings line;
683 struct ucc_hdlc_private *priv = netdev_priv(dev);
684
685 if (cmd != SIOCWANDEV)
686 return hdlc_ioctl(dev, ifr, cmd);
687
688 switch (ifr->ifr_settings.type) {
689 case IF_GET_IFACE:
690 ifr->ifr_settings.type = IF_IFACE_E1;
691 if (ifr->ifr_settings.size < size) {
692 ifr->ifr_settings.size = size; /* data size wanted */
693 return -ENOBUFS;
694 }
695 memset(&line, 0, sizeof(line));
696 line.clock_type = priv->clocking;
697
698 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
699 return -EFAULT;
700 return 0;
701
702 default:
703 return hdlc_ioctl(dev, ifr, cmd);
704 }
705 }
706
uhdlc_open(struct net_device * dev)707 static int uhdlc_open(struct net_device *dev)
708 {
709 u32 cecr_subblock;
710 hdlc_device *hdlc = dev_to_hdlc(dev);
711 struct ucc_hdlc_private *priv = hdlc->priv;
712 struct ucc_tdm *utdm = priv->utdm;
713 int rc = 0;
714
715 if (priv->hdlc_busy != 1) {
716 if (request_irq(priv->ut_info->uf_info.irq,
717 ucc_hdlc_irq_handler, 0, "hdlc", priv))
718 return -ENODEV;
719
720 cecr_subblock = ucc_fast_get_qe_cr_subblock(
721 priv->ut_info->uf_info.ucc_num);
722
723 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
724 QE_CR_PROTOCOL_UNSPECIFIED, 0);
725
726 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
727
728 /* Enable the TDM port */
729 if (priv->tsa)
730 utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
731
732 priv->hdlc_busy = 1;
733 netif_device_attach(priv->ndev);
734 napi_enable(&priv->napi);
735 netdev_reset_queue(dev);
736 netif_start_queue(dev);
737
738 rc = hdlc_open(dev);
739 if (rc)
740 uhdlc_close(dev);
741 }
742
743 return rc;
744 }
745
uhdlc_memclean(struct ucc_hdlc_private * priv)746 static void uhdlc_memclean(struct ucc_hdlc_private *priv)
747 {
748 qe_muram_free(ioread16be(&priv->ucc_pram->riptr));
749 qe_muram_free(ioread16be(&priv->ucc_pram->tiptr));
750
751 if (priv->rx_bd_base) {
752 dma_free_coherent(priv->dev,
753 RX_BD_RING_LEN * sizeof(struct qe_bd),
754 priv->rx_bd_base, priv->dma_rx_bd);
755
756 priv->rx_bd_base = NULL;
757 priv->dma_rx_bd = 0;
758 }
759
760 if (priv->tx_bd_base) {
761 dma_free_coherent(priv->dev,
762 TX_BD_RING_LEN * sizeof(struct qe_bd),
763 priv->tx_bd_base, priv->dma_tx_bd);
764
765 priv->tx_bd_base = NULL;
766 priv->dma_tx_bd = 0;
767 }
768
769 if (priv->ucc_pram) {
770 qe_muram_free(priv->ucc_pram_offset);
771 priv->ucc_pram = NULL;
772 priv->ucc_pram_offset = 0;
773 }
774
775 kfree(priv->rx_skbuff);
776 priv->rx_skbuff = NULL;
777
778 kfree(priv->tx_skbuff);
779 priv->tx_skbuff = NULL;
780
781 if (priv->uf_regs) {
782 iounmap(priv->uf_regs);
783 priv->uf_regs = NULL;
784 }
785
786 if (priv->uccf) {
787 ucc_fast_free(priv->uccf);
788 priv->uccf = NULL;
789 }
790
791 if (priv->rx_buffer) {
792 dma_free_coherent(priv->dev,
793 RX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
794 priv->rx_buffer, priv->dma_rx_addr);
795 priv->rx_buffer = NULL;
796 priv->dma_rx_addr = 0;
797 }
798
799 if (priv->tx_buffer) {
800 dma_free_coherent(priv->dev,
801 TX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
802 priv->tx_buffer, priv->dma_tx_addr);
803 priv->tx_buffer = NULL;
804 priv->dma_tx_addr = 0;
805 }
806 }
807
uhdlc_close(struct net_device * dev)808 static int uhdlc_close(struct net_device *dev)
809 {
810 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
811 struct ucc_tdm *utdm = priv->utdm;
812 u32 cecr_subblock;
813
814 napi_disable(&priv->napi);
815 cecr_subblock = ucc_fast_get_qe_cr_subblock(
816 priv->ut_info->uf_info.ucc_num);
817
818 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
819 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
820 qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
821 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
822
823 if (priv->tsa)
824 utdm->si_regs->siglmr1_h &= ~(0x1 << utdm->tdm_port);
825
826 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
827
828 free_irq(priv->ut_info->uf_info.irq, priv);
829 netif_stop_queue(dev);
830 netdev_reset_queue(dev);
831 priv->hdlc_busy = 0;
832
833 hdlc_close(dev);
834
835 return 0;
836 }
837
ucc_hdlc_attach(struct net_device * dev,unsigned short encoding,unsigned short parity)838 static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding,
839 unsigned short parity)
840 {
841 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
842
843 if (encoding != ENCODING_NRZ &&
844 encoding != ENCODING_NRZI)
845 return -EINVAL;
846
847 if (parity != PARITY_NONE &&
848 parity != PARITY_CRC32_PR1_CCITT &&
849 parity != PARITY_CRC16_PR0_CCITT &&
850 parity != PARITY_CRC16_PR1_CCITT)
851 return -EINVAL;
852
853 priv->encoding = encoding;
854 priv->parity = parity;
855
856 return 0;
857 }
858
859 #ifdef CONFIG_PM
store_clk_config(struct ucc_hdlc_private * priv)860 static void store_clk_config(struct ucc_hdlc_private *priv)
861 {
862 struct qe_mux *qe_mux_reg = &qe_immr->qmx;
863
864 /* store si clk */
865 priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
866 priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
867
868 /* store si sync */
869 priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
870
871 /* store ucc clk */
872 memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
873 }
874
resume_clk_config(struct ucc_hdlc_private * priv)875 static void resume_clk_config(struct ucc_hdlc_private *priv)
876 {
877 struct qe_mux *qe_mux_reg = &qe_immr->qmx;
878
879 memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
880
881 iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
882 iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
883
884 iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
885 }
886
uhdlc_suspend(struct device * dev)887 static int uhdlc_suspend(struct device *dev)
888 {
889 struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
890 struct ucc_fast __iomem *uf_regs;
891
892 if (!priv)
893 return -EINVAL;
894
895 if (!netif_running(priv->ndev))
896 return 0;
897
898 netif_device_detach(priv->ndev);
899 napi_disable(&priv->napi);
900
901 uf_regs = priv->uf_regs;
902
903 /* backup gumr guemr*/
904 priv->gumr = ioread32be(&uf_regs->gumr);
905 priv->guemr = ioread8(&uf_regs->guemr);
906
907 priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak),
908 GFP_KERNEL);
909 if (!priv->ucc_pram_bak)
910 return -ENOMEM;
911
912 /* backup HDLC parameter */
913 memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram,
914 sizeof(struct ucc_hdlc_param));
915
916 /* store the clk configuration */
917 store_clk_config(priv);
918
919 /* save power */
920 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
921
922 return 0;
923 }
924
uhdlc_resume(struct device * dev)925 static int uhdlc_resume(struct device *dev)
926 {
927 struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
928 struct ucc_tdm *utdm;
929 struct ucc_tdm_info *ut_info;
930 struct ucc_fast __iomem *uf_regs;
931 struct ucc_fast_private *uccf;
932 struct ucc_fast_info *uf_info;
933 int i;
934 u32 cecr_subblock;
935 u16 bd_status;
936
937 if (!priv)
938 return -EINVAL;
939
940 if (!netif_running(priv->ndev))
941 return 0;
942
943 utdm = priv->utdm;
944 ut_info = priv->ut_info;
945 uf_info = &ut_info->uf_info;
946 uf_regs = priv->uf_regs;
947 uccf = priv->uccf;
948
949 /* restore gumr guemr */
950 iowrite8(priv->guemr, &uf_regs->guemr);
951 iowrite32be(priv->gumr, &uf_regs->gumr);
952
953 /* Set Virtual Fifo registers */
954 iowrite16be(uf_info->urfs, &uf_regs->urfs);
955 iowrite16be(uf_info->urfet, &uf_regs->urfet);
956 iowrite16be(uf_info->urfset, &uf_regs->urfset);
957 iowrite16be(uf_info->utfs, &uf_regs->utfs);
958 iowrite16be(uf_info->utfet, &uf_regs->utfet);
959 iowrite16be(uf_info->utftt, &uf_regs->utftt);
960 /* utfb, urfb are offsets from MURAM base */
961 iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
962 iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
963
964 /* Rx Tx and sync clock routing */
965 resume_clk_config(priv);
966
967 iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
968 iowrite32be(0xffffffff, &uf_regs->ucce);
969
970 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
971
972 /* rebuild SIRAM */
973 if (priv->tsa)
974 ucc_tdm_init(priv->utdm, priv->ut_info);
975
976 /* Write to QE CECR, UCCx channel to Stop Transmission */
977 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
978 qe_issue_cmd(QE_STOP_TX, cecr_subblock,
979 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
980
981 /* Set UPSMR normal mode */
982 iowrite32be(0, &uf_regs->upsmr);
983
984 /* init parameter base */
985 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
986 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
987 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
988
989 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
990 qe_muram_addr(priv->ucc_pram_offset);
991
992 /* restore ucc parameter */
993 memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak,
994 sizeof(struct ucc_hdlc_param));
995 kfree(priv->ucc_pram_bak);
996
997 /* rebuild BD entry */
998 for (i = 0; i < RX_BD_RING_LEN; i++) {
999 if (i < (RX_BD_RING_LEN - 1))
1000 bd_status = R_E_S | R_I_S;
1001 else
1002 bd_status = R_E_S | R_I_S | R_W_S;
1003
1004 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
1005 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
1006 &priv->rx_bd_base[i].buf);
1007 }
1008
1009 for (i = 0; i < TX_BD_RING_LEN; i++) {
1010 if (i < (TX_BD_RING_LEN - 1))
1011 bd_status = T_I_S | T_TC_S;
1012 else
1013 bd_status = T_I_S | T_TC_S | T_W_S;
1014
1015 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
1016 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
1017 &priv->tx_bd_base[i].buf);
1018 }
1019
1020 /* if hdlc is busy enable TX and RX */
1021 if (priv->hdlc_busy == 1) {
1022 cecr_subblock = ucc_fast_get_qe_cr_subblock(
1023 priv->ut_info->uf_info.ucc_num);
1024
1025 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
1026 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
1027
1028 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
1029
1030 /* Enable the TDM port */
1031 if (priv->tsa)
1032 utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port);
1033 }
1034
1035 napi_enable(&priv->napi);
1036 netif_device_attach(priv->ndev);
1037
1038 return 0;
1039 }
1040
1041 static const struct dev_pm_ops uhdlc_pm_ops = {
1042 .suspend = uhdlc_suspend,
1043 .resume = uhdlc_resume,
1044 .freeze = uhdlc_suspend,
1045 .thaw = uhdlc_resume,
1046 };
1047
1048 #define HDLC_PM_OPS (&uhdlc_pm_ops)
1049
1050 #else
1051
1052 #define HDLC_PM_OPS NULL
1053
1054 #endif
uhdlc_tx_timeout(struct net_device * ndev,unsigned int txqueue)1055 static void uhdlc_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1056 {
1057 netdev_err(ndev, "%s\n", __func__);
1058 }
1059
1060 static const struct net_device_ops uhdlc_ops = {
1061 .ndo_open = uhdlc_open,
1062 .ndo_stop = uhdlc_close,
1063 .ndo_start_xmit = hdlc_start_xmit,
1064 .ndo_do_ioctl = uhdlc_ioctl,
1065 .ndo_tx_timeout = uhdlc_tx_timeout,
1066 };
1067
hdlc_map_iomem(char * name,int init_flag,void __iomem ** ptr)1068 static int hdlc_map_iomem(char *name, int init_flag, void __iomem **ptr)
1069 {
1070 struct device_node *np;
1071 struct platform_device *pdev;
1072 struct resource *res;
1073 static int siram_init_flag;
1074 int ret = 0;
1075
1076 np = of_find_compatible_node(NULL, NULL, name);
1077 if (!np)
1078 return -EINVAL;
1079
1080 pdev = of_find_device_by_node(np);
1081 if (!pdev) {
1082 pr_err("%pOFn: failed to lookup pdev\n", np);
1083 of_node_put(np);
1084 return -EINVAL;
1085 }
1086
1087 of_node_put(np);
1088 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089 if (!res) {
1090 ret = -EINVAL;
1091 goto error_put_device;
1092 }
1093 *ptr = ioremap(res->start, resource_size(res));
1094 if (!*ptr) {
1095 ret = -ENOMEM;
1096 goto error_put_device;
1097 }
1098
1099 /* We've remapped the addresses, and we don't need the device any
1100 * more, so we should release it.
1101 */
1102 put_device(&pdev->dev);
1103
1104 if (init_flag && siram_init_flag == 0) {
1105 memset_io(*ptr, 0, resource_size(res));
1106 siram_init_flag = 1;
1107 }
1108 return 0;
1109
1110 error_put_device:
1111 put_device(&pdev->dev);
1112
1113 return ret;
1114 }
1115
ucc_hdlc_probe(struct platform_device * pdev)1116 static int ucc_hdlc_probe(struct platform_device *pdev)
1117 {
1118 struct device_node *np = pdev->dev.of_node;
1119 struct ucc_hdlc_private *uhdlc_priv = NULL;
1120 struct ucc_tdm_info *ut_info;
1121 struct ucc_tdm *utdm = NULL;
1122 struct resource res;
1123 struct net_device *dev;
1124 hdlc_device *hdlc;
1125 int ucc_num;
1126 const char *sprop;
1127 int ret;
1128 u32 val;
1129
1130 ret = of_property_read_u32_index(np, "cell-index", 0, &val);
1131 if (ret) {
1132 dev_err(&pdev->dev, "Invalid ucc property\n");
1133 return -ENODEV;
1134 }
1135
1136 ucc_num = val - 1;
1137 if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) {
1138 dev_err(&pdev->dev, ": Invalid UCC num\n");
1139 return -EINVAL;
1140 }
1141
1142 memcpy(&utdm_info[ucc_num], &utdm_primary_info,
1143 sizeof(utdm_primary_info));
1144
1145 ut_info = &utdm_info[ucc_num];
1146 ut_info->uf_info.ucc_num = ucc_num;
1147
1148 sprop = of_get_property(np, "rx-clock-name", NULL);
1149 if (sprop) {
1150 ut_info->uf_info.rx_clock = qe_clock_source(sprop);
1151 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) ||
1152 (ut_info->uf_info.rx_clock > QE_CLK24)) {
1153 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1154 return -EINVAL;
1155 }
1156 } else {
1157 dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1158 return -EINVAL;
1159 }
1160
1161 sprop = of_get_property(np, "tx-clock-name", NULL);
1162 if (sprop) {
1163 ut_info->uf_info.tx_clock = qe_clock_source(sprop);
1164 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) ||
1165 (ut_info->uf_info.tx_clock > QE_CLK24)) {
1166 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1167 return -EINVAL;
1168 }
1169 } else {
1170 dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1171 return -EINVAL;
1172 }
1173
1174 ret = of_address_to_resource(np, 0, &res);
1175 if (ret)
1176 return -EINVAL;
1177
1178 ut_info->uf_info.regs = res.start;
1179 ut_info->uf_info.irq = irq_of_parse_and_map(np, 0);
1180
1181 uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL);
1182 if (!uhdlc_priv) {
1183 return -ENOMEM;
1184 }
1185
1186 dev_set_drvdata(&pdev->dev, uhdlc_priv);
1187 uhdlc_priv->dev = &pdev->dev;
1188 uhdlc_priv->ut_info = ut_info;
1189
1190 if (of_get_property(np, "fsl,tdm-interface", NULL))
1191 uhdlc_priv->tsa = 1;
1192
1193 if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
1194 uhdlc_priv->loopback = 1;
1195
1196 if (of_get_property(np, "fsl,hdlc-bus", NULL))
1197 uhdlc_priv->hdlc_bus = 1;
1198
1199 if (uhdlc_priv->tsa == 1) {
1200 utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
1201 if (!utdm) {
1202 ret = -ENOMEM;
1203 dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n");
1204 goto free_uhdlc_priv;
1205 }
1206 uhdlc_priv->utdm = utdm;
1207 ret = ucc_of_parse_tdm(np, utdm, ut_info);
1208 if (ret)
1209 goto free_utdm;
1210
1211 ret = hdlc_map_iomem("fsl,t1040-qe-si", 0,
1212 (void __iomem **)&utdm->si_regs);
1213 if (ret)
1214 goto free_utdm;
1215 ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1,
1216 (void __iomem **)&utdm->siram);
1217 if (ret)
1218 goto unmap_si_regs;
1219 }
1220
1221 if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask))
1222 uhdlc_priv->hmask = DEFAULT_ADDR_MASK;
1223
1224 ret = uhdlc_init(uhdlc_priv);
1225 if (ret) {
1226 dev_err(&pdev->dev, "Failed to init uhdlc\n");
1227 goto undo_uhdlc_init;
1228 }
1229
1230 dev = alloc_hdlcdev(uhdlc_priv);
1231 if (!dev) {
1232 ret = -ENOMEM;
1233 pr_err("ucc_hdlc: unable to allocate memory\n");
1234 goto undo_uhdlc_init;
1235 }
1236
1237 uhdlc_priv->ndev = dev;
1238 hdlc = dev_to_hdlc(dev);
1239 dev->tx_queue_len = 16;
1240 dev->netdev_ops = &uhdlc_ops;
1241 dev->watchdog_timeo = 2 * HZ;
1242 hdlc->attach = ucc_hdlc_attach;
1243 hdlc->xmit = ucc_hdlc_tx;
1244 netif_napi_add(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
1245 if (register_hdlc_device(dev)) {
1246 ret = -ENOBUFS;
1247 pr_err("ucc_hdlc: unable to register hdlc device\n");
1248 goto free_dev;
1249 }
1250
1251 return 0;
1252
1253 free_dev:
1254 free_netdev(dev);
1255 undo_uhdlc_init:
1256 if (utdm)
1257 iounmap(utdm->siram);
1258 unmap_si_regs:
1259 if (utdm)
1260 iounmap(utdm->si_regs);
1261 free_utdm:
1262 if (uhdlc_priv->tsa)
1263 kfree(utdm);
1264 free_uhdlc_priv:
1265 kfree(uhdlc_priv);
1266 return ret;
1267 }
1268
ucc_hdlc_remove(struct platform_device * pdev)1269 static int ucc_hdlc_remove(struct platform_device *pdev)
1270 {
1271 struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev);
1272
1273 uhdlc_memclean(priv);
1274
1275 if (priv->utdm->si_regs) {
1276 iounmap(priv->utdm->si_regs);
1277 priv->utdm->si_regs = NULL;
1278 }
1279
1280 if (priv->utdm->siram) {
1281 iounmap(priv->utdm->siram);
1282 priv->utdm->siram = NULL;
1283 }
1284 kfree(priv);
1285
1286 dev_info(&pdev->dev, "UCC based hdlc module removed\n");
1287
1288 return 0;
1289 }
1290
1291 static const struct of_device_id fsl_ucc_hdlc_of_match[] = {
1292 {
1293 .compatible = "fsl,ucc-hdlc",
1294 },
1295 {},
1296 };
1297
1298 MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);
1299
1300 static struct platform_driver ucc_hdlc_driver = {
1301 .probe = ucc_hdlc_probe,
1302 .remove = ucc_hdlc_remove,
1303 .driver = {
1304 .name = DRV_NAME,
1305 .pm = HDLC_PM_OPS,
1306 .of_match_table = fsl_ucc_hdlc_of_match,
1307 },
1308 };
1309
1310 module_platform_driver(ucc_hdlc_driver);
1311 MODULE_LICENSE("GPL");
1312 MODULE_DESCRIPTION(DRV_DESC);
1313