1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include "main.h"
6 #include "regd.h"
7 #include "fw.h"
8 #include "ps.h"
9 #include "sec.h"
10 #include "mac.h"
11 #include "coex.h"
12 #include "phy.h"
13 #include "reg.h"
14 #include "efuse.h"
15 #include "tx.h"
16 #include "debug.h"
17 #include "bf.h"
18
19 unsigned int rtw_fw_lps_deep_mode;
20 EXPORT_SYMBOL(rtw_fw_lps_deep_mode);
21 bool rtw_bf_support = true;
22 unsigned int rtw_debug_mask;
23 EXPORT_SYMBOL(rtw_debug_mask);
24
25 module_param_named(lps_deep_mode, rtw_fw_lps_deep_mode, uint, 0644);
26 module_param_named(support_bf, rtw_bf_support, bool, 0644);
27 module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
28
29 MODULE_PARM_DESC(lps_deep_mode, "Deeper PS mode. If 0, deep PS is disabled");
30 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
31 MODULE_PARM_DESC(debug_mask, "Debugging mask");
32
33 static struct ieee80211_channel rtw_channeltable_2g[] = {
34 {.center_freq = 2412, .hw_value = 1,},
35 {.center_freq = 2417, .hw_value = 2,},
36 {.center_freq = 2422, .hw_value = 3,},
37 {.center_freq = 2427, .hw_value = 4,},
38 {.center_freq = 2432, .hw_value = 5,},
39 {.center_freq = 2437, .hw_value = 6,},
40 {.center_freq = 2442, .hw_value = 7,},
41 {.center_freq = 2447, .hw_value = 8,},
42 {.center_freq = 2452, .hw_value = 9,},
43 {.center_freq = 2457, .hw_value = 10,},
44 {.center_freq = 2462, .hw_value = 11,},
45 {.center_freq = 2467, .hw_value = 12,},
46 {.center_freq = 2472, .hw_value = 13,},
47 {.center_freq = 2484, .hw_value = 14,},
48 };
49
50 static struct ieee80211_channel rtw_channeltable_5g[] = {
51 {.center_freq = 5180, .hw_value = 36,},
52 {.center_freq = 5200, .hw_value = 40,},
53 {.center_freq = 5220, .hw_value = 44,},
54 {.center_freq = 5240, .hw_value = 48,},
55 {.center_freq = 5260, .hw_value = 52,},
56 {.center_freq = 5280, .hw_value = 56,},
57 {.center_freq = 5300, .hw_value = 60,},
58 {.center_freq = 5320, .hw_value = 64,},
59 {.center_freq = 5500, .hw_value = 100,},
60 {.center_freq = 5520, .hw_value = 104,},
61 {.center_freq = 5540, .hw_value = 108,},
62 {.center_freq = 5560, .hw_value = 112,},
63 {.center_freq = 5580, .hw_value = 116,},
64 {.center_freq = 5600, .hw_value = 120,},
65 {.center_freq = 5620, .hw_value = 124,},
66 {.center_freq = 5640, .hw_value = 128,},
67 {.center_freq = 5660, .hw_value = 132,},
68 {.center_freq = 5680, .hw_value = 136,},
69 {.center_freq = 5700, .hw_value = 140,},
70 {.center_freq = 5745, .hw_value = 149,},
71 {.center_freq = 5765, .hw_value = 153,},
72 {.center_freq = 5785, .hw_value = 157,},
73 {.center_freq = 5805, .hw_value = 161,},
74 {.center_freq = 5825, .hw_value = 165,
75 .flags = IEEE80211_CHAN_NO_HT40MINUS},
76 };
77
78 static struct ieee80211_rate rtw_ratetable[] = {
79 {.bitrate = 10, .hw_value = 0x00,},
80 {.bitrate = 20, .hw_value = 0x01,},
81 {.bitrate = 55, .hw_value = 0x02,},
82 {.bitrate = 110, .hw_value = 0x03,},
83 {.bitrate = 60, .hw_value = 0x04,},
84 {.bitrate = 90, .hw_value = 0x05,},
85 {.bitrate = 120, .hw_value = 0x06,},
86 {.bitrate = 180, .hw_value = 0x07,},
87 {.bitrate = 240, .hw_value = 0x08,},
88 {.bitrate = 360, .hw_value = 0x09,},
89 {.bitrate = 480, .hw_value = 0x0a,},
90 {.bitrate = 540, .hw_value = 0x0b,},
91 };
92
rtw_desc_to_bitrate(u8 desc_rate)93 u16 rtw_desc_to_bitrate(u8 desc_rate)
94 {
95 struct ieee80211_rate rate;
96
97 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
98 return 0;
99
100 rate = rtw_ratetable[desc_rate];
101
102 return rate.bitrate;
103 }
104
105 static struct ieee80211_supported_band rtw_band_2ghz = {
106 .band = NL80211_BAND_2GHZ,
107
108 .channels = rtw_channeltable_2g,
109 .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
110
111 .bitrates = rtw_ratetable,
112 .n_bitrates = ARRAY_SIZE(rtw_ratetable),
113
114 .ht_cap = {0},
115 .vht_cap = {0},
116 };
117
118 static struct ieee80211_supported_band rtw_band_5ghz = {
119 .band = NL80211_BAND_5GHZ,
120
121 .channels = rtw_channeltable_5g,
122 .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
123
124 /* 5G has no CCK rates */
125 .bitrates = rtw_ratetable + 4,
126 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
127
128 .ht_cap = {0},
129 .vht_cap = {0},
130 };
131
132 struct rtw_watch_dog_iter_data {
133 struct rtw_dev *rtwdev;
134 struct rtw_vif *rtwvif;
135 };
136
rtw_dynamic_csi_rate(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif)137 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
138 {
139 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
140 u8 fix_rate_enable = 0;
141 u8 new_csi_rate_idx;
142
143 if (rtwvif->bfee.role != RTW_BFEE_SU &&
144 rtwvif->bfee.role != RTW_BFEE_MU)
145 return;
146
147 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
148 bf_info->cur_csi_rpt_rate,
149 fix_rate_enable, &new_csi_rate_idx);
150
151 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
152 bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
153 }
154
rtw_vif_watch_dog_iter(void * data,u8 * mac,struct ieee80211_vif * vif)155 static void rtw_vif_watch_dog_iter(void *data, u8 *mac,
156 struct ieee80211_vif *vif)
157 {
158 struct rtw_watch_dog_iter_data *iter_data = data;
159 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
160
161 if (vif->type == NL80211_IFTYPE_STATION)
162 if (vif->bss_conf.assoc)
163 iter_data->rtwvif = rtwvif;
164
165 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
166
167 rtwvif->stats.tx_unicast = 0;
168 rtwvif->stats.rx_unicast = 0;
169 rtwvif->stats.tx_cnt = 0;
170 rtwvif->stats.rx_cnt = 0;
171 }
172
173 /* process TX/RX statistics periodically for hardware,
174 * the information helps hardware to enhance performance
175 */
rtw_watch_dog_work(struct work_struct * work)176 static void rtw_watch_dog_work(struct work_struct *work)
177 {
178 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
179 watch_dog_work.work);
180 struct rtw_traffic_stats *stats = &rtwdev->stats;
181 struct rtw_watch_dog_iter_data data = {};
182 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
183 bool ps_active;
184
185 mutex_lock(&rtwdev->mutex);
186
187 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
188 goto unlock;
189
190 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
191 RTW_WATCH_DOG_DELAY_TIME);
192
193 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
194 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
195 else
196 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
197
198 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
199 rtw_coex_wl_status_change_notify(rtwdev);
200
201 if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
202 stats->rx_cnt > RTW_LPS_THRESHOLD)
203 ps_active = true;
204 else
205 ps_active = false;
206
207 ewma_tp_add(&stats->tx_ewma_tp,
208 (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
209 ewma_tp_add(&stats->rx_ewma_tp,
210 (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
211 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
212 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
213
214 /* reset tx/rx statictics */
215 stats->tx_unicast = 0;
216 stats->rx_unicast = 0;
217 stats->tx_cnt = 0;
218 stats->rx_cnt = 0;
219
220 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
221 goto unlock;
222
223 /* make sure BB/RF is working for dynamic mech */
224 rtw_leave_lps(rtwdev);
225
226 rtw_phy_dynamic_mechanism(rtwdev);
227
228 data.rtwdev = rtwdev;
229 /* use atomic version to avoid taking local->iflist_mtx mutex */
230 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data);
231
232 /* fw supports only one station associated to enter lps, if there are
233 * more than two stations associated to the AP, then we can not enter
234 * lps, because fw does not handle the overlapped beacon interval
235 *
236 * mac80211 should iterate vifs and determine if driver can enter
237 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to
238 * get that vif and check if device is having traffic more than the
239 * threshold.
240 */
241 if (rtwdev->ps_enabled && data.rtwvif && !ps_active)
242 rtw_enter_lps(rtwdev, data.rtwvif->port);
243
244 rtwdev->watch_dog_cnt++;
245
246 unlock:
247 mutex_unlock(&rtwdev->mutex);
248 }
249
rtw_c2h_work(struct work_struct * work)250 static void rtw_c2h_work(struct work_struct *work)
251 {
252 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
253 struct sk_buff *skb, *tmp;
254
255 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
256 skb_unlink(skb, &rtwdev->c2h_queue);
257 rtw_fw_c2h_cmd_handle(rtwdev, skb);
258 dev_kfree_skb_any(skb);
259 }
260 }
261
rtw_acquire_macid(struct rtw_dev * rtwdev)262 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
263 {
264 unsigned long mac_id;
265
266 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
267 if (mac_id < RTW_MAX_MAC_ID_NUM)
268 set_bit(mac_id, rtwdev->mac_id_map);
269
270 return mac_id;
271 }
272
rtw_sta_add(struct rtw_dev * rtwdev,struct ieee80211_sta * sta,struct ieee80211_vif * vif)273 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
274 struct ieee80211_vif *vif)
275 {
276 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
277 int i;
278
279 si->mac_id = rtw_acquire_macid(rtwdev);
280 if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
281 return -ENOSPC;
282
283 si->sta = sta;
284 si->vif = vif;
285 si->init_ra_lv = 1;
286 ewma_rssi_init(&si->avg_rssi);
287 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
288 rtw_txq_init(rtwdev, sta->txq[i]);
289
290 rtw_update_sta_info(rtwdev, si);
291 rtw_fw_media_status_report(rtwdev, si->mac_id, true);
292
293 rtwdev->sta_cnt++;
294 rtw_info(rtwdev, "sta %pM joined with macid %d\n",
295 sta->addr, si->mac_id);
296
297 return 0;
298 }
299
rtw_sta_remove(struct rtw_dev * rtwdev,struct ieee80211_sta * sta,bool fw_exist)300 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
301 bool fw_exist)
302 {
303 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
304 int i;
305
306 rtw_release_macid(rtwdev, si->mac_id);
307 if (fw_exist)
308 rtw_fw_media_status_report(rtwdev, si->mac_id, false);
309
310 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
311 rtw_txq_cleanup(rtwdev, sta->txq[i]);
312
313 kfree(si->mask);
314
315 rtwdev->sta_cnt--;
316 rtw_info(rtwdev, "sta %pM with macid %d left\n",
317 sta->addr, si->mac_id);
318 }
319
rtw_fw_dump_crash_log(struct rtw_dev * rtwdev)320 static bool rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
321 {
322 u32 size = rtwdev->chip->fw_rxff_size;
323 u32 *buf;
324 u8 seq;
325 bool ret = true;
326
327 buf = vmalloc(size);
328 if (!buf)
329 goto exit;
330
331 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
332 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
333 goto free_buf;
334 }
335
336 if (GET_FW_DUMP_LEN(buf) == 0) {
337 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
338 goto free_buf;
339 }
340
341 seq = GET_FW_DUMP_SEQ(buf);
342 if (seq > 0 && seq != (rtwdev->fw.prev_dump_seq + 1)) {
343 rtw_dbg(rtwdev, RTW_DBG_FW,
344 "fw crash dump's seq is wrong: %d\n", seq);
345 goto free_buf;
346 }
347 if (seq == 0 &&
348 (GET_FW_DUMP_TLV_TYPE(buf) != FW_CD_TYPE ||
349 GET_FW_DUMP_TLV_LEN(buf) != FW_CD_LEN ||
350 GET_FW_DUMP_TLV_VAL(buf) != FW_CD_VAL)) {
351 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's tlv is wrong\n");
352 goto free_buf;
353 }
354
355 print_hex_dump_bytes("rtw88 fw dump: ", DUMP_PREFIX_OFFSET, buf, size);
356
357 if (GET_FW_DUMP_MORE(buf) == 1) {
358 rtwdev->fw.prev_dump_seq = seq;
359 ret = false;
360 }
361
362 free_buf:
363 vfree(buf);
364 exit:
365 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
366
367 return ret;
368 }
369
rtw_vif_assoc_changed(struct rtw_vif * rtwvif,struct ieee80211_bss_conf * conf)370 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
371 struct ieee80211_bss_conf *conf)
372 {
373 if (conf && conf->assoc) {
374 rtwvif->aid = conf->aid;
375 rtwvif->net_type = RTW_NET_MGD_LINKED;
376 } else {
377 rtwvif->aid = 0;
378 rtwvif->net_type = RTW_NET_NO_LINK;
379 }
380 }
381
rtw_reset_key_iter(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key,void * data)382 static void rtw_reset_key_iter(struct ieee80211_hw *hw,
383 struct ieee80211_vif *vif,
384 struct ieee80211_sta *sta,
385 struct ieee80211_key_conf *key,
386 void *data)
387 {
388 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
389 struct rtw_sec_desc *sec = &rtwdev->sec;
390
391 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
392 }
393
rtw_reset_sta_iter(void * data,struct ieee80211_sta * sta)394 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
395 {
396 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
397
398 if (rtwdev->sta_cnt == 0) {
399 rtw_warn(rtwdev, "sta count before reset should not be 0\n");
400 return;
401 }
402 rtw_sta_remove(rtwdev, sta, false);
403 }
404
rtw_reset_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)405 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
406 {
407 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
408 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
409
410 rtw_bf_disassoc(rtwdev, vif, NULL);
411 rtw_vif_assoc_changed(rtwvif, NULL);
412 rtw_txq_cleanup(rtwdev, vif->txq);
413 }
414
rtw_fw_recovery(struct rtw_dev * rtwdev)415 void rtw_fw_recovery(struct rtw_dev *rtwdev)
416 {
417 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
418 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
419 }
420
rtw_fw_recovery_work(struct work_struct * work)421 static void rtw_fw_recovery_work(struct work_struct *work)
422 {
423 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
424 fw_recovery_work);
425
426 /* rtw_fw_dump_crash_log() returns false indicates that there are
427 * still more log to dump. Driver set 0x1cf[7:0] = 0x1 to tell firmware
428 * to dump the remaining part of the log, and firmware will trigger an
429 * IMR_C2HCMD interrupt to inform driver the log is ready.
430 */
431 if (!rtw_fw_dump_crash_log(rtwdev)) {
432 rtw_write8(rtwdev, REG_HRCV_MSG, 1);
433 return;
434 }
435 rtwdev->fw.prev_dump_seq = 0;
436
437 WARN(1, "firmware crash, start reset and recover\n");
438
439 mutex_lock(&rtwdev->mutex);
440
441 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
442 rcu_read_lock();
443 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
444 rcu_read_unlock();
445 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
446 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
447 rtw_enter_ips(rtwdev);
448
449 mutex_unlock(&rtwdev->mutex);
450
451 ieee80211_restart_hw(rtwdev->hw);
452 }
453
454 struct rtw_txq_ba_iter_data {
455 };
456
rtw_txq_ba_iter(void * data,struct ieee80211_sta * sta)457 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
458 {
459 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
460 int ret;
461 u8 tid;
462
463 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
464 while (tid != IEEE80211_NUM_TIDS) {
465 clear_bit(tid, si->tid_ba);
466 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
467 if (ret == -EINVAL) {
468 struct ieee80211_txq *txq;
469 struct rtw_txq *rtwtxq;
470
471 txq = sta->txq[tid];
472 rtwtxq = (struct rtw_txq *)txq->drv_priv;
473 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
474 }
475
476 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
477 }
478 }
479
rtw_txq_ba_work(struct work_struct * work)480 static void rtw_txq_ba_work(struct work_struct *work)
481 {
482 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
483 struct rtw_txq_ba_iter_data data;
484
485 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
486 }
487
rtw_get_channel_params(struct cfg80211_chan_def * chandef,struct rtw_channel_params * chan_params)488 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
489 struct rtw_channel_params *chan_params)
490 {
491 struct ieee80211_channel *channel = chandef->chan;
492 enum nl80211_chan_width width = chandef->width;
493 u8 *cch_by_bw = chan_params->cch_by_bw;
494 u32 primary_freq, center_freq;
495 u8 center_chan;
496 u8 bandwidth = RTW_CHANNEL_WIDTH_20;
497 u8 primary_chan_idx = 0;
498 u8 i;
499
500 center_chan = channel->hw_value;
501 primary_freq = channel->center_freq;
502 center_freq = chandef->center_freq1;
503
504 /* assign the center channel used while 20M bw is selected */
505 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value;
506
507 switch (width) {
508 case NL80211_CHAN_WIDTH_20_NOHT:
509 case NL80211_CHAN_WIDTH_20:
510 bandwidth = RTW_CHANNEL_WIDTH_20;
511 primary_chan_idx = RTW_SC_DONT_CARE;
512 break;
513 case NL80211_CHAN_WIDTH_40:
514 bandwidth = RTW_CHANNEL_WIDTH_40;
515 if (primary_freq > center_freq) {
516 primary_chan_idx = RTW_SC_20_UPPER;
517 center_chan -= 2;
518 } else {
519 primary_chan_idx = RTW_SC_20_LOWER;
520 center_chan += 2;
521 }
522 break;
523 case NL80211_CHAN_WIDTH_80:
524 bandwidth = RTW_CHANNEL_WIDTH_80;
525 if (primary_freq > center_freq) {
526 if (primary_freq - center_freq == 10) {
527 primary_chan_idx = RTW_SC_20_UPPER;
528 center_chan -= 2;
529 } else {
530 primary_chan_idx = RTW_SC_20_UPMOST;
531 center_chan -= 6;
532 }
533 /* assign the center channel used
534 * while 40M bw is selected
535 */
536 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4;
537 } else {
538 if (center_freq - primary_freq == 10) {
539 primary_chan_idx = RTW_SC_20_LOWER;
540 center_chan += 2;
541 } else {
542 primary_chan_idx = RTW_SC_20_LOWEST;
543 center_chan += 6;
544 }
545 /* assign the center channel used
546 * while 40M bw is selected
547 */
548 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4;
549 }
550 break;
551 default:
552 center_chan = 0;
553 break;
554 }
555
556 chan_params->center_chan = center_chan;
557 chan_params->bandwidth = bandwidth;
558 chan_params->primary_chan_idx = primary_chan_idx;
559
560 /* assign the center channel used while current bw is selected */
561 cch_by_bw[bandwidth] = center_chan;
562
563 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++)
564 cch_by_bw[i] = 0;
565 }
566
rtw_set_channel(struct rtw_dev * rtwdev)567 void rtw_set_channel(struct rtw_dev *rtwdev)
568 {
569 struct ieee80211_hw *hw = rtwdev->hw;
570 struct rtw_hal *hal = &rtwdev->hal;
571 struct rtw_chip_info *chip = rtwdev->chip;
572 struct rtw_channel_params ch_param;
573 u8 center_chan, bandwidth, primary_chan_idx;
574 u8 i;
575
576 rtw_get_channel_params(&hw->conf.chandef, &ch_param);
577 if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
578 return;
579
580 center_chan = ch_param.center_chan;
581 bandwidth = ch_param.bandwidth;
582 primary_chan_idx = ch_param.primary_chan_idx;
583
584 hal->current_band_width = bandwidth;
585 hal->current_channel = center_chan;
586 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
587
588 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++)
589 hal->cch_by_bw[i] = ch_param.cch_by_bw[i];
590
591 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
592
593 if (hal->current_band_type == RTW_BAND_5G) {
594 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
595 } else {
596 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
597 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
598 else
599 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
600 }
601
602 rtw_phy_set_tx_power_level(rtwdev, center_chan);
603
604 /* if the channel isn't set for scanning, we will do RF calibration
605 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
606 * during scanning on each channel takes too long.
607 */
608 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
609 rtwdev->need_rfk = true;
610 }
611
rtw_chip_prepare_tx(struct rtw_dev * rtwdev)612 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
613 {
614 struct rtw_chip_info *chip = rtwdev->chip;
615
616 if (rtwdev->need_rfk) {
617 rtwdev->need_rfk = false;
618 chip->ops->phy_calibration(rtwdev);
619 }
620 }
621
rtw_vif_write_addr(struct rtw_dev * rtwdev,u32 start,u8 * addr)622 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
623 {
624 int i;
625
626 for (i = 0; i < ETH_ALEN; i++)
627 rtw_write8(rtwdev, start + i, addr[i]);
628 }
629
rtw_vif_port_config(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif,u32 config)630 void rtw_vif_port_config(struct rtw_dev *rtwdev,
631 struct rtw_vif *rtwvif,
632 u32 config)
633 {
634 u32 addr, mask;
635
636 if (config & PORT_SET_MAC_ADDR) {
637 addr = rtwvif->conf->mac_addr.addr;
638 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
639 }
640 if (config & PORT_SET_BSSID) {
641 addr = rtwvif->conf->bssid.addr;
642 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
643 }
644 if (config & PORT_SET_NET_TYPE) {
645 addr = rtwvif->conf->net_type.addr;
646 mask = rtwvif->conf->net_type.mask;
647 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
648 }
649 if (config & PORT_SET_AID) {
650 addr = rtwvif->conf->aid.addr;
651 mask = rtwvif->conf->aid.mask;
652 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
653 }
654 if (config & PORT_SET_BCN_CTRL) {
655 addr = rtwvif->conf->bcn_ctrl.addr;
656 mask = rtwvif->conf->bcn_ctrl.mask;
657 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
658 }
659 }
660
hw_bw_cap_to_bitamp(u8 bw_cap)661 static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
662 {
663 u8 bw = 0;
664
665 switch (bw_cap) {
666 case EFUSE_HW_CAP_IGNORE:
667 case EFUSE_HW_CAP_SUPP_BW80:
668 bw |= BIT(RTW_CHANNEL_WIDTH_80);
669 fallthrough;
670 case EFUSE_HW_CAP_SUPP_BW40:
671 bw |= BIT(RTW_CHANNEL_WIDTH_40);
672 fallthrough;
673 default:
674 bw |= BIT(RTW_CHANNEL_WIDTH_20);
675 break;
676 }
677
678 return bw;
679 }
680
rtw_hw_config_rf_ant_num(struct rtw_dev * rtwdev,u8 hw_ant_num)681 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
682 {
683 struct rtw_hal *hal = &rtwdev->hal;
684 struct rtw_chip_info *chip = rtwdev->chip;
685
686 if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
687 hw_ant_num >= hal->rf_path_num)
688 return;
689
690 switch (hw_ant_num) {
691 case 1:
692 hal->rf_type = RF_1T1R;
693 hal->rf_path_num = 1;
694 if (!chip->fix_rf_phy_num)
695 hal->rf_phy_num = hal->rf_path_num;
696 hal->antenna_tx = BB_PATH_A;
697 hal->antenna_rx = BB_PATH_A;
698 break;
699 default:
700 WARN(1, "invalid hw configuration from efuse\n");
701 break;
702 }
703 }
704
get_vht_ra_mask(struct ieee80211_sta * sta)705 static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
706 {
707 u64 ra_mask = 0;
708 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map);
709 u8 vht_mcs_cap;
710 int i, nss;
711
712 /* 4SS, every two bits for MCS7/8/9 */
713 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
714 vht_mcs_cap = mcs_map & 0x3;
715 switch (vht_mcs_cap) {
716 case 2: /* MCS9 */
717 ra_mask |= 0x3ffULL << nss;
718 break;
719 case 1: /* MCS8 */
720 ra_mask |= 0x1ffULL << nss;
721 break;
722 case 0: /* MCS7 */
723 ra_mask |= 0x0ffULL << nss;
724 break;
725 default:
726 break;
727 }
728 }
729
730 return ra_mask;
731 }
732
get_rate_id(u8 wireless_set,enum rtw_bandwidth bw_mode,u8 tx_num)733 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
734 {
735 u8 rate_id = 0;
736
737 switch (wireless_set) {
738 case WIRELESS_CCK:
739 rate_id = RTW_RATEID_B_20M;
740 break;
741 case WIRELESS_OFDM:
742 rate_id = RTW_RATEID_G;
743 break;
744 case WIRELESS_CCK | WIRELESS_OFDM:
745 rate_id = RTW_RATEID_BG;
746 break;
747 case WIRELESS_OFDM | WIRELESS_HT:
748 if (tx_num == 1)
749 rate_id = RTW_RATEID_GN_N1SS;
750 else if (tx_num == 2)
751 rate_id = RTW_RATEID_GN_N2SS;
752 else if (tx_num == 3)
753 rate_id = RTW_RATEID_ARFR5_N_3SS;
754 break;
755 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
756 if (bw_mode == RTW_CHANNEL_WIDTH_40) {
757 if (tx_num == 1)
758 rate_id = RTW_RATEID_BGN_40M_1SS;
759 else if (tx_num == 2)
760 rate_id = RTW_RATEID_BGN_40M_2SS;
761 else if (tx_num == 3)
762 rate_id = RTW_RATEID_ARFR5_N_3SS;
763 else if (tx_num == 4)
764 rate_id = RTW_RATEID_ARFR7_N_4SS;
765 } else {
766 if (tx_num == 1)
767 rate_id = RTW_RATEID_BGN_20M_1SS;
768 else if (tx_num == 2)
769 rate_id = RTW_RATEID_BGN_20M_2SS;
770 else if (tx_num == 3)
771 rate_id = RTW_RATEID_ARFR5_N_3SS;
772 else if (tx_num == 4)
773 rate_id = RTW_RATEID_ARFR7_N_4SS;
774 }
775 break;
776 case WIRELESS_OFDM | WIRELESS_VHT:
777 if (tx_num == 1)
778 rate_id = RTW_RATEID_ARFR1_AC_1SS;
779 else if (tx_num == 2)
780 rate_id = RTW_RATEID_ARFR0_AC_2SS;
781 else if (tx_num == 3)
782 rate_id = RTW_RATEID_ARFR4_AC_3SS;
783 else if (tx_num == 4)
784 rate_id = RTW_RATEID_ARFR6_AC_4SS;
785 break;
786 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
787 if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
788 if (tx_num == 1)
789 rate_id = RTW_RATEID_ARFR1_AC_1SS;
790 else if (tx_num == 2)
791 rate_id = RTW_RATEID_ARFR0_AC_2SS;
792 else if (tx_num == 3)
793 rate_id = RTW_RATEID_ARFR4_AC_3SS;
794 else if (tx_num == 4)
795 rate_id = RTW_RATEID_ARFR6_AC_4SS;
796 } else {
797 if (tx_num == 1)
798 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
799 else if (tx_num == 2)
800 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
801 else if (tx_num == 3)
802 rate_id = RTW_RATEID_ARFR4_AC_3SS;
803 else if (tx_num == 4)
804 rate_id = RTW_RATEID_ARFR6_AC_4SS;
805 }
806 break;
807 default:
808 break;
809 }
810
811 return rate_id;
812 }
813
814 #define RA_MASK_CCK_RATES 0x0000f
815 #define RA_MASK_OFDM_RATES 0x00ff0
816 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
817 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
818 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
819 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
820 RA_MASK_HT_RATES_2SS | \
821 RA_MASK_HT_RATES_3SS)
822 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
823 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
824 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
825 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
826 RA_MASK_VHT_RATES_2SS | \
827 RA_MASK_VHT_RATES_3SS)
828 #define RA_MASK_CCK_IN_HT 0x00005
829 #define RA_MASK_CCK_IN_VHT 0x00005
830 #define RA_MASK_OFDM_IN_VHT 0x00010
831 #define RA_MASK_OFDM_IN_HT_2G 0x00010
832 #define RA_MASK_OFDM_IN_HT_5G 0x00030
833
rtw_update_rate_mask(struct rtw_dev * rtwdev,struct rtw_sta_info * si,u64 ra_mask,bool is_vht_enable,u8 wireless_set)834 static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev,
835 struct rtw_sta_info *si,
836 u64 ra_mask, bool is_vht_enable,
837 u8 wireless_set)
838 {
839 struct rtw_hal *hal = &rtwdev->hal;
840 const struct cfg80211_bitrate_mask *mask = si->mask;
841 u64 cfg_mask = GENMASK_ULL(63, 0);
842 u8 rssi_level, band;
843
844 if (wireless_set != WIRELESS_CCK) {
845 rssi_level = si->rssi_level;
846 if (rssi_level == 0)
847 ra_mask &= 0xffffffffffffffffULL;
848 else if (rssi_level == 1)
849 ra_mask &= 0xfffffffffffffff0ULL;
850 else if (rssi_level == 2)
851 ra_mask &= 0xffffffffffffefe0ULL;
852 else if (rssi_level == 3)
853 ra_mask &= 0xffffffffffffcfc0ULL;
854 else if (rssi_level == 4)
855 ra_mask &= 0xffffffffffff8f80ULL;
856 else if (rssi_level >= 5)
857 ra_mask &= 0xffffffffffff0f00ULL;
858 }
859
860 if (!si->use_cfg_mask)
861 return ra_mask;
862
863 band = hal->current_band_type;
864 if (band == RTW_BAND_2G) {
865 band = NL80211_BAND_2GHZ;
866 cfg_mask = mask->control[band].legacy;
867 } else if (band == RTW_BAND_5G) {
868 band = NL80211_BAND_5GHZ;
869 cfg_mask = u64_encode_bits(mask->control[band].legacy,
870 RA_MASK_OFDM_RATES);
871 }
872
873 if (!is_vht_enable) {
874 if (ra_mask & RA_MASK_HT_RATES_1SS)
875 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
876 RA_MASK_HT_RATES_1SS);
877 if (ra_mask & RA_MASK_HT_RATES_2SS)
878 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
879 RA_MASK_HT_RATES_2SS);
880 } else {
881 if (ra_mask & RA_MASK_VHT_RATES_1SS)
882 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
883 RA_MASK_VHT_RATES_1SS);
884 if (ra_mask & RA_MASK_VHT_RATES_2SS)
885 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
886 RA_MASK_VHT_RATES_2SS);
887 }
888
889 ra_mask &= cfg_mask;
890
891 return ra_mask;
892 }
893
rtw_update_sta_info(struct rtw_dev * rtwdev,struct rtw_sta_info * si)894 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si)
895 {
896 struct ieee80211_sta *sta = si->sta;
897 struct rtw_efuse *efuse = &rtwdev->efuse;
898 struct rtw_hal *hal = &rtwdev->hal;
899 u8 wireless_set;
900 u8 bw_mode;
901 u8 rate_id;
902 u8 rf_type = RF_1T1R;
903 u8 stbc_en = 0;
904 u8 ldpc_en = 0;
905 u8 tx_num = 1;
906 u64 ra_mask = 0;
907 bool is_vht_enable = false;
908 bool is_support_sgi = false;
909
910 if (sta->vht_cap.vht_supported) {
911 is_vht_enable = true;
912 ra_mask |= get_vht_ra_mask(sta);
913 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
914 stbc_en = VHT_STBC_EN;
915 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
916 ldpc_en = VHT_LDPC_EN;
917 } else if (sta->ht_cap.ht_supported) {
918 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) |
919 (sta->ht_cap.mcs.rx_mask[0] << 12);
920 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
921 stbc_en = HT_STBC_EN;
922 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
923 ldpc_en = HT_LDPC_EN;
924 }
925
926 if (efuse->hw_cap.nss == 1)
927 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
928
929 if (hal->current_band_type == RTW_BAND_5G) {
930 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4;
931 if (sta->vht_cap.vht_supported) {
932 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
933 wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
934 } else if (sta->ht_cap.ht_supported) {
935 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
936 wireless_set = WIRELESS_OFDM | WIRELESS_HT;
937 } else {
938 wireless_set = WIRELESS_OFDM;
939 }
940 } else if (hal->current_band_type == RTW_BAND_2G) {
941 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ];
942 if (sta->vht_cap.vht_supported) {
943 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
944 RA_MASK_OFDM_IN_VHT;
945 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
946 WIRELESS_HT | WIRELESS_VHT;
947 } else if (sta->ht_cap.ht_supported) {
948 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
949 RA_MASK_OFDM_IN_HT_2G;
950 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
951 WIRELESS_HT;
952 } else if (sta->supp_rates[0] <= 0xf) {
953 wireless_set = WIRELESS_CCK;
954 } else {
955 wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
956 }
957 } else {
958 rtw_err(rtwdev, "Unknown band type\n");
959 wireless_set = 0;
960 }
961
962 switch (sta->bandwidth) {
963 case IEEE80211_STA_RX_BW_80:
964 bw_mode = RTW_CHANNEL_WIDTH_80;
965 is_support_sgi = sta->vht_cap.vht_supported &&
966 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
967 break;
968 case IEEE80211_STA_RX_BW_40:
969 bw_mode = RTW_CHANNEL_WIDTH_40;
970 is_support_sgi = sta->ht_cap.ht_supported &&
971 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
972 break;
973 default:
974 bw_mode = RTW_CHANNEL_WIDTH_20;
975 is_support_sgi = sta->ht_cap.ht_supported &&
976 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
977 break;
978 }
979
980 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) {
981 tx_num = 2;
982 rf_type = RF_2T2R;
983 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) {
984 tx_num = 2;
985 rf_type = RF_2T2R;
986 }
987
988 rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
989
990 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable,
991 wireless_set);
992
993 si->bw_mode = bw_mode;
994 si->stbc_en = stbc_en;
995 si->ldpc_en = ldpc_en;
996 si->rf_type = rf_type;
997 si->wireless_set = wireless_set;
998 si->sgi_enable = is_support_sgi;
999 si->vht_enable = is_vht_enable;
1000 si->ra_mask = ra_mask;
1001 si->rate_id = rate_id;
1002
1003 rtw_fw_send_ra_info(rtwdev, si);
1004 }
1005
rtw_wait_firmware_completion(struct rtw_dev * rtwdev)1006 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1007 {
1008 struct rtw_chip_info *chip = rtwdev->chip;
1009 struct rtw_fw_state *fw;
1010
1011 fw = &rtwdev->fw;
1012 wait_for_completion(&fw->completion);
1013 if (!fw->firmware)
1014 return -EINVAL;
1015
1016 if (chip->wow_fw_name) {
1017 fw = &rtwdev->wow_fw;
1018 wait_for_completion(&fw->completion);
1019 if (!fw->firmware)
1020 return -EINVAL;
1021 }
1022
1023 return 0;
1024 }
1025
rtw_power_on(struct rtw_dev * rtwdev)1026 static int rtw_power_on(struct rtw_dev *rtwdev)
1027 {
1028 struct rtw_chip_info *chip = rtwdev->chip;
1029 struct rtw_fw_state *fw = &rtwdev->fw;
1030 bool wifi_only;
1031 int ret;
1032
1033 ret = rtw_hci_setup(rtwdev);
1034 if (ret) {
1035 rtw_err(rtwdev, "failed to setup hci\n");
1036 goto err;
1037 }
1038
1039 /* power on MAC before firmware downloaded */
1040 ret = rtw_mac_power_on(rtwdev);
1041 if (ret) {
1042 rtw_err(rtwdev, "failed to power on mac\n");
1043 goto err;
1044 }
1045
1046 ret = rtw_wait_firmware_completion(rtwdev);
1047 if (ret) {
1048 rtw_err(rtwdev, "failed to wait firmware completion\n");
1049 goto err_off;
1050 }
1051
1052 ret = rtw_download_firmware(rtwdev, fw);
1053 if (ret) {
1054 rtw_err(rtwdev, "failed to download firmware\n");
1055 goto err_off;
1056 }
1057
1058 /* config mac after firmware downloaded */
1059 ret = rtw_mac_init(rtwdev);
1060 if (ret) {
1061 rtw_err(rtwdev, "failed to configure mac\n");
1062 goto err_off;
1063 }
1064
1065 chip->ops->phy_set_param(rtwdev);
1066
1067 ret = rtw_hci_start(rtwdev);
1068 if (ret) {
1069 rtw_err(rtwdev, "failed to start hci\n");
1070 goto err_off;
1071 }
1072
1073 /* send H2C after HCI has started */
1074 rtw_fw_send_general_info(rtwdev);
1075 rtw_fw_send_phydm_info(rtwdev);
1076
1077 wifi_only = !rtwdev->efuse.btcoex;
1078 rtw_coex_power_on_setting(rtwdev);
1079 rtw_coex_init_hw_config(rtwdev, wifi_only);
1080
1081 return 0;
1082
1083 err_off:
1084 rtw_mac_power_off(rtwdev);
1085
1086 err:
1087 return ret;
1088 }
1089
rtw_core_start(struct rtw_dev * rtwdev)1090 int rtw_core_start(struct rtw_dev *rtwdev)
1091 {
1092 int ret;
1093
1094 ret = rtw_power_on(rtwdev);
1095 if (ret)
1096 return ret;
1097
1098 rtw_sec_enable_sec_engine(rtwdev);
1099
1100 /* rcr reset after powered on */
1101 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1102
1103 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1104 RTW_WATCH_DOG_DELAY_TIME);
1105
1106 set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1107
1108 return 0;
1109 }
1110
rtw_power_off(struct rtw_dev * rtwdev)1111 static void rtw_power_off(struct rtw_dev *rtwdev)
1112 {
1113 rtw_hci_stop(rtwdev);
1114 rtw_mac_power_off(rtwdev);
1115 }
1116
rtw_core_stop(struct rtw_dev * rtwdev)1117 void rtw_core_stop(struct rtw_dev *rtwdev)
1118 {
1119 struct rtw_coex *coex = &rtwdev->coex;
1120
1121 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1122 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1123
1124 mutex_unlock(&rtwdev->mutex);
1125
1126 cancel_work_sync(&rtwdev->c2h_work);
1127 cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1128 cancel_delayed_work_sync(&coex->bt_relink_work);
1129 cancel_delayed_work_sync(&coex->bt_reenable_work);
1130 cancel_delayed_work_sync(&coex->defreeze_work);
1131 cancel_delayed_work_sync(&coex->wl_remain_work);
1132 cancel_delayed_work_sync(&coex->bt_remain_work);
1133
1134 mutex_lock(&rtwdev->mutex);
1135
1136 rtw_power_off(rtwdev);
1137 }
1138
rtw_init_ht_cap(struct rtw_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)1139 static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1140 struct ieee80211_sta_ht_cap *ht_cap)
1141 {
1142 struct rtw_efuse *efuse = &rtwdev->efuse;
1143
1144 ht_cap->ht_supported = true;
1145 ht_cap->cap = 0;
1146 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1147 IEEE80211_HT_CAP_MAX_AMSDU |
1148 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1149
1150 if (rtw_chip_has_rx_ldpc(rtwdev))
1151 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1152
1153 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1154 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1155 IEEE80211_HT_CAP_DSSSCCK40 |
1156 IEEE80211_HT_CAP_SGI_40;
1157 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1158 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
1159 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1160 if (efuse->hw_cap.nss > 1) {
1161 ht_cap->mcs.rx_mask[0] = 0xFF;
1162 ht_cap->mcs.rx_mask[1] = 0xFF;
1163 ht_cap->mcs.rx_mask[4] = 0x01;
1164 ht_cap->mcs.rx_highest = cpu_to_le16(300);
1165 } else {
1166 ht_cap->mcs.rx_mask[0] = 0xFF;
1167 ht_cap->mcs.rx_mask[1] = 0x00;
1168 ht_cap->mcs.rx_mask[4] = 0x01;
1169 ht_cap->mcs.rx_highest = cpu_to_le16(150);
1170 }
1171 }
1172
rtw_init_vht_cap(struct rtw_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)1173 static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1174 struct ieee80211_sta_vht_cap *vht_cap)
1175 {
1176 struct rtw_efuse *efuse = &rtwdev->efuse;
1177 u16 mcs_map;
1178 __le16 highest;
1179
1180 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1181 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1182 return;
1183
1184 vht_cap->vht_supported = true;
1185 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1186 IEEE80211_VHT_CAP_SHORT_GI_80 |
1187 IEEE80211_VHT_CAP_RXSTBC_1 |
1188 IEEE80211_VHT_CAP_HTC_VHT |
1189 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1190 0;
1191 if (rtwdev->hal.rf_path_num > 1)
1192 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1193 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1194 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1195 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1196 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1197
1198 if (rtw_chip_has_rx_ldpc(rtwdev))
1199 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1200
1201 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
1202 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
1203 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
1204 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
1205 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
1206 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
1207 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
1208 if (efuse->hw_cap.nss > 1) {
1209 highest = cpu_to_le16(780);
1210 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
1211 } else {
1212 highest = cpu_to_le16(390);
1213 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
1214 }
1215
1216 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1217 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1218 vht_cap->vht_mcs.rx_highest = highest;
1219 vht_cap->vht_mcs.tx_highest = highest;
1220 }
1221
rtw_set_supported_band(struct ieee80211_hw * hw,struct rtw_chip_info * chip)1222 static void rtw_set_supported_band(struct ieee80211_hw *hw,
1223 struct rtw_chip_info *chip)
1224 {
1225 struct rtw_dev *rtwdev = hw->priv;
1226 struct ieee80211_supported_band *sband;
1227
1228 if (chip->band & RTW_BAND_2G) {
1229 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1230 if (!sband)
1231 goto err_out;
1232 if (chip->ht_supported)
1233 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1234 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1235 }
1236
1237 if (chip->band & RTW_BAND_5G) {
1238 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1239 if (!sband)
1240 goto err_out;
1241 if (chip->ht_supported)
1242 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1243 if (chip->vht_supported)
1244 rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1245 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1246 }
1247
1248 return;
1249
1250 err_out:
1251 rtw_err(rtwdev, "failed to set supported band\n");
1252 kfree(sband);
1253 }
1254
rtw_unset_supported_band(struct ieee80211_hw * hw,struct rtw_chip_info * chip)1255 static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1256 struct rtw_chip_info *chip)
1257 {
1258 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1259 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1260 }
1261
__update_firmware_info(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1262 static void __update_firmware_info(struct rtw_dev *rtwdev,
1263 struct rtw_fw_state *fw)
1264 {
1265 const struct rtw_fw_hdr *fw_hdr =
1266 (const struct rtw_fw_hdr *)fw->firmware->data;
1267
1268 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1269 fw->version = le16_to_cpu(fw_hdr->version);
1270 fw->sub_version = fw_hdr->subversion;
1271 fw->sub_index = fw_hdr->subindex;
1272 }
1273
__update_firmware_info_legacy(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1274 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1275 struct rtw_fw_state *fw)
1276 {
1277 struct rtw_fw_hdr_legacy *legacy =
1278 (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1279
1280 fw->h2c_version = 0;
1281 fw->version = le16_to_cpu(legacy->version);
1282 fw->sub_version = legacy->subversion1;
1283 fw->sub_index = legacy->subversion2;
1284 }
1285
update_firmware_info(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1286 static void update_firmware_info(struct rtw_dev *rtwdev,
1287 struct rtw_fw_state *fw)
1288 {
1289 if (rtw_chip_wcpu_11n(rtwdev))
1290 __update_firmware_info_legacy(rtwdev, fw);
1291 else
1292 __update_firmware_info(rtwdev, fw);
1293 }
1294
rtw_load_firmware_cb(const struct firmware * firmware,void * context)1295 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1296 {
1297 struct rtw_fw_state *fw = context;
1298 struct rtw_dev *rtwdev = fw->rtwdev;
1299
1300 if (!firmware || !firmware->data) {
1301 rtw_err(rtwdev, "failed to request firmware\n");
1302 complete_all(&fw->completion);
1303 return;
1304 }
1305
1306 fw->firmware = firmware;
1307 update_firmware_info(rtwdev, fw);
1308 complete_all(&fw->completion);
1309
1310 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n",
1311 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1312 }
1313
rtw_load_firmware(struct rtw_dev * rtwdev,enum rtw_fw_type type)1314 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1315 {
1316 const char *fw_name;
1317 struct rtw_fw_state *fw;
1318 int ret;
1319
1320 switch (type) {
1321 case RTW_WOWLAN_FW:
1322 fw = &rtwdev->wow_fw;
1323 fw_name = rtwdev->chip->wow_fw_name;
1324 break;
1325
1326 case RTW_NORMAL_FW:
1327 fw = &rtwdev->fw;
1328 fw_name = rtwdev->chip->fw_name;
1329 break;
1330
1331 default:
1332 rtw_warn(rtwdev, "unsupported firmware type\n");
1333 return -ENOENT;
1334 }
1335
1336 fw->rtwdev = rtwdev;
1337 init_completion(&fw->completion);
1338
1339 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1340 GFP_KERNEL, fw, rtw_load_firmware_cb);
1341 if (ret) {
1342 rtw_err(rtwdev, "failed to async firmware request\n");
1343 return ret;
1344 }
1345
1346 return 0;
1347 }
1348
rtw_chip_parameter_setup(struct rtw_dev * rtwdev)1349 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1350 {
1351 struct rtw_chip_info *chip = rtwdev->chip;
1352 struct rtw_hal *hal = &rtwdev->hal;
1353 struct rtw_efuse *efuse = &rtwdev->efuse;
1354 int ret = 0;
1355
1356 switch (rtw_hci_type(rtwdev)) {
1357 case RTW_HCI_TYPE_PCIE:
1358 rtwdev->hci.rpwm_addr = 0x03d9;
1359 rtwdev->hci.cpwm_addr = 0x03da;
1360 break;
1361 default:
1362 rtw_err(rtwdev, "unsupported hci type\n");
1363 return -EINVAL;
1364 }
1365
1366 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1367 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1368 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1369 if (hal->chip_version & BIT_RF_TYPE_ID) {
1370 hal->rf_type = RF_2T2R;
1371 hal->rf_path_num = 2;
1372 hal->antenna_tx = BB_PATH_AB;
1373 hal->antenna_rx = BB_PATH_AB;
1374 } else {
1375 hal->rf_type = RF_1T1R;
1376 hal->rf_path_num = 1;
1377 hal->antenna_tx = BB_PATH_A;
1378 hal->antenna_rx = BB_PATH_A;
1379 }
1380 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1381 hal->rf_path_num;
1382
1383 efuse->physical_size = chip->phy_efuse_size;
1384 efuse->logical_size = chip->log_efuse_size;
1385 efuse->protect_size = chip->ptct_efuse_size;
1386
1387 /* default use ack */
1388 rtwdev->hal.rcr |= BIT_VHT_DACK;
1389
1390 hal->bfee_sts_cap = 3;
1391
1392 return ret;
1393 }
1394
rtw_chip_efuse_enable(struct rtw_dev * rtwdev)1395 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1396 {
1397 struct rtw_fw_state *fw = &rtwdev->fw;
1398 int ret;
1399
1400 ret = rtw_hci_setup(rtwdev);
1401 if (ret) {
1402 rtw_err(rtwdev, "failed to setup hci\n");
1403 goto err;
1404 }
1405
1406 ret = rtw_mac_power_on(rtwdev);
1407 if (ret) {
1408 rtw_err(rtwdev, "failed to power on mac\n");
1409 goto err;
1410 }
1411
1412 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1413
1414 wait_for_completion(&fw->completion);
1415 if (!fw->firmware) {
1416 ret = -EINVAL;
1417 rtw_err(rtwdev, "failed to load firmware\n");
1418 goto err;
1419 }
1420
1421 ret = rtw_download_firmware(rtwdev, fw);
1422 if (ret) {
1423 rtw_err(rtwdev, "failed to download firmware\n");
1424 goto err_off;
1425 }
1426
1427 return 0;
1428
1429 err_off:
1430 rtw_mac_power_off(rtwdev);
1431
1432 err:
1433 return ret;
1434 }
1435
rtw_dump_hw_feature(struct rtw_dev * rtwdev)1436 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1437 {
1438 struct rtw_efuse *efuse = &rtwdev->efuse;
1439 u8 hw_feature[HW_FEATURE_LEN];
1440 u8 id;
1441 u8 bw;
1442 int i;
1443
1444 id = rtw_read8(rtwdev, REG_C2HEVT);
1445 if (id != C2H_HW_FEATURE_REPORT) {
1446 rtw_err(rtwdev, "failed to read hw feature report\n");
1447 return -EBUSY;
1448 }
1449
1450 for (i = 0; i < HW_FEATURE_LEN; i++)
1451 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1452
1453 rtw_write8(rtwdev, REG_C2HEVT, 0);
1454
1455 bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1456 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1457 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1458 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1459 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1460 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1461
1462 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1463
1464 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1465 efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1466 efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1467
1468 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1469 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1470 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1471 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1472
1473 return 0;
1474 }
1475
rtw_chip_efuse_disable(struct rtw_dev * rtwdev)1476 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1477 {
1478 rtw_hci_stop(rtwdev);
1479 rtw_mac_power_off(rtwdev);
1480 }
1481
rtw_chip_efuse_info_setup(struct rtw_dev * rtwdev)1482 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
1483 {
1484 struct rtw_efuse *efuse = &rtwdev->efuse;
1485 int ret;
1486
1487 mutex_lock(&rtwdev->mutex);
1488
1489 /* power on mac to read efuse */
1490 ret = rtw_chip_efuse_enable(rtwdev);
1491 if (ret)
1492 goto out_unlock;
1493
1494 ret = rtw_parse_efuse_map(rtwdev);
1495 if (ret)
1496 goto out_disable;
1497
1498 ret = rtw_dump_hw_feature(rtwdev);
1499 if (ret)
1500 goto out_disable;
1501
1502 ret = rtw_check_supported_rfe(rtwdev);
1503 if (ret)
1504 goto out_disable;
1505
1506 if (efuse->crystal_cap == 0xff)
1507 efuse->crystal_cap = 0;
1508 if (efuse->pa_type_2g == 0xff)
1509 efuse->pa_type_2g = 0;
1510 if (efuse->pa_type_5g == 0xff)
1511 efuse->pa_type_5g = 0;
1512 if (efuse->lna_type_2g == 0xff)
1513 efuse->lna_type_2g = 0;
1514 if (efuse->lna_type_5g == 0xff)
1515 efuse->lna_type_5g = 0;
1516 if (efuse->channel_plan == 0xff)
1517 efuse->channel_plan = 0x7f;
1518 if (efuse->rf_board_option == 0xff)
1519 efuse->rf_board_option = 0;
1520 if (efuse->bt_setting & BIT(0))
1521 efuse->share_ant = true;
1522 if (efuse->regd == 0xff)
1523 efuse->regd = 0;
1524 if (efuse->tx_bb_swing_setting_2g == 0xff)
1525 efuse->tx_bb_swing_setting_2g = 0;
1526 if (efuse->tx_bb_swing_setting_5g == 0xff)
1527 efuse->tx_bb_swing_setting_5g = 0;
1528
1529 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
1530 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
1531 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
1532 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
1533 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
1534
1535 out_disable:
1536 rtw_chip_efuse_disable(rtwdev);
1537
1538 out_unlock:
1539 mutex_unlock(&rtwdev->mutex);
1540 return ret;
1541 }
1542
rtw_chip_board_info_setup(struct rtw_dev * rtwdev)1543 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
1544 {
1545 struct rtw_hal *hal = &rtwdev->hal;
1546 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
1547
1548 if (!rfe_def)
1549 return -ENODEV;
1550
1551 rtw_phy_setup_phy_cond(rtwdev, 0);
1552
1553 rtw_phy_init_tx_power(rtwdev);
1554 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
1555 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
1556 rtw_phy_tx_power_by_rate_config(hal);
1557 rtw_phy_tx_power_limit_config(hal);
1558
1559 return 0;
1560 }
1561
rtw_chip_info_setup(struct rtw_dev * rtwdev)1562 int rtw_chip_info_setup(struct rtw_dev *rtwdev)
1563 {
1564 int ret;
1565
1566 ret = rtw_chip_parameter_setup(rtwdev);
1567 if (ret) {
1568 rtw_err(rtwdev, "failed to setup chip parameters\n");
1569 goto err_out;
1570 }
1571
1572 ret = rtw_chip_efuse_info_setup(rtwdev);
1573 if (ret) {
1574 rtw_err(rtwdev, "failed to setup chip efuse info\n");
1575 goto err_out;
1576 }
1577
1578 ret = rtw_chip_board_info_setup(rtwdev);
1579 if (ret) {
1580 rtw_err(rtwdev, "failed to setup chip board info\n");
1581 goto err_out;
1582 }
1583
1584 return 0;
1585
1586 err_out:
1587 return ret;
1588 }
1589 EXPORT_SYMBOL(rtw_chip_info_setup);
1590
rtw_stats_init(struct rtw_dev * rtwdev)1591 static void rtw_stats_init(struct rtw_dev *rtwdev)
1592 {
1593 struct rtw_traffic_stats *stats = &rtwdev->stats;
1594 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1595 int i;
1596
1597 ewma_tp_init(&stats->tx_ewma_tp);
1598 ewma_tp_init(&stats->rx_ewma_tp);
1599
1600 for (i = 0; i < RTW_EVM_NUM; i++)
1601 ewma_evm_init(&dm_info->ewma_evm[i]);
1602 for (i = 0; i < RTW_SNR_NUM; i++)
1603 ewma_snr_init(&dm_info->ewma_snr[i]);
1604 }
1605
rtw_core_init(struct rtw_dev * rtwdev)1606 int rtw_core_init(struct rtw_dev *rtwdev)
1607 {
1608 struct rtw_chip_info *chip = rtwdev->chip;
1609 struct rtw_coex *coex = &rtwdev->coex;
1610 int ret;
1611
1612 INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
1613 INIT_LIST_HEAD(&rtwdev->txqs);
1614
1615 timer_setup(&rtwdev->tx_report.purge_timer,
1616 rtw_tx_report_purge_timer, 0);
1617 tasklet_setup(&rtwdev->tx_tasklet, rtw_tx_tasklet);
1618
1619 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
1620 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
1621 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
1622 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
1623 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
1624 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
1625 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
1626 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
1627 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
1628 skb_queue_head_init(&rtwdev->c2h_queue);
1629 skb_queue_head_init(&rtwdev->coex.queue);
1630 skb_queue_head_init(&rtwdev->tx_report.queue);
1631
1632 spin_lock_init(&rtwdev->rf_lock);
1633 spin_lock_init(&rtwdev->h2c.lock);
1634 spin_lock_init(&rtwdev->txq_lock);
1635 spin_lock_init(&rtwdev->tx_report.q_lock);
1636
1637 mutex_init(&rtwdev->mutex);
1638 mutex_init(&rtwdev->coex.mutex);
1639 mutex_init(&rtwdev->hal.tx_power_mutex);
1640
1641 init_waitqueue_head(&rtwdev->coex.wait);
1642
1643 rtwdev->sec.total_cam_num = 32;
1644 rtwdev->hal.current_channel = 1;
1645 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
1646 if (!(BIT(rtw_fw_lps_deep_mode) & chip->lps_deep_mode_supported))
1647 rtwdev->lps_conf.deep_mode = LPS_DEEP_MODE_NONE;
1648 else
1649 rtwdev->lps_conf.deep_mode = rtw_fw_lps_deep_mode;
1650
1651 rtw_stats_init(rtwdev);
1652
1653 /* default rx filter setting */
1654 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
1655 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
1656 BIT_AB | BIT_AM | BIT_APM;
1657
1658 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
1659 if (ret) {
1660 rtw_warn(rtwdev, "no firmware loaded\n");
1661 return ret;
1662 }
1663
1664 if (chip->wow_fw_name) {
1665 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
1666 if (ret) {
1667 rtw_warn(rtwdev, "no wow firmware loaded\n");
1668 wait_for_completion(&rtwdev->fw.completion);
1669 if (rtwdev->fw.firmware)
1670 release_firmware(rtwdev->fw.firmware);
1671 return ret;
1672 }
1673 }
1674 return 0;
1675 }
1676 EXPORT_SYMBOL(rtw_core_init);
1677
rtw_core_deinit(struct rtw_dev * rtwdev)1678 void rtw_core_deinit(struct rtw_dev *rtwdev)
1679 {
1680 struct rtw_fw_state *fw = &rtwdev->fw;
1681 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
1682 struct rtw_rsvd_page *rsvd_pkt, *tmp;
1683 unsigned long flags;
1684
1685 rtw_wait_firmware_completion(rtwdev);
1686
1687 if (fw->firmware)
1688 release_firmware(fw->firmware);
1689
1690 if (wow_fw->firmware)
1691 release_firmware(wow_fw->firmware);
1692
1693 tasklet_kill(&rtwdev->tx_tasklet);
1694 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
1695 skb_queue_purge(&rtwdev->tx_report.queue);
1696 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
1697
1698 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
1699 build_list) {
1700 list_del(&rsvd_pkt->build_list);
1701 kfree(rsvd_pkt);
1702 }
1703
1704 mutex_destroy(&rtwdev->mutex);
1705 mutex_destroy(&rtwdev->coex.mutex);
1706 mutex_destroy(&rtwdev->hal.tx_power_mutex);
1707 }
1708 EXPORT_SYMBOL(rtw_core_deinit);
1709
rtw_register_hw(struct rtw_dev * rtwdev,struct ieee80211_hw * hw)1710 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
1711 {
1712 struct rtw_hal *hal = &rtwdev->hal;
1713 int max_tx_headroom = 0;
1714 int ret;
1715
1716 /* TODO: USB & SDIO may need extra room? */
1717 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
1718
1719 hw->extra_tx_headroom = max_tx_headroom;
1720 hw->queues = IEEE80211_NUM_ACS;
1721 hw->txq_data_size = sizeof(struct rtw_txq);
1722 hw->sta_data_size = sizeof(struct rtw_sta_info);
1723 hw->vif_data_size = sizeof(struct rtw_vif);
1724
1725 ieee80211_hw_set(hw, SIGNAL_DBM);
1726 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
1727 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
1728 ieee80211_hw_set(hw, MFP_CAPABLE);
1729 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
1730 ieee80211_hw_set(hw, SUPPORTS_PS);
1731 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
1732 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
1733 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
1734 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
1735 ieee80211_hw_set(hw, TX_AMSDU);
1736
1737 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1738 BIT(NL80211_IFTYPE_AP) |
1739 BIT(NL80211_IFTYPE_ADHOC) |
1740 BIT(NL80211_IFTYPE_MESH_POINT);
1741 hw->wiphy->available_antennas_tx = hal->antenna_tx;
1742 hw->wiphy->available_antennas_rx = hal->antenna_rx;
1743
1744 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
1745 WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
1746
1747 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
1748
1749 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
1750
1751 #ifdef CONFIG_PM
1752 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
1753 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
1754 #endif
1755 rtw_set_supported_band(hw, rtwdev->chip);
1756 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
1757
1758 rtw_regd_init(rtwdev, rtw_regd_notifier);
1759
1760 ret = ieee80211_register_hw(hw);
1761 if (ret) {
1762 rtw_err(rtwdev, "failed to register hw\n");
1763 return ret;
1764 }
1765
1766 if (regulatory_hint(hw->wiphy, rtwdev->regd.alpha2))
1767 rtw_err(rtwdev, "regulatory_hint fail\n");
1768
1769 rtw_debugfs_init(rtwdev);
1770
1771 rtwdev->bf_info.bfer_mu_cnt = 0;
1772 rtwdev->bf_info.bfer_su_cnt = 0;
1773
1774 return 0;
1775 }
1776 EXPORT_SYMBOL(rtw_register_hw);
1777
rtw_unregister_hw(struct rtw_dev * rtwdev,struct ieee80211_hw * hw)1778 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
1779 {
1780 struct rtw_chip_info *chip = rtwdev->chip;
1781
1782 ieee80211_unregister_hw(hw);
1783 rtw_unset_supported_band(hw, chip);
1784 }
1785 EXPORT_SYMBOL(rtw_unregister_hw);
1786
1787 MODULE_AUTHOR("Realtek Corporation");
1788 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
1789 MODULE_LICENSE("Dual BSD/GPL");
1790