1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * This file contains the common interrupt handlers
40 */
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/io.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
50
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
53
54 #include "core.h"
55 #include "hcd.h"
56
dwc2_op_state_str(struct dwc2_hsotg * hsotg)57 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
58 {
59 switch (hsotg->op_state) {
60 case OTG_STATE_A_HOST:
61 return "a_host";
62 case OTG_STATE_A_SUSPEND:
63 return "a_suspend";
64 case OTG_STATE_A_PERIPHERAL:
65 return "a_peripheral";
66 case OTG_STATE_B_PERIPHERAL:
67 return "b_peripheral";
68 case OTG_STATE_B_HOST:
69 return "b_host";
70 default:
71 return "unknown";
72 }
73 }
74
75 /**
76 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
77 * When the PRTINT interrupt fires, there are certain status bits in the Host
78 * Port that needs to get cleared.
79 *
80 * @hsotg: Programming view of DWC_otg controller
81 */
dwc2_handle_usb_port_intr(struct dwc2_hsotg * hsotg)82 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
83 {
84 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
85
86 if (hprt0 & HPRT0_ENACHG) {
87 hprt0 &= ~HPRT0_ENA;
88 dwc2_writel(hsotg, hprt0, HPRT0);
89 }
90 }
91
92 /**
93 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
94 *
95 * @hsotg: Programming view of DWC_otg controller
96 */
dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg * hsotg)97 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
98 {
99 /* Clear interrupt */
100 dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
101
102 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
103 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
104 }
105
106 /**
107 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
108 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
109 *
110 * @hsotg: Programming view of DWC_otg controller
111 */
dwc2_handle_otg_intr(struct dwc2_hsotg * hsotg)112 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
113 {
114 u32 gotgint;
115 u32 gotgctl;
116 u32 gintmsk;
117
118 gotgint = dwc2_readl(hsotg, GOTGINT);
119 gotgctl = dwc2_readl(hsotg, GOTGCTL);
120 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
121 dwc2_op_state_str(hsotg));
122
123 if (gotgint & GOTGINT_SES_END_DET) {
124 dev_dbg(hsotg->dev,
125 " ++OTG Interrupt: Session End Detected++ (%s)\n",
126 dwc2_op_state_str(hsotg));
127 gotgctl = dwc2_readl(hsotg, GOTGCTL);
128
129 if (dwc2_is_device_mode(hsotg))
130 dwc2_hsotg_disconnect(hsotg);
131
132 if (hsotg->op_state == OTG_STATE_B_HOST) {
133 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
134 } else {
135 /*
136 * If not B_HOST and Device HNP still set, HNP did
137 * not succeed!
138 */
139 if (gotgctl & GOTGCTL_DEVHNPEN) {
140 dev_dbg(hsotg->dev, "Session End Detected\n");
141 dev_err(hsotg->dev,
142 "Device Not Connected/Responding!\n");
143 }
144
145 /*
146 * If Session End Detected the B-Cable has been
147 * disconnected
148 */
149 /* Reset to a clean state */
150 hsotg->lx_state = DWC2_L0;
151 }
152
153 gotgctl = dwc2_readl(hsotg, GOTGCTL);
154 gotgctl &= ~GOTGCTL_DEVHNPEN;
155 dwc2_writel(hsotg, gotgctl, GOTGCTL);
156 }
157
158 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
159 dev_dbg(hsotg->dev,
160 " ++OTG Interrupt: Session Request Success Status Change++\n");
161 gotgctl = dwc2_readl(hsotg, GOTGCTL);
162 if (gotgctl & GOTGCTL_SESREQSCS) {
163 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
164 hsotg->params.i2c_enable) {
165 hsotg->srp_success = 1;
166 } else {
167 /* Clear Session Request */
168 gotgctl = dwc2_readl(hsotg, GOTGCTL);
169 gotgctl &= ~GOTGCTL_SESREQ;
170 dwc2_writel(hsotg, gotgctl, GOTGCTL);
171 }
172 }
173 }
174
175 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
176 /*
177 * Print statements during the HNP interrupt handling
178 * can cause it to fail
179 */
180 gotgctl = dwc2_readl(hsotg, GOTGCTL);
181 /*
182 * WA for 3.00a- HW is not setting cur_mode, even sometimes
183 * this does not help
184 */
185 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
186 udelay(100);
187 if (gotgctl & GOTGCTL_HSTNEGSCS) {
188 if (dwc2_is_host_mode(hsotg)) {
189 hsotg->op_state = OTG_STATE_B_HOST;
190 /*
191 * Need to disable SOF interrupt immediately.
192 * When switching from device to host, the PCD
193 * interrupt handler won't handle the interrupt
194 * if host mode is already set. The HCD
195 * interrupt handler won't get called if the
196 * HCD state is HALT. This means that the
197 * interrupt does not get handled and Linux
198 * complains loudly.
199 */
200 gintmsk = dwc2_readl(hsotg, GINTMSK);
201 gintmsk &= ~GINTSTS_SOF;
202 dwc2_writel(hsotg, gintmsk, GINTMSK);
203
204 /*
205 * Call callback function with spin lock
206 * released
207 */
208 spin_unlock(&hsotg->lock);
209
210 /* Initialize the Core for Host mode */
211 dwc2_hcd_start(hsotg);
212 spin_lock(&hsotg->lock);
213 hsotg->op_state = OTG_STATE_B_HOST;
214 }
215 } else {
216 gotgctl = dwc2_readl(hsotg, GOTGCTL);
217 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
218 dwc2_writel(hsotg, gotgctl, GOTGCTL);
219 dev_dbg(hsotg->dev, "HNP Failed\n");
220 dev_err(hsotg->dev,
221 "Device Not Connected/Responding\n");
222 }
223 }
224
225 if (gotgint & GOTGINT_HST_NEG_DET) {
226 /*
227 * The disconnect interrupt is set at the same time as
228 * Host Negotiation Detected. During the mode switch all
229 * interrupts are cleared so the disconnect interrupt
230 * handler will not get executed.
231 */
232 dev_dbg(hsotg->dev,
233 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
234 (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
235 if (dwc2_is_device_mode(hsotg)) {
236 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
237 hsotg->op_state);
238 spin_unlock(&hsotg->lock);
239 dwc2_hcd_disconnect(hsotg, false);
240 spin_lock(&hsotg->lock);
241 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
242 } else {
243 /* Need to disable SOF interrupt immediately */
244 gintmsk = dwc2_readl(hsotg, GINTMSK);
245 gintmsk &= ~GINTSTS_SOF;
246 dwc2_writel(hsotg, gintmsk, GINTMSK);
247 spin_unlock(&hsotg->lock);
248 dwc2_hcd_start(hsotg);
249 spin_lock(&hsotg->lock);
250 hsotg->op_state = OTG_STATE_A_HOST;
251 }
252 }
253
254 if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
255 dev_dbg(hsotg->dev,
256 " ++OTG Interrupt: A-Device Timeout Change++\n");
257 if (gotgint & GOTGINT_DBNCE_DONE)
258 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
259
260 /* Clear GOTGINT */
261 dwc2_writel(hsotg, gotgint, GOTGINT);
262 }
263
264 /**
265 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
266 * Change Interrupt
267 *
268 * @hsotg: Programming view of DWC_otg controller
269 *
270 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
271 * Device to Host Mode transition or a Host to Device Mode transition. This only
272 * occurs when the cable is connected/removed from the PHY connector.
273 */
dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg * hsotg)274 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
275 {
276 u32 gintmsk;
277
278 /* Clear interrupt */
279 dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
280
281 /* Need to disable SOF interrupt immediately */
282 gintmsk = dwc2_readl(hsotg, GINTMSK);
283 gintmsk &= ~GINTSTS_SOF;
284 dwc2_writel(hsotg, gintmsk, GINTMSK);
285
286 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
287 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
288
289 /*
290 * Need to schedule a work, as there are possible DELAY function calls.
291 */
292 if (hsotg->wq_otg)
293 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
294 }
295
296 /**
297 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
298 * initiating the Session Request Protocol to request the host to turn on bus
299 * power so a new session can begin
300 *
301 * @hsotg: Programming view of DWC_otg controller
302 *
303 * This handler responds by turning on bus power. If the DWC_otg controller is
304 * in low power mode, this handler brings the controller out of low power mode
305 * before turning on bus power.
306 */
dwc2_handle_session_req_intr(struct dwc2_hsotg * hsotg)307 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
308 {
309 int ret;
310 u32 hprt0;
311
312 /* Clear interrupt */
313 dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
314
315 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
316 hsotg->lx_state);
317
318 if (dwc2_is_device_mode(hsotg)) {
319 if (hsotg->lx_state == DWC2_L2) {
320 ret = dwc2_exit_partial_power_down(hsotg, true);
321 if (ret && (ret != -ENOTSUPP))
322 dev_err(hsotg->dev,
323 "exit power_down failed\n");
324 }
325
326 /*
327 * Report disconnect if there is any previous session
328 * established
329 */
330 dwc2_hsotg_disconnect(hsotg);
331 } else {
332 /* Turn on the port power bit. */
333 hprt0 = dwc2_read_hprt0(hsotg);
334 hprt0 |= HPRT0_PWR;
335 dwc2_writel(hsotg, hprt0, HPRT0);
336 /* Connect hcd after port power is set. */
337 dwc2_hcd_connect(hsotg);
338 }
339 }
340
341 /**
342 * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
343 *
344 * @hsotg: Programming view of DWC_otg controller
345 *
346 */
dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg * hsotg)347 static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
348 {
349 u32 glpmcfg;
350 u32 i = 0;
351
352 if (hsotg->lx_state != DWC2_L1) {
353 dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
354 return;
355 }
356
357 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
358 if (dwc2_is_device_mode(hsotg)) {
359 dev_dbg(hsotg->dev, "Exit from L1 state\n");
360 glpmcfg &= ~GLPMCFG_ENBLSLPM;
361 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
362 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
363
364 do {
365 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
366
367 if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
368 GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
369 break;
370
371 udelay(1);
372 } while (++i < 200);
373
374 if (i == 200) {
375 dev_err(hsotg->dev, "Failed to exit L1 sleep state in 200us.\n");
376 return;
377 }
378 dwc2_gadget_init_lpm(hsotg);
379 } else {
380 /* TODO */
381 dev_err(hsotg->dev, "Host side LPM is not supported.\n");
382 return;
383 }
384
385 /* Change to L0 state */
386 hsotg->lx_state = DWC2_L0;
387
388 /* Inform gadget to exit from L1 */
389 call_gadget(hsotg, resume);
390 }
391
392 /*
393 * This interrupt indicates that the DWC_otg controller has detected a
394 * resume or remote wakeup sequence. If the DWC_otg controller is in
395 * low power mode, the handler must brings the controller out of low
396 * power mode. The controller automatically begins resume signaling.
397 * The handler schedules a time to stop resume signaling.
398 */
dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg * hsotg)399 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
400 {
401 int ret;
402
403 /* Clear interrupt */
404 dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
405
406 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
407 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
408
409 if (hsotg->lx_state == DWC2_L1) {
410 dwc2_wakeup_from_lpm_l1(hsotg);
411 return;
412 }
413
414 if (dwc2_is_device_mode(hsotg)) {
415 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
416 dwc2_readl(hsotg, DSTS));
417 if (hsotg->lx_state == DWC2_L2) {
418 u32 dctl = dwc2_readl(hsotg, DCTL);
419
420 /* Clear Remote Wakeup Signaling */
421 dctl &= ~DCTL_RMTWKUPSIG;
422 dwc2_writel(hsotg, dctl, DCTL);
423 ret = dwc2_exit_partial_power_down(hsotg, true);
424 if (ret && (ret != -ENOTSUPP))
425 dev_err(hsotg->dev, "exit power_down failed\n");
426
427 /* Change to L0 state */
428 hsotg->lx_state = DWC2_L0;
429 call_gadget(hsotg, resume);
430 } else {
431 /* Change to L0 state */
432 hsotg->lx_state = DWC2_L0;
433 }
434 } else {
435 if (hsotg->params.power_down)
436 return;
437
438 if (hsotg->lx_state != DWC2_L1) {
439 u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
440
441 /* Restart the Phy Clock */
442 pcgcctl &= ~PCGCTL_STOPPCLK;
443 dwc2_writel(hsotg, pcgcctl, PCGCTL);
444
445 /*
446 * If we've got this quirk then the PHY is stuck upon
447 * wakeup. Assert reset. This will propagate out and
448 * eventually we'll re-enumerate the device. Not great
449 * but the best we can do. We can't call phy_reset()
450 * at interrupt time but there's no hurry, so we'll
451 * schedule it for later.
452 */
453 if (hsotg->reset_phy_on_wake)
454 dwc2_host_schedule_phy_reset(hsotg);
455
456 mod_timer(&hsotg->wkp_timer,
457 jiffies + msecs_to_jiffies(71));
458 } else {
459 /* Change to L0 state */
460 hsotg->lx_state = DWC2_L0;
461 }
462 }
463 }
464
465 /*
466 * This interrupt indicates that a device has been disconnected from the
467 * root port
468 */
dwc2_handle_disconnect_intr(struct dwc2_hsotg * hsotg)469 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
470 {
471 dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
472
473 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
474 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
475 dwc2_op_state_str(hsotg));
476
477 if (hsotg->op_state == OTG_STATE_A_HOST)
478 dwc2_hcd_disconnect(hsotg, false);
479 }
480
481 /*
482 * This interrupt indicates that SUSPEND state has been detected on the USB.
483 *
484 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
485 * to "a_host".
486 *
487 * When power management is enabled the core will be put in low power mode.
488 */
dwc2_handle_usb_suspend_intr(struct dwc2_hsotg * hsotg)489 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
490 {
491 u32 dsts;
492 int ret;
493
494 /* Clear interrupt */
495 dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
496
497 dev_dbg(hsotg->dev, "USB SUSPEND\n");
498
499 if (dwc2_is_device_mode(hsotg)) {
500 /*
501 * Check the Device status register to determine if the Suspend
502 * state is active
503 */
504 dsts = dwc2_readl(hsotg, DSTS);
505 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
506 dev_dbg(hsotg->dev,
507 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
508 !!(dsts & DSTS_SUSPSTS),
509 hsotg->hw_params.power_optimized,
510 hsotg->hw_params.hibernation);
511
512 /* Ignore suspend request before enumeration */
513 if (!dwc2_is_device_connected(hsotg)) {
514 dev_dbg(hsotg->dev,
515 "ignore suspend request before enumeration\n");
516 return;
517 }
518 if (dsts & DSTS_SUSPSTS) {
519 if (hsotg->hw_params.power_optimized) {
520 ret = dwc2_enter_partial_power_down(hsotg);
521 if (ret) {
522 if (ret != -ENOTSUPP)
523 dev_err(hsotg->dev,
524 "%s: enter partial_power_down failed\n",
525 __func__);
526 goto skip_power_saving;
527 }
528
529 udelay(100);
530
531 /* Ask phy to be suspended */
532 if (!IS_ERR_OR_NULL(hsotg->uphy))
533 usb_phy_set_suspend(hsotg->uphy, true);
534 }
535
536 if (hsotg->hw_params.hibernation) {
537 ret = dwc2_enter_hibernation(hsotg, 0);
538 if (ret && ret != -ENOTSUPP)
539 dev_err(hsotg->dev,
540 "%s: enter hibernation failed\n",
541 __func__);
542 }
543 skip_power_saving:
544 /*
545 * Change to L2 (suspend) state before releasing
546 * spinlock
547 */
548 hsotg->lx_state = DWC2_L2;
549
550 /* Call gadget suspend callback */
551 call_gadget(hsotg, suspend);
552 }
553 } else {
554 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
555 dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
556
557 /* Change to L2 (suspend) state */
558 hsotg->lx_state = DWC2_L2;
559 /* Clear the a_peripheral flag, back to a_host */
560 spin_unlock(&hsotg->lock);
561 dwc2_hcd_start(hsotg);
562 spin_lock(&hsotg->lock);
563 hsotg->op_state = OTG_STATE_A_HOST;
564 }
565 }
566 }
567
568 /**
569 * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
570 *
571 * @hsotg: Programming view of DWC_otg controller
572 *
573 */
dwc2_handle_lpm_intr(struct dwc2_hsotg * hsotg)574 static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
575 {
576 u32 glpmcfg;
577 u32 pcgcctl;
578 u32 hird;
579 u32 hird_thres;
580 u32 hird_thres_en;
581 u32 enslpm;
582
583 /* Clear interrupt */
584 dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
585
586 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
587
588 if (!(glpmcfg & GLPMCFG_LPMCAP)) {
589 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
590 return;
591 }
592
593 hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
594 hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
595 ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
596 hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
597 enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
598
599 if (dwc2_is_device_mode(hsotg)) {
600 dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
601
602 if (hird_thres_en && hird >= hird_thres) {
603 dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
604 } else if (enslpm) {
605 dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
606 } else {
607 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
608
609 pcgcctl = dwc2_readl(hsotg, PCGCTL);
610 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
611 dwc2_writel(hsotg, pcgcctl, PCGCTL);
612 }
613 /**
614 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
615 */
616 udelay(10);
617
618 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
619
620 if (glpmcfg & GLPMCFG_SLPSTS) {
621 /* Save the current state */
622 hsotg->lx_state = DWC2_L1;
623 dev_dbg(hsotg->dev,
624 "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
625
626 /* Inform gadget that we are in L1 state */
627 call_gadget(hsotg, suspend);
628 }
629 }
630 }
631
632 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
633 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
634 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
635 GINTSTS_USBSUSP | GINTSTS_PRTINT | \
636 GINTSTS_LPMTRANRCVD)
637
638 /*
639 * This function returns the Core Interrupt register
640 */
dwc2_read_common_intr(struct dwc2_hsotg * hsotg)641 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
642 {
643 u32 gintsts;
644 u32 gintmsk;
645 u32 gahbcfg;
646 u32 gintmsk_common = GINTMSK_COMMON;
647
648 gintsts = dwc2_readl(hsotg, GINTSTS);
649 gintmsk = dwc2_readl(hsotg, GINTMSK);
650 gahbcfg = dwc2_readl(hsotg, GAHBCFG);
651
652 /* If any common interrupts set */
653 if (gintsts & gintmsk_common)
654 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
655 gintsts, gintmsk);
656
657 if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
658 return gintsts & gintmsk & gintmsk_common;
659 else
660 return 0;
661 }
662
663 /**
664 * dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect.
665 * Exits hibernation without restoring registers.
666 *
667 * @hsotg: Programming view of DWC_otg controller
668 * @gpwrdn: GPWRDN register
669 */
dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg * hsotg,u32 gpwrdn)670 static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
671 u32 gpwrdn)
672 {
673 u32 gpwrdn_tmp;
674
675 /* Switch-on voltage to the core */
676 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
677 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
678 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
679 udelay(5);
680
681 /* Reset core */
682 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
683 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
684 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
685 udelay(5);
686
687 /* Disable Power Down Clamp */
688 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
689 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
690 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
691 udelay(5);
692
693 /* Deassert reset core */
694 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
695 gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
696 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
697 udelay(5);
698
699 /* Disable PMU interrupt */
700 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
701 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
702 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
703
704 /* De-assert Wakeup Logic */
705 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
706 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
707 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
708
709 hsotg->hibernated = 0;
710
711 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
712 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
713 hsotg->bus_suspended = 0;
714 #endif
715
716 if (gpwrdn & GPWRDN_IDSTS) {
717 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
718 dwc2_core_init(hsotg, false);
719 dwc2_enable_global_interrupts(hsotg);
720 dwc2_hsotg_core_init_disconnected(hsotg, false);
721 dwc2_hsotg_core_connect(hsotg);
722 } else {
723 hsotg->op_state = OTG_STATE_A_HOST;
724
725 /* Initialize the Core for Host mode */
726 dwc2_core_init(hsotg, false);
727 dwc2_enable_global_interrupts(hsotg);
728 dwc2_hcd_start(hsotg);
729 }
730 }
731
732 /*
733 * GPWRDN interrupt handler.
734 *
735 * The GPWRDN interrupts are those that occur in both Host and
736 * Device mode while core is in hibernated state.
737 */
dwc2_handle_gpwrdn_intr(struct dwc2_hsotg * hsotg)738 static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
739 {
740 u32 gpwrdn;
741 int linestate;
742
743 gpwrdn = dwc2_readl(hsotg, GPWRDN);
744 /* clear all interrupt */
745 dwc2_writel(hsotg, gpwrdn, GPWRDN);
746 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
747 dev_dbg(hsotg->dev,
748 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
749 gpwrdn);
750
751 if ((gpwrdn & GPWRDN_DISCONN_DET) &&
752 (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
753 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
754 /*
755 * Call disconnect detect function to exit from
756 * hibernation
757 */
758 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
759 } else if ((gpwrdn & GPWRDN_LNSTSCHG) &&
760 (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
761 dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
762 if (hsotg->hw_params.hibernation &&
763 hsotg->hibernated) {
764 if (gpwrdn & GPWRDN_IDSTS) {
765 dwc2_exit_hibernation(hsotg, 0, 0, 0);
766 call_gadget(hsotg, resume);
767 } else {
768 dwc2_exit_hibernation(hsotg, 1, 0, 1);
769 }
770 }
771 } else if ((gpwrdn & GPWRDN_RST_DET) &&
772 (gpwrdn & GPWRDN_RST_DET_MSK)) {
773 dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
774 if (!linestate && (gpwrdn & GPWRDN_BSESSVLD))
775 dwc2_exit_hibernation(hsotg, 0, 1, 0);
776 } else if ((gpwrdn & GPWRDN_STS_CHGINT) &&
777 (gpwrdn & GPWRDN_STS_CHGINT_MSK)) {
778 dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
779 /*
780 * As GPWRDN_STS_CHGINT exit from hibernation flow is
781 * the same as in GPWRDN_DISCONN_DET flow. Call
782 * disconnect detect helper function to exit from
783 * hibernation.
784 */
785 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
786 }
787 }
788
789 /*
790 * Common interrupt handler
791 *
792 * The common interrupts are those that occur in both Host and Device mode.
793 * This handler handles the following interrupts:
794 * - Mode Mismatch Interrupt
795 * - OTG Interrupt
796 * - Connector ID Status Change Interrupt
797 * - Disconnect Interrupt
798 * - Session Request Interrupt
799 * - Resume / Remote Wakeup Detected Interrupt
800 * - Suspend Interrupt
801 */
dwc2_handle_common_intr(int irq,void * dev)802 irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
803 {
804 struct dwc2_hsotg *hsotg = dev;
805 u32 gintsts;
806 irqreturn_t retval = IRQ_NONE;
807
808 spin_lock(&hsotg->lock);
809
810 if (!dwc2_is_controller_alive(hsotg)) {
811 dev_warn(hsotg->dev, "Controller is dead\n");
812 goto out;
813 }
814
815 /* Reading current frame number value in device or host modes. */
816 if (dwc2_is_device_mode(hsotg))
817 hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
818 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
819 else
820 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
821 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
822
823 gintsts = dwc2_read_common_intr(hsotg);
824 if (gintsts & ~GINTSTS_PRTINT)
825 retval = IRQ_HANDLED;
826
827 /* In case of hibernated state gintsts must not work */
828 if (hsotg->hibernated) {
829 dwc2_handle_gpwrdn_intr(hsotg);
830 retval = IRQ_HANDLED;
831 goto out;
832 }
833
834 if (gintsts & GINTSTS_MODEMIS)
835 dwc2_handle_mode_mismatch_intr(hsotg);
836 if (gintsts & GINTSTS_OTGINT)
837 dwc2_handle_otg_intr(hsotg);
838 if (gintsts & GINTSTS_CONIDSTSCHNG)
839 dwc2_handle_conn_id_status_change_intr(hsotg);
840 if (gintsts & GINTSTS_DISCONNINT)
841 dwc2_handle_disconnect_intr(hsotg);
842 if (gintsts & GINTSTS_SESSREQINT)
843 dwc2_handle_session_req_intr(hsotg);
844 if (gintsts & GINTSTS_WKUPINT)
845 dwc2_handle_wakeup_detected_intr(hsotg);
846 if (gintsts & GINTSTS_USBSUSP)
847 dwc2_handle_usb_suspend_intr(hsotg);
848 if (gintsts & GINTSTS_LPMTRANRCVD)
849 dwc2_handle_lpm_intr(hsotg);
850
851 if (gintsts & GINTSTS_PRTINT) {
852 /*
853 * The port interrupt occurs while in device mode with HPRT0
854 * Port Enable/Disable
855 */
856 if (dwc2_is_device_mode(hsotg)) {
857 dev_dbg(hsotg->dev,
858 " --Port interrupt received in Device mode--\n");
859 dwc2_handle_usb_port_intr(hsotg);
860 retval = IRQ_HANDLED;
861 }
862 }
863
864 out:
865 spin_unlock(&hsotg->lock);
866 return retval;
867 }
868