1// SPDX-License-Identifier: GPL-2.0 2/{ 3 dpe: dpe@E8600000 { 4 compatible = "hisilicon,hi3660-dpe"; 5 status = "ok"; 6 7 reg = <0x0 0xE8600000 0x0 0x80000>, 8 <0x0 0xFFF35000 0 0x1000>, 9 <0x0 0xFFF0A000 0 0x1000>, 10 <0x0 0xFFF31000 0 0x1000>, 11 <0x0 0xE86C0000 0 0x10000>; 12 interrupts = <0 245 4>; 13 14 clocks = <&crg_ctrl HI3660_ACLK_GATE_DSS>, 15 <&crg_ctrl HI3660_PCLK_GATE_DSS>, 16 <&crg_ctrl HI3660_CLK_GATE_EDC0>, 17 <&crg_ctrl HI3660_CLK_GATE_LDI0>, 18 <&crg_ctrl HI3660_CLK_GATE_LDI1>, 19 <&sctrl HI3660_CLK_GATE_DSS_AXI_MM>, 20 <&sctrl HI3660_PCLK_GATE_MMBUF>; 21 clock-names = "aclk_dss", 22 "pclk_dss", 23 "clk_edc0", 24 "clk_ldi0", 25 "clk_ldi1", 26 "clk_dss_axi_mm", 27 "pclk_mmbuf"; 28 29 dma-coherent; 30 31 port { 32 dpe_out: endpoint { 33 remote-endpoint = <&dsi_in>; 34 }; 35 }; 36 37 iommu_info { 38 start-addr = <0x8000>; 39 size = <0xbfff8000>; 40 }; 41 }; 42 43 dsi: dsi@E8601000 { 44 compatible = "hisilicon,hi3660-dsi"; 45 status = "ok"; 46 47 reg = <0 0xE8601000 0 0x7F000>, 48 <0 0xFFF35000 0 0x1000>; 49 50 clocks = <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_REF>, 51 <&crg_ctrl HI3660_CLK_GATE_TXDPHY1_REF>, 52 <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_CFG>, 53 <&crg_ctrl HI3660_CLK_GATE_TXDPHY1_CFG>, 54 <&crg_ctrl HI3660_PCLK_GATE_DSI0>, 55 <&crg_ctrl HI3660_PCLK_GATE_DSI1>; 56 clock-names = "clk_txdphy0_ref", 57 "clk_txdphy1_ref", 58 "clk_txdphy0_cfg", 59 "clk_txdphy1_cfg", 60 "pclk_dsi0", 61 "pclk_dsi1"; 62 63 #address-cells = <1>; 64 #size-cells = <0>; 65 mux-gpio = <&gpio2 4 0>; 66 67 ports { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 port@0 { 72 reg = <0>; 73 dsi_in: endpoint { 74 remote-endpoint = <&dpe_out>; 75 }; 76 }; 77 78 port@1 { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 reg = <1>; 82 83 dsi_out0: endpoint@0 { 84 reg = <0>; 85 remote-endpoint = <&adv7533_in>; 86 }; 87 88 }; 89 }; 90 }; 91}; 92