1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * linux/sound/soc/hisilicon/hi3660-i2s.c
4 *
5 * I2S IP driver for hi3660.
6 *
7 * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
8 */
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/clk.h>
14 #include <linux/jiffies.h>
15 #include <linux/io.h>
16 #include <linux/gpio.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/initval.h>
22 #include <sound/soc.h>
23 #include <linux/interrupt.h>
24 #include <linux/reset.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/reset-controller.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30
31 #include "hi3660-i2s.h"
32
33 struct hi3660_i2s {
34 struct device *dev;
35 struct reset_control *rc;
36 int clocks;
37 struct regulator *regu_asp;
38 struct pinctrl *pctrl;
39 struct pinctrl_state *pin_default;
40 struct pinctrl_state *pin_idle;
41 struct clk *asp_subsys_clk;
42 struct snd_soc_dai_driver dai;
43 void __iomem *base;
44 void __iomem *base_syscon;
45 phys_addr_t base_phys;
46 struct snd_dmaengine_dai_dma_data dma_data[2];
47 spinlock_t lock;
48 int rate;
49 int format;
50 int bits;
51 int channels;
52 u32 master;
53 u32 status;
54 };
55
update_bits(struct hi3660_i2s * i2s,u32 ofs,u32 reset,u32 set)56 static void update_bits(struct hi3660_i2s *i2s, u32 ofs, u32 reset, u32 set)
57 {
58 u32 val = readl(i2s->base + ofs) & ~reset;
59
60 writel(val | set, i2s->base + ofs);
61 }
62
update_bits_syscon(struct hi3660_i2s * i2s,u32 ofs,u32 reset,u32 set)63 static void update_bits_syscon(struct hi3660_i2s *i2s,
64 u32 ofs, u32 reset, u32 set)
65 {
66 u32 val = readl(i2s->base_syscon + ofs) & ~reset;
67
68 writel(val | set, i2s->base_syscon + ofs);
69 }
70
enable_format(struct hi3660_i2s * i2s,struct snd_pcm_substream * substream)71 static int enable_format(struct hi3660_i2s *i2s,
72 struct snd_pcm_substream *substream)
73 {
74 switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
75 case SND_SOC_DAIFMT_CBM_CFM:
76 i2s->master = false;
77 update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
78 0, HI_ASP_CFG_R_CLK_SEL_EN);
79 break;
80 case SND_SOC_DAIFMT_CBS_CFS:
81 i2s->master = true;
82 update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
83 HI_ASP_CFG_R_CLK_SEL_EN, 0);
84 break;
85 default:
86 return -EINVAL;
87 }
88
89 return 0;
90 }
91
startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)92 static int startup(struct snd_pcm_substream *substream,
93 struct snd_soc_dai *cpu_dai)
94 {
95 struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
96
97 /* deassert reset on sio_bt*/
98 update_bits_syscon(i2s, HI_ASP_CFG_R_RST_CTRLDIS_REG,
99 0, BIT(2)|BIT(6)|BIT(8)|BIT(16));
100
101 /* enable clk before frequency division */
102 update_bits_syscon(i2s, HI_ASP_CFG_R_GATE_EN_REG,
103 0, BIT(5)|BIT(6));
104
105 /* enable frequency division */
106 update_bits_syscon(i2s, HI_ASP_CFG_R_GATE_CLKDIV_EN_REG,
107 0, BIT(2)|BIT(5));
108
109 /* select clk */
110 update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
111 HI_ASP_MASK, HI_ASP_CFG_R_CLK_SEL);
112
113 /* select clk_div */
114 update_bits_syscon(i2s, HI_ASP_CFG_R_CLK1_DIV_REG,
115 HI_ASP_MASK, HI_ASP_CFG_R_CLK1_DIV_SEL);
116 update_bits_syscon(i2s, HI_ASP_CFG_R_CLK4_DIV_REG,
117 HI_ASP_MASK, HI_ASP_CFG_R_CLK4_DIV_SEL);
118 update_bits_syscon(i2s, HI_ASP_CFG_R_CLK6_DIV_REG,
119 HI_ASP_MASK, HI_ASP_CFG_R_CLK6_DIV_SEL);
120
121 /* sio config */
122 update_bits(i2s, HI_ASP_SIO_MODE_REG, HI_ASP_MASK, 0x0);
123 update_bits(i2s, HI_ASP_SIO_DATA_WIDTH_SET_REG, HI_ASP_MASK, 0x9);
124 update_bits(i2s, HI_ASP_SIO_I2S_POS_MERGE_EN_REG, HI_ASP_MASK, 0x1);
125 update_bits(i2s, HI_ASP_SIO_I2S_START_POS_REG, HI_ASP_MASK, 0x0);
126
127 return 0;
128 }
129
shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)130 static void shutdown(struct snd_pcm_substream *substream,
131 struct snd_soc_dai *cpu_dai)
132 {
133 struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
134
135 if (!IS_ERR_OR_NULL(i2s->asp_subsys_clk))
136 clk_disable_unprepare(i2s->asp_subsys_clk);
137 }
138
txctrl(struct snd_soc_dai * cpu_dai,int on)139 static void txctrl(struct snd_soc_dai *cpu_dai, int on)
140 {
141 struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
142
143 spin_lock(&i2s->lock);
144
145 if (on) {
146 /* enable SIO TX */
147 update_bits(i2s, HI_ASP_SIO_CT_SET_REG, 0,
148 HI_ASP_SIO_TX_ENABLE |
149 HI_ASP_SIO_TX_DATA_MERGE |
150 HI_ASP_SIO_TX_FIFO_THRESHOLD |
151 HI_ASP_SIO_RX_ENABLE |
152 HI_ASP_SIO_RX_DATA_MERGE |
153 HI_ASP_SIO_RX_FIFO_THRESHOLD);
154 } else {
155 /* disable SIO TX */
156 update_bits(i2s, HI_ASP_SIO_CT_CLR_REG, 0,
157 HI_ASP_SIO_TX_ENABLE | HI_ASP_SIO_RX_ENABLE);
158 }
159 spin_unlock(&i2s->lock);
160 }
161
rxctrl(struct snd_soc_dai * cpu_dai,int on)162 static void rxctrl(struct snd_soc_dai *cpu_dai, int on)
163 {
164 struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
165
166 spin_lock(&i2s->lock);
167 if (on)
168 /* enable SIO RX */
169 update_bits(i2s, HI_ASP_SIO_CT_SET_REG, 0,
170 HI_ASP_SIO_TX_ENABLE |
171 HI_ASP_SIO_TX_DATA_MERGE |
172 HI_ASP_SIO_TX_FIFO_THRESHOLD |
173 HI_ASP_SIO_RX_ENABLE |
174 HI_ASP_SIO_RX_DATA_MERGE |
175 HI_ASP_SIO_RX_FIFO_THRESHOLD);
176 else
177 /* disable SIO RX */
178 update_bits(i2s, HI_ASP_SIO_CT_CLR_REG, 0,
179 HI_ASP_SIO_TX_ENABLE | HI_ASP_SIO_RX_ENABLE);
180 spin_unlock(&i2s->lock);
181 }
182
set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)183 static int set_sysclk(struct snd_soc_dai *cpu_dai,
184 int clk_id, unsigned int freq, int dir)
185 {
186 return 0;
187 }
188
set_format(struct snd_soc_dai * cpu_dai,unsigned int fmt)189 static int set_format(struct snd_soc_dai *cpu_dai, unsigned int fmt)
190 {
191 struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
192
193 i2s->format = fmt;
194 i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
195 SND_SOC_DAIFMT_CBS_CFS;
196
197 return 0;
198 }
199
hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)200 static int hw_params(struct snd_pcm_substream *substream,
201 struct snd_pcm_hw_params *params,
202 struct snd_soc_dai *cpu_dai)
203 {
204 struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
205 struct snd_dmaengine_dai_dma_data *dma_data;
206
207 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
208
209 enable_format(i2s, substream);
210
211 dma_data->maxburst = 4;
212
213 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
214 dma_data->addr = i2s->base_phys +
215 HI_ASP_SIO_I2S_DUAL_TX_CHN_REG;
216 else
217 dma_data->addr = i2s->base_phys +
218 HI_ASP_SIO_I2S_DUAL_RX_CHN_REG;
219
220 switch (params_format(params)) {
221 case SNDRV_PCM_FORMAT_U16_LE:
222 case SNDRV_PCM_FORMAT_S16_LE:
223 i2s->bits = 16;
224 dma_data->addr_width = 4;
225 break;
226
227 case SNDRV_PCM_FORMAT_U24_LE:
228 case SNDRV_PCM_FORMAT_S24_LE:
229 i2s->bits = 32;
230 dma_data->addr_width = 4;
231 break;
232 default:
233 dev_err(cpu_dai->dev, "Bad format\n");
234 return -EINVAL;
235 }
236
237 return 0;
238 }
239
trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)240 static int trigger(struct snd_pcm_substream *substream, int cmd,
241 struct snd_soc_dai *cpu_dai)
242 {
243 switch (cmd) {
244 case SNDRV_PCM_TRIGGER_START:
245 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
246 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
247 rxctrl(cpu_dai, 1);
248 else
249 txctrl(cpu_dai, 1);
250 break;
251 case SNDRV_PCM_TRIGGER_STOP:
252 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
253 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
254 rxctrl(cpu_dai, 0);
255 else
256 txctrl(cpu_dai, 0);
257 break;
258 default:
259 dev_err(cpu_dai->dev, "unknown cmd\n");
260 return -EINVAL;
261 }
262
263 return 0;
264 }
265
dai_probe(struct snd_soc_dai * dai)266 static int dai_probe(struct snd_soc_dai *dai)
267 {
268 struct hi3660_i2s *i2s = snd_soc_dai_get_drvdata(dai);
269
270 snd_soc_dai_init_dma_data(dai,
271 &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
272 &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
273
274 return 0;
275 }
276
277
278 static struct snd_soc_dai_ops dai_ops = {
279 .trigger = trigger,
280 .hw_params = hw_params,
281 .set_fmt = set_format,
282 .set_sysclk = set_sysclk,
283 .startup = startup,
284 .shutdown = shutdown,
285 };
286
287 static struct snd_soc_dai_driver dai_init = {
288 .name = "hi3660_i2s",
289 .probe = dai_probe,
290 .playback = {
291 .channels_min = 2,
292 .channels_max = 2,
293 .formats = SNDRV_PCM_FMTBIT_S16_LE |
294 SNDRV_PCM_FMTBIT_U16_LE,
295 .rates = SNDRV_PCM_RATE_48000,
296 },
297 .capture = {
298 .channels_min = 2,
299 .channels_max = 2,
300 .formats = SNDRV_PCM_FMTBIT_S16_LE |
301 SNDRV_PCM_FMTBIT_U16_LE,
302 .rates = SNDRV_PCM_RATE_48000,
303 },
304 .ops = &dai_ops,
305 };
306
307 static const struct snd_soc_component_driver component_driver = {
308 .name = "hi3660_i2s",
309 };
310
311 #include <sound/dmaengine_pcm.h>
312
313 static const struct snd_pcm_hardware sound_hardware = {
314 .info = SNDRV_PCM_INFO_MMAP |
315 SNDRV_PCM_INFO_MMAP_VALID |
316 SNDRV_PCM_INFO_PAUSE |
317 SNDRV_PCM_INFO_RESUME |
318 SNDRV_PCM_INFO_INTERLEAVED |
319 SNDRV_PCM_INFO_HALF_DUPLEX,
320 .period_bytes_min = 4096,
321 .period_bytes_max = 4096,
322 .periods_min = 4,
323 .periods_max = UINT_MAX,
324 .buffer_bytes_max = SIZE_MAX,
325 };
326
327 static const struct snd_dmaengine_pcm_config dmaengine_pcm_config = {
328 .pcm_hardware = &sound_hardware,
329 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
330 .prealloc_buffer_size = 64 * 1024,
331 };
332
hi3660_i2s_probe(struct platform_device * pdev)333 static int hi3660_i2s_probe(struct platform_device *pdev)
334 {
335 struct device *dev = &pdev->dev;
336 struct hi3660_i2s *i2s;
337 struct resource *res;
338 int ret;
339
340 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
341 if (!i2s)
342 return -ENOMEM;
343
344 i2s->dev = dev;
345 spin_lock_init(&i2s->lock);
346
347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
348 if (!res) {
349 ret = -ENODEV;
350 return ret;
351 }
352 i2s->base_phys = (phys_addr_t)res->start;
353
354 i2s->dai = dai_init;
355 dev_set_drvdata(&pdev->dev, i2s);
356
357 i2s->base = devm_ioremap_resource(dev, res);
358 if (IS_ERR(i2s->base)) {
359 dev_err(&pdev->dev, "ioremap failed\n");
360 ret = PTR_ERR(i2s->base);
361 return ret;
362 }
363
364 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
365 if (!res) {
366 ret = -ENODEV;
367 return ret;
368 }
369 i2s->base_syscon = devm_ioremap(dev, res->start, resource_size(res));
370 if (IS_ERR(i2s->base_syscon)) {
371 dev_err(&pdev->dev, "ioremap failed\n");
372 ret = PTR_ERR(i2s->base_syscon);
373 return ret;
374 }
375
376 /* i2s iomux config */
377 i2s->pctrl = devm_pinctrl_get(dev);
378 if (IS_ERR(i2s->pctrl)) {
379 dev_err(dev, "could not get pinctrl\n");
380 ret = -EIO;
381 return ret;
382 }
383
384 i2s->pin_default = pinctrl_lookup_state(i2s->pctrl,
385 PINCTRL_STATE_DEFAULT);
386 if (IS_ERR(i2s->pin_default)) {
387 dev_err(dev,
388 "could not get default state (%li)\n",
389 PTR_ERR(i2s->pin_default));
390 ret = -EIO;
391 return ret;
392 }
393
394 if (pinctrl_select_state(i2s->pctrl, i2s->pin_default)) {
395 dev_err(dev, "could not set pins to default state\n");
396 ret = -EIO;
397 return ret;
398 }
399
400 ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
401 &dmaengine_pcm_config, 0);
402 if (ret)
403 return ret;
404
405 ret = snd_soc_register_component(&pdev->dev, &component_driver,
406 &i2s->dai, 1);
407 if (ret) {
408 dev_err(&pdev->dev, "Failed to register dai\n");
409 return ret;
410 }
411
412 return 0;
413 }
414
hi3660_i2s_remove(struct platform_device * pdev)415 static int hi3660_i2s_remove(struct platform_device *pdev)
416 {
417 struct hi3660_i2s *i2s = dev_get_drvdata(&pdev->dev);
418
419 snd_soc_unregister_component(&pdev->dev);
420 dev_set_drvdata(&pdev->dev, NULL);
421
422 pinctrl_put(i2s->pctrl);
423
424 return 0;
425 }
426
427 static const struct of_device_id dt_ids[] = {
428 { .compatible = "hisilicon,hi3660-i2s-1.0" },
429 { /* sentinel */ }
430 };
431
432 MODULE_DEVICE_TABLE(of, dt_ids);
433
434 static struct platform_driver local_platform_driver = {
435 .probe = hi3660_i2s_probe,
436 .remove = hi3660_i2s_remove,
437 .driver = {
438 .name = "hi3660_i2s",
439 .owner = THIS_MODULE,
440 .of_match_table = dt_ids,
441 },
442 };
443
444 module_platform_driver(local_platform_driver);
445
446 MODULE_DESCRIPTION("Hisilicon I2S driver");
447 MODULE_AUTHOR("Guangke Ji <j00209069@notesmail.huawei.com>");
448 MODULE_LICENSE("GPL");
449