124 	if (DISPLAY_VER(dev_priv) >= 12) {  in psr_irq_control()
190 	if (DISPLAY_VER(dev_priv) >= 12) {  in intel_psr_irq_handler()
211 		if (DISPLAY_VER(dev_priv) >= 9) {  in intel_psr_irq_handler()
339 	if (DISPLAY_VER(dev_priv) >= 9 &&  in intel_psr_init_dpcd()
419 		if (DISPLAY_VER(dev_priv) >= 8)  in intel_psr_enable_sink()
436 	if (DISPLAY_VER(dev_priv) >= 11)  in intel_psr1_get_tp_time()
507 	if (DISPLAY_VER(dev_priv) >= 8)  in hsw_activate_psr1()
546 	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)  in hsw_activate_psr2()
552 	if (DISPLAY_VER(dev_priv) >= 12) {  in hsw_activate_psr2()
585 	} else if (DISPLAY_VER(dev_priv) >= 12) {  in hsw_activate_psr2()
588 	} else if (DISPLAY_VER(dev_priv) >= 9) {  in hsw_activate_psr2()
623 	if (DISPLAY_VER(dev_priv) < 9)  in transcoder_has_psr2()
625 	else if (DISPLAY_VER(dev_priv) >= 12)  in transcoder_has_psr2()
836 	if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)  in _compute_psr2_sdp_prior_scanline_indication()
850 	if (DISPLAY_VER(i915) >= 12) {  in _compute_psr2_wake_times()
945 	if (DISPLAY_VER(dev_priv) >= 12) {  in intel_psr2_config_valid()
949 	} else if (DISPLAY_VER(dev_priv) >= 10) {  in intel_psr2_config_valid()
953 	} else if (DISPLAY_VER(dev_priv) == 9) {  in intel_psr2_config_valid()
1116 	if (DISPLAY_VER(dev_priv) >= 12) {  in intel_psr_get_config()
1160 	if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {  in intel_psr_enable_source()
1180 	if (DISPLAY_VER(dev_priv) < 11)  in intel_psr_enable_source()
1229 	if (DISPLAY_VER(dev_priv) >= 12) {  in psr_interrupt_error_check()
1500 	if (DISPLAY_VER(dev_priv) >= 9)  in psr_force_hw_tracking_exit()
1857 		else if (DISPLAY_VER(dev_priv) < 9 && psr->enabled) {  in intel_psr_update()
2270 	if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {  in intel_psr_init()
2287 		if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable)  in intel_psr_init()
2294 	else if (DISPLAY_VER(dev_priv) < 12)  in intel_psr_init()