1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_damage_helper.h>
26
27 #include "display/intel_dp.h"
28
29 #include "i915_drv.h"
30 #include "intel_atomic.h"
31 #include "intel_de.h"
32 #include "intel_display_types.h"
33 #include "intel_dp_aux.h"
34 #include "intel_hdmi.h"
35 #include "intel_psr.h"
36 #include "intel_snps_phy.h"
37 #include "intel_sprite.h"
38 #include "skl_universal_plane.h"
39
40 /**
41 * DOC: Panel Self Refresh (PSR/SRD)
42 *
43 * Since Haswell Display controller supports Panel Self-Refresh on display
44 * panels witch have a remote frame buffer (RFB) implemented according to PSR
45 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
46 * when system is idle but display is on as it eliminates display refresh
47 * request to DDR memory completely as long as the frame buffer for that
48 * display is unchanged.
49 *
50 * Panel Self Refresh must be supported by both Hardware (source) and
51 * Panel (sink).
52 *
53 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
54 * to power down the link and memory controller. For DSI panels the same idea
55 * is called "manual mode".
56 *
57 * The implementation uses the hardware-based PSR support which automatically
58 * enters/exits self-refresh mode. The hardware takes care of sending the
59 * required DP aux message and could even retrain the link (that part isn't
60 * enabled yet though). The hardware also keeps track of any frontbuffer
61 * changes to know when to exit self-refresh mode again. Unfortunately that
62 * part doesn't work too well, hence why the i915 PSR support uses the
63 * software frontbuffer tracking to make sure it doesn't miss a screen
64 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
65 * get called by the frontbuffer tracking code. Note that because of locking
66 * issues the self-refresh re-enable code is done from a work queue, which
67 * must be correctly synchronized/cancelled when shutting down the pipe."
68 *
69 * DC3CO (DC3 clock off)
70 *
71 * On top of PSR2, GEN12 adds a intermediate power savings state that turns
72 * clock off automatically during PSR2 idle state.
73 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
74 * entry/exit allows the HW to enter a low-power state even when page flipping
75 * periodically (for instance a 30fps video playback scenario).
76 *
77 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
78 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
79 * frames, if no other flip occurs and the function above is executed, DC3CO is
80 * disabled and PSR2 is configured to enter deep sleep, resetting again in case
81 * of another flip.
82 * Front buffer modifications do not trigger DC3CO activation on purpose as it
83 * would bring a lot of complexity and most of the moderns systems will only
84 * use page flips.
85 */
86
psr_global_enabled(struct intel_dp * intel_dp)87 static bool psr_global_enabled(struct intel_dp *intel_dp)
88 {
89 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
90
91 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
92 case I915_PSR_DEBUG_DEFAULT:
93 return i915->params.enable_psr;
94 case I915_PSR_DEBUG_DISABLE:
95 return false;
96 default:
97 return true;
98 }
99 }
100
psr2_global_enabled(struct intel_dp * intel_dp)101 static bool psr2_global_enabled(struct intel_dp *intel_dp)
102 {
103 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
104 case I915_PSR_DEBUG_DISABLE:
105 case I915_PSR_DEBUG_FORCE_PSR1:
106 return false;
107 default:
108 return true;
109 }
110 }
111
psr_irq_control(struct intel_dp * intel_dp)112 static void psr_irq_control(struct intel_dp *intel_dp)
113 {
114 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
115 enum transcoder trans_shift;
116 i915_reg_t imr_reg;
117 u32 mask, val;
118
119 /*
120 * gen12+ has registers relative to transcoder and one per transcoder
121 * using the same bit definition: handle it as TRANSCODER_EDP to force
122 * 0 shift in bit definition
123 */
124 if (DISPLAY_VER(dev_priv) >= 12) {
125 trans_shift = 0;
126 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
127 } else {
128 trans_shift = intel_dp->psr.transcoder;
129 imr_reg = EDP_PSR_IMR;
130 }
131
132 mask = EDP_PSR_ERROR(trans_shift);
133 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
134 mask |= EDP_PSR_POST_EXIT(trans_shift) |
135 EDP_PSR_PRE_ENTRY(trans_shift);
136
137 /* Warning: it is masking/setting reserved bits too */
138 val = intel_de_read(dev_priv, imr_reg);
139 val &= ~EDP_PSR_TRANS_MASK(trans_shift);
140 val |= ~mask;
141 intel_de_write(dev_priv, imr_reg, val);
142 }
143
psr_event_print(struct drm_i915_private * i915,u32 val,bool psr2_enabled)144 static void psr_event_print(struct drm_i915_private *i915,
145 u32 val, bool psr2_enabled)
146 {
147 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
148 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
149 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
150 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
151 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
152 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
153 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
154 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
155 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n");
156 if (val & PSR_EVENT_GRAPHICS_RESET)
157 drm_dbg_kms(&i915->drm, "\tGraphics reset\n");
158 if (val & PSR_EVENT_PCH_INTERRUPT)
159 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n");
160 if (val & PSR_EVENT_MEMORY_UP)
161 drm_dbg_kms(&i915->drm, "\tMemory up\n");
162 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
163 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n");
164 if (val & PSR_EVENT_WD_TIMER_EXPIRE)
165 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n");
166 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
167 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n");
168 if (val & PSR_EVENT_REGISTER_UPDATE)
169 drm_dbg_kms(&i915->drm, "\tRegister updated\n");
170 if (val & PSR_EVENT_HDCP_ENABLE)
171 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n");
172 if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
173 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n");
174 if (val & PSR_EVENT_VBI_ENABLE)
175 drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
176 if (val & PSR_EVENT_LPSP_MODE_EXIT)
177 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
178 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
179 drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
180 }
181
intel_psr_irq_handler(struct intel_dp * intel_dp,u32 psr_iir)182 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
183 {
184 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
185 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
186 ktime_t time_ns = ktime_get();
187 enum transcoder trans_shift;
188 i915_reg_t imr_reg;
189
190 if (DISPLAY_VER(dev_priv) >= 12) {
191 trans_shift = 0;
192 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
193 } else {
194 trans_shift = intel_dp->psr.transcoder;
195 imr_reg = EDP_PSR_IMR;
196 }
197
198 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
199 intel_dp->psr.last_entry_attempt = time_ns;
200 drm_dbg_kms(&dev_priv->drm,
201 "[transcoder %s] PSR entry attempt in 2 vblanks\n",
202 transcoder_name(cpu_transcoder));
203 }
204
205 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
206 intel_dp->psr.last_exit = time_ns;
207 drm_dbg_kms(&dev_priv->drm,
208 "[transcoder %s] PSR exit completed\n",
209 transcoder_name(cpu_transcoder));
210
211 if (DISPLAY_VER(dev_priv) >= 9) {
212 u32 val = intel_de_read(dev_priv,
213 PSR_EVENT(cpu_transcoder));
214 bool psr2_enabled = intel_dp->psr.psr2_enabled;
215
216 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
217 val);
218 psr_event_print(dev_priv, val, psr2_enabled);
219 }
220 }
221
222 if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
223 u32 val;
224
225 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
226 transcoder_name(cpu_transcoder));
227
228 intel_dp->psr.irq_aux_error = true;
229
230 /*
231 * If this interruption is not masked it will keep
232 * interrupting so fast that it prevents the scheduled
233 * work to run.
234 * Also after a PSR error, we don't want to arm PSR
235 * again so we don't care about unmask the interruption
236 * or unset irq_aux_error.
237 */
238 val = intel_de_read(dev_priv, imr_reg);
239 val |= EDP_PSR_ERROR(trans_shift);
240 intel_de_write(dev_priv, imr_reg, val);
241
242 schedule_work(&intel_dp->psr.work);
243 }
244 }
245
intel_dp_get_alpm_status(struct intel_dp * intel_dp)246 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
247 {
248 u8 alpm_caps = 0;
249
250 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
251 &alpm_caps) != 1)
252 return false;
253 return alpm_caps & DP_ALPM_CAP;
254 }
255
intel_dp_get_sink_sync_latency(struct intel_dp * intel_dp)256 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
257 {
258 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
259 u8 val = 8; /* assume the worst if we can't read the value */
260
261 if (drm_dp_dpcd_readb(&intel_dp->aux,
262 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
263 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
264 else
265 drm_dbg_kms(&i915->drm,
266 "Unable to get sink synchronization latency, assuming 8 frames\n");
267 return val;
268 }
269
intel_dp_get_su_granularity(struct intel_dp * intel_dp)270 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
271 {
272 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
273 ssize_t r;
274 u16 w;
275 u8 y;
276
277 /* If sink don't have specific granularity requirements set legacy ones */
278 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
279 /* As PSR2 HW sends full lines, we do not care about x granularity */
280 w = 4;
281 y = 4;
282 goto exit;
283 }
284
285 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
286 if (r != 2)
287 drm_dbg_kms(&i915->drm,
288 "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
289 /*
290 * Spec says that if the value read is 0 the default granularity should
291 * be used instead.
292 */
293 if (r != 2 || w == 0)
294 w = 4;
295
296 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
297 if (r != 1) {
298 drm_dbg_kms(&i915->drm,
299 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
300 y = 4;
301 }
302 if (y == 0)
303 y = 1;
304
305 exit:
306 intel_dp->psr.su_w_granularity = w;
307 intel_dp->psr.su_y_granularity = y;
308 }
309
intel_psr_init_dpcd(struct intel_dp * intel_dp)310 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
311 {
312 struct drm_i915_private *dev_priv =
313 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
314
315 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
316 sizeof(intel_dp->psr_dpcd));
317
318 if (!intel_dp->psr_dpcd[0])
319 return;
320 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
321 intel_dp->psr_dpcd[0]);
322
323 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
324 drm_dbg_kms(&dev_priv->drm,
325 "PSR support not currently available for this panel\n");
326 return;
327 }
328
329 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
330 drm_dbg_kms(&dev_priv->drm,
331 "Panel lacks power state control, PSR cannot be enabled\n");
332 return;
333 }
334
335 intel_dp->psr.sink_support = true;
336 intel_dp->psr.sink_sync_latency =
337 intel_dp_get_sink_sync_latency(intel_dp);
338
339 if (DISPLAY_VER(dev_priv) >= 9 &&
340 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
341 bool y_req = intel_dp->psr_dpcd[1] &
342 DP_PSR2_SU_Y_COORDINATE_REQUIRED;
343 bool alpm = intel_dp_get_alpm_status(intel_dp);
344
345 /*
346 * All panels that supports PSR version 03h (PSR2 +
347 * Y-coordinate) can handle Y-coordinates in VSC but we are
348 * only sure that it is going to be used when required by the
349 * panel. This way panel is capable to do selective update
350 * without a aux frame sync.
351 *
352 * To support PSR version 02h and PSR version 03h without
353 * Y-coordinate requirement panels we would need to enable
354 * GTC first.
355 */
356 intel_dp->psr.sink_psr2_support = y_req && alpm;
357 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
358 intel_dp->psr.sink_psr2_support ? "" : "not ");
359
360 if (intel_dp->psr.sink_psr2_support) {
361 intel_dp->psr.colorimetry_support =
362 intel_dp_get_colorimetry_status(intel_dp);
363 intel_dp_get_su_granularity(intel_dp);
364 }
365 }
366 }
367
hsw_psr_setup_aux(struct intel_dp * intel_dp)368 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
369 {
370 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
371 u32 aux_clock_divider, aux_ctl;
372 int i;
373 static const u8 aux_msg[] = {
374 [0] = DP_AUX_NATIVE_WRITE << 4,
375 [1] = DP_SET_POWER >> 8,
376 [2] = DP_SET_POWER & 0xff,
377 [3] = 1 - 1,
378 [4] = DP_SET_POWER_D0,
379 };
380 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
381 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
382 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
383 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
384
385 BUILD_BUG_ON(sizeof(aux_msg) > 20);
386 for (i = 0; i < sizeof(aux_msg); i += 4)
387 intel_de_write(dev_priv,
388 EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2),
389 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
390
391 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
392
393 /* Start with bits set for DDI_AUX_CTL register */
394 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
395 aux_clock_divider);
396
397 /* Select only valid bits for SRD_AUX_CTL */
398 aux_ctl &= psr_aux_mask;
399 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder),
400 aux_ctl);
401 }
402
intel_psr_enable_sink(struct intel_dp * intel_dp)403 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
404 {
405 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
406 u8 dpcd_val = DP_PSR_ENABLE;
407
408 /* Enable ALPM at sink for psr2 */
409 if (intel_dp->psr.psr2_enabled) {
410 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
411 DP_ALPM_ENABLE |
412 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
413
414 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
415 } else {
416 if (intel_dp->psr.link_standby)
417 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
418
419 if (DISPLAY_VER(dev_priv) >= 8)
420 dpcd_val |= DP_PSR_CRC_VERIFICATION;
421 }
422
423 if (intel_dp->psr.req_psr2_sdp_prior_scanline)
424 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
425
426 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
427
428 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
429 }
430
intel_psr1_get_tp_time(struct intel_dp * intel_dp)431 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
432 {
433 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
434 u32 val = 0;
435
436 if (DISPLAY_VER(dev_priv) >= 11)
437 val |= EDP_PSR_TP4_TIME_0US;
438
439 if (dev_priv->params.psr_safest_params) {
440 val |= EDP_PSR_TP1_TIME_2500us;
441 val |= EDP_PSR_TP2_TP3_TIME_2500us;
442 goto check_tp3_sel;
443 }
444
445 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
446 val |= EDP_PSR_TP1_TIME_0us;
447 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
448 val |= EDP_PSR_TP1_TIME_100us;
449 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
450 val |= EDP_PSR_TP1_TIME_500us;
451 else
452 val |= EDP_PSR_TP1_TIME_2500us;
453
454 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
455 val |= EDP_PSR_TP2_TP3_TIME_0us;
456 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
457 val |= EDP_PSR_TP2_TP3_TIME_100us;
458 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
459 val |= EDP_PSR_TP2_TP3_TIME_500us;
460 else
461 val |= EDP_PSR_TP2_TP3_TIME_2500us;
462
463 check_tp3_sel:
464 if (intel_dp_source_supports_hbr2(intel_dp) &&
465 drm_dp_tps3_supported(intel_dp->dpcd))
466 val |= EDP_PSR_TP1_TP3_SEL;
467 else
468 val |= EDP_PSR_TP1_TP2_SEL;
469
470 return val;
471 }
472
psr_compute_idle_frames(struct intel_dp * intel_dp)473 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
474 {
475 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
476 int idle_frames;
477
478 /* Let's use 6 as the minimum to cover all known cases including the
479 * off-by-one issue that HW has in some cases.
480 */
481 idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
482 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
483
484 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
485 idle_frames = 0xf;
486
487 return idle_frames;
488 }
489
hsw_activate_psr1(struct intel_dp * intel_dp)490 static void hsw_activate_psr1(struct intel_dp *intel_dp)
491 {
492 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
493 u32 max_sleep_time = 0x1f;
494 u32 val = EDP_PSR_ENABLE;
495
496 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
497
498 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
499 if (IS_HASWELL(dev_priv))
500 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
501
502 if (intel_dp->psr.link_standby)
503 val |= EDP_PSR_LINK_STANDBY;
504
505 val |= intel_psr1_get_tp_time(intel_dp);
506
507 if (DISPLAY_VER(dev_priv) >= 8)
508 val |= EDP_PSR_CRC_ENABLE;
509
510 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
511 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
512 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
513 }
514
intel_psr2_get_tp_time(struct intel_dp * intel_dp)515 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
516 {
517 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
518 u32 val = 0;
519
520 if (dev_priv->params.psr_safest_params)
521 return EDP_PSR2_TP2_TIME_2500us;
522
523 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
524 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
525 val |= EDP_PSR2_TP2_TIME_50us;
526 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
527 val |= EDP_PSR2_TP2_TIME_100us;
528 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
529 val |= EDP_PSR2_TP2_TIME_500us;
530 else
531 val |= EDP_PSR2_TP2_TIME_2500us;
532
533 return val;
534 }
535
hsw_activate_psr2(struct intel_dp * intel_dp)536 static void hsw_activate_psr2(struct intel_dp *intel_dp)
537 {
538 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
539 u32 val = EDP_PSR2_ENABLE;
540
541 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
542
543 if (!IS_ALDERLAKE_P(dev_priv))
544 val |= EDP_SU_TRACK_ENABLE;
545
546 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
547 val |= EDP_Y_COORDINATE_ENABLE;
548
549 val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
550 val |= intel_psr2_get_tp_time(intel_dp);
551
552 if (DISPLAY_VER(dev_priv) >= 12) {
553 if (intel_dp->psr.io_wake_lines < 9 &&
554 intel_dp->psr.fast_wake_lines < 9)
555 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
556 else
557 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
558 }
559
560 /* Wa_22012278275:adl-p */
561 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
562 static const u8 map[] = {
563 2, /* 5 lines */
564 1, /* 6 lines */
565 0, /* 7 lines */
566 3, /* 8 lines */
567 6, /* 9 lines */
568 5, /* 10 lines */
569 4, /* 11 lines */
570 7, /* 12 lines */
571 };
572 /*
573 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
574 * comments bellow for more information
575 */
576 u32 tmp;
577
578 tmp = map[intel_dp->psr.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
579 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
580 val |= tmp;
581
582 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
583 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
584 val |= tmp;
585 } else if (DISPLAY_VER(dev_priv) >= 12) {
586 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
587 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
588 } else if (DISPLAY_VER(dev_priv) >= 9) {
589 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
590 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
591 }
592
593 if (intel_dp->psr.req_psr2_sdp_prior_scanline)
594 val |= EDP_PSR2_SU_SDP_SCANLINE;
595
596 if (intel_dp->psr.psr2_sel_fetch_enabled) {
597 /* Wa_1408330847 */
598 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
599 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
600 DIS_RAM_BYPASS_PSR2_MAN_TRACK,
601 DIS_RAM_BYPASS_PSR2_MAN_TRACK);
602
603 intel_de_write(dev_priv,
604 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
605 PSR2_MAN_TRK_CTL_ENABLE);
606 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
607 intel_de_write(dev_priv,
608 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
609 }
610
611 /*
612 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
613 * recommending keep this bit unset while PSR2 is enabled.
614 */
615 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);
616
617 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
618 }
619
620 static bool
transcoder_has_psr2(struct drm_i915_private * dev_priv,enum transcoder trans)621 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
622 {
623 if (DISPLAY_VER(dev_priv) < 9)
624 return false;
625 else if (DISPLAY_VER(dev_priv) >= 12)
626 return trans == TRANSCODER_A;
627 else
628 return trans == TRANSCODER_EDP;
629 }
630
intel_get_frame_time_us(const struct intel_crtc_state * cstate)631 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
632 {
633 if (!cstate || !cstate->hw.active)
634 return 0;
635
636 return DIV_ROUND_UP(1000 * 1000,
637 drm_mode_vrefresh(&cstate->hw.adjusted_mode));
638 }
639
psr2_program_idle_frames(struct intel_dp * intel_dp,u32 idle_frames)640 static void psr2_program_idle_frames(struct intel_dp *intel_dp,
641 u32 idle_frames)
642 {
643 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
644 u32 val;
645
646 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
647 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));
648 val &= ~EDP_PSR2_IDLE_FRAME_MASK;
649 val |= idle_frames;
650 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
651 }
652
tgl_psr2_enable_dc3co(struct intel_dp * intel_dp)653 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
654 {
655 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
656
657 psr2_program_idle_frames(intel_dp, 0);
658 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
659 }
660
tgl_psr2_disable_dc3co(struct intel_dp * intel_dp)661 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
662 {
663 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
664
665 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
666 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
667 }
668
tgl_dc3co_disable_work(struct work_struct * work)669 static void tgl_dc3co_disable_work(struct work_struct *work)
670 {
671 struct intel_dp *intel_dp =
672 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
673
674 mutex_lock(&intel_dp->psr.lock);
675 /* If delayed work is pending, it is not idle */
676 if (delayed_work_pending(&intel_dp->psr.dc3co_work))
677 goto unlock;
678
679 tgl_psr2_disable_dc3co(intel_dp);
680 unlock:
681 mutex_unlock(&intel_dp->psr.lock);
682 }
683
tgl_disallow_dc3co_on_psr2_exit(struct intel_dp * intel_dp)684 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
685 {
686 if (!intel_dp->psr.dc3co_exitline)
687 return;
688
689 cancel_delayed_work(&intel_dp->psr.dc3co_work);
690 /* Before PSR2 exit disallow dc3co*/
691 tgl_psr2_disable_dc3co(intel_dp);
692 }
693
694 static bool
dc3co_is_pipe_port_compatible(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)695 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
696 struct intel_crtc_state *crtc_state)
697 {
698 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
699 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
700 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
701 enum port port = dig_port->base.port;
702
703 if (IS_ALDERLAKE_P(dev_priv))
704 return pipe <= PIPE_B && port <= PORT_B;
705 else
706 return pipe == PIPE_A && port == PORT_A;
707 }
708
709 static void
tgl_dc3co_exitline_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)710 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
711 struct intel_crtc_state *crtc_state)
712 {
713 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
714 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
715 u32 exit_scanlines;
716
717 /*
718 * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
719 * disable DC3CO until the changed dc3co activating/deactivating sequence
720 * is applied. B.Specs:49196
721 */
722 return;
723
724 /*
725 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
726 * TODO: when the issue is addressed, this restriction should be removed.
727 */
728 if (crtc_state->enable_psr2_sel_fetch)
729 return;
730
731 if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
732 return;
733
734 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
735 return;
736
737 /* Wa_16011303918:adl-p */
738 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
739 return;
740
741 /*
742 * DC3CO Exit time 200us B.Spec 49196
743 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
744 */
745 exit_scanlines =
746 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
747
748 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
749 return;
750
751 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
752 }
753
intel_psr2_sel_fetch_config_valid(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)754 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
755 struct intel_crtc_state *crtc_state)
756 {
757 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
758
759 if (!dev_priv->params.enable_psr2_sel_fetch &&
760 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
761 drm_dbg_kms(&dev_priv->drm,
762 "PSR2 sel fetch not enabled, disabled by parameter\n");
763 return false;
764 }
765
766 if (crtc_state->uapi.async_flip) {
767 drm_dbg_kms(&dev_priv->drm,
768 "PSR2 sel fetch not enabled, async flip enabled\n");
769 return false;
770 }
771
772 /* Wa_14010254185 Wa_14010103792 */
773 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
774 drm_dbg_kms(&dev_priv->drm,
775 "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
776 return false;
777 }
778
779 return crtc_state->enable_psr2_sel_fetch = true;
780 }
781
psr2_granularity_check(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)782 static bool psr2_granularity_check(struct intel_dp *intel_dp,
783 struct intel_crtc_state *crtc_state)
784 {
785 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
786 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
787 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
788 u16 y_granularity = 0;
789
790 /* PSR2 HW only send full lines so we only need to validate the width */
791 if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
792 return false;
793
794 if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
795 return false;
796
797 /* HW tracking is only aligned to 4 lines */
798 if (!crtc_state->enable_psr2_sel_fetch)
799 return intel_dp->psr.su_y_granularity == 4;
800
801 /*
802 * adl_p has 1 line granularity. For other platforms with SW tracking we
803 * can adjust the y coordinates to match sink requirement if multiple of
804 * 4.
805 */
806 if (IS_ALDERLAKE_P(dev_priv))
807 y_granularity = intel_dp->psr.su_y_granularity;
808 else if (intel_dp->psr.su_y_granularity <= 2)
809 y_granularity = 4;
810 else if ((intel_dp->psr.su_y_granularity % 4) == 0)
811 y_granularity = intel_dp->psr.su_y_granularity;
812
813 if (y_granularity == 0 || crtc_vdisplay % y_granularity)
814 return false;
815
816 crtc_state->su_y_granularity = y_granularity;
817 return true;
818 }
819
_compute_psr2_sdp_prior_scanline_indication(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)820 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
821 struct intel_crtc_state *crtc_state)
822 {
823 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
824 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
825 u32 hblank_total, hblank_ns, req_ns;
826
827 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
828 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
829
830 /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */
831 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000);
832
833 if ((hblank_ns - req_ns) > 100)
834 return true;
835
836 if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
837 return false;
838
839 crtc_state->req_psr2_sdp_prior_scanline = true;
840 return true;
841 }
842
_compute_psr2_wake_times(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)843 static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
844 struct intel_crtc_state *crtc_state)
845 {
846 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
847 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
848 u8 max_wake_lines;
849
850 if (DISPLAY_VER(i915) >= 12) {
851 io_wake_time = 42;
852 /*
853 * According to Bspec it's 42us, but based on testing
854 * it is not enough -> use 45 us.
855 */
856 fast_wake_time = 45;
857 max_wake_lines = 12;
858 } else {
859 io_wake_time = 50;
860 fast_wake_time = 32;
861 max_wake_lines = 8;
862 }
863
864 io_wake_lines = intel_usecs_to_scanlines(
865 &crtc_state->hw.adjusted_mode, io_wake_time);
866 fast_wake_lines = intel_usecs_to_scanlines(
867 &crtc_state->hw.adjusted_mode, fast_wake_time);
868
869 if (io_wake_lines > max_wake_lines ||
870 fast_wake_lines > max_wake_lines)
871 return false;
872
873 if (i915->params.psr_safest_params)
874 io_wake_lines = fast_wake_lines = max_wake_lines;
875
876 /* According to Bspec lower limit should be set as 7 lines. */
877 intel_dp->psr.io_wake_lines = max(io_wake_lines, 7);
878 intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7);
879
880 return true;
881 }
882
intel_psr2_config_valid(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)883 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
884 struct intel_crtc_state *crtc_state)
885 {
886 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
887 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
888 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
889 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
890
891 if (!intel_dp->psr.sink_psr2_support)
892 return false;
893
894 /* JSL and EHL only supports eDP 1.3 */
895 if (IS_JSL_EHL(dev_priv)) {
896 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
897 return false;
898 }
899
900 /* Wa_16011181250 */
901 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
902 IS_DG2(dev_priv)) {
903 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n");
904 return false;
905 }
906
907 /*
908 * We are missing the implementation of some workarounds to enabled PSR2
909 * in Alderlake_P, until ready PSR2 should be kept disabled.
910 */
911 if (IS_ALDERLAKE_P(dev_priv)) {
912 drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n");
913 return false;
914 }
915
916 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
917 drm_dbg_kms(&dev_priv->drm,
918 "PSR2 not supported in transcoder %s\n",
919 transcoder_name(crtc_state->cpu_transcoder));
920 return false;
921 }
922
923 if (!psr2_global_enabled(intel_dp)) {
924 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
925 return false;
926 }
927
928 /*
929 * DSC and PSR2 cannot be enabled simultaneously. If a requested
930 * resolution requires DSC to be enabled, priority is given to DSC
931 * over PSR2.
932 */
933 if (crtc_state->dsc.compression_enable) {
934 drm_dbg_kms(&dev_priv->drm,
935 "PSR2 cannot be enabled since DSC is enabled\n");
936 return false;
937 }
938
939 if (crtc_state->crc_enabled) {
940 drm_dbg_kms(&dev_priv->drm,
941 "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
942 return false;
943 }
944
945 if (DISPLAY_VER(dev_priv) >= 12) {
946 psr_max_h = 5120;
947 psr_max_v = 3200;
948 max_bpp = 30;
949 } else if (DISPLAY_VER(dev_priv) >= 10) {
950 psr_max_h = 4096;
951 psr_max_v = 2304;
952 max_bpp = 24;
953 } else if (DISPLAY_VER(dev_priv) == 9) {
954 psr_max_h = 3640;
955 psr_max_v = 2304;
956 max_bpp = 24;
957 }
958
959 if (crtc_state->pipe_bpp > max_bpp) {
960 drm_dbg_kms(&dev_priv->drm,
961 "PSR2 not enabled, pipe bpp %d > max supported %d\n",
962 crtc_state->pipe_bpp, max_bpp);
963 return false;
964 }
965
966 /* Wa_16011303918:adl-p */
967 if (crtc_state->vrr.enable &&
968 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
969 drm_dbg_kms(&dev_priv->drm,
970 "PSR2 not enabled, not compatible with HW stepping + VRR\n");
971 return false;
972 }
973
974 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
975 drm_dbg_kms(&dev_priv->drm,
976 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");
977 return false;
978 }
979
980 if (!_compute_psr2_wake_times(intel_dp, crtc_state)) {
981 drm_dbg_kms(&dev_priv->drm,
982 "PSR2 not enabled, Unable to use long enough wake times\n");
983 return false;
984 }
985
986 if (HAS_PSR2_SEL_FETCH(dev_priv)) {
987 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
988 !HAS_PSR_HW_TRACKING(dev_priv)) {
989 drm_dbg_kms(&dev_priv->drm,
990 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n");
991 return false;
992 }
993 }
994
995 /* Wa_2209313811 */
996 if (!crtc_state->enable_psr2_sel_fetch &&
997 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
998 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
999 goto unsupported;
1000 }
1001
1002 if (!psr2_granularity_check(intel_dp, crtc_state)) {
1003 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
1004 goto unsupported;
1005 }
1006
1007 if (!crtc_state->enable_psr2_sel_fetch &&
1008 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
1009 drm_dbg_kms(&dev_priv->drm,
1010 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
1011 crtc_hdisplay, crtc_vdisplay,
1012 psr_max_h, psr_max_v);
1013 goto unsupported;
1014 }
1015
1016 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
1017 return true;
1018
1019 unsupported:
1020 crtc_state->enable_psr2_sel_fetch = false;
1021 return false;
1022 }
1023
intel_psr_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)1024 void intel_psr_compute_config(struct intel_dp *intel_dp,
1025 struct intel_crtc_state *crtc_state)
1026 {
1027 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1028 const struct drm_display_mode *adjusted_mode =
1029 &crtc_state->hw.adjusted_mode;
1030 int psr_setup_time;
1031
1032 /*
1033 * Current PSR panels don't work reliably with VRR enabled
1034 * So if VRR is enabled, do not enable PSR.
1035 */
1036 if (crtc_state->vrr.enable)
1037 return;
1038
1039 if (!CAN_PSR(intel_dp))
1040 return;
1041
1042 if (!psr_global_enabled(intel_dp)) {
1043 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
1044 return;
1045 }
1046
1047 if (intel_dp->psr.sink_not_reliable) {
1048 drm_dbg_kms(&dev_priv->drm,
1049 "PSR sink implementation is not reliable\n");
1050 return;
1051 }
1052
1053 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1054 drm_dbg_kms(&dev_priv->drm,
1055 "PSR condition failed: Interlaced mode enabled\n");
1056 return;
1057 }
1058
1059 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
1060 if (psr_setup_time < 0) {
1061 drm_dbg_kms(&dev_priv->drm,
1062 "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
1063 intel_dp->psr_dpcd[1]);
1064 return;
1065 }
1066
1067 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
1068 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
1069 drm_dbg_kms(&dev_priv->drm,
1070 "PSR condition failed: PSR setup time (%d us) too long\n",
1071 psr_setup_time);
1072 return;
1073 }
1074
1075 crtc_state->has_psr = true;
1076 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
1077 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1078 }
1079
intel_psr_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1080 void intel_psr_get_config(struct intel_encoder *encoder,
1081 struct intel_crtc_state *pipe_config)
1082 {
1083 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1084 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1085 struct intel_dp *intel_dp;
1086 u32 val;
1087
1088 if (!dig_port)
1089 return;
1090
1091 intel_dp = &dig_port->dp;
1092 if (!CAN_PSR(intel_dp))
1093 return;
1094
1095 mutex_lock(&intel_dp->psr.lock);
1096 if (!intel_dp->psr.enabled)
1097 goto unlock;
1098
1099 /*
1100 * Not possible to read EDP_PSR/PSR2_CTL registers as it is
1101 * enabled/disabled because of frontbuffer tracking and others.
1102 */
1103 pipe_config->has_psr = true;
1104 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
1105 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1106
1107 if (!intel_dp->psr.psr2_enabled)
1108 goto unlock;
1109
1110 if (HAS_PSR2_SEL_FETCH(dev_priv)) {
1111 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
1112 if (val & PSR2_MAN_TRK_CTL_ENABLE)
1113 pipe_config->enable_psr2_sel_fetch = true;
1114 }
1115
1116 if (DISPLAY_VER(dev_priv) >= 12) {
1117 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
1118 val &= EXITLINE_MASK;
1119 pipe_config->dc3co_exitline = val;
1120 }
1121 unlock:
1122 mutex_unlock(&intel_dp->psr.lock);
1123 }
1124
intel_psr_activate(struct intel_dp * intel_dp)1125 static void intel_psr_activate(struct intel_dp *intel_dp)
1126 {
1127 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1128 enum transcoder transcoder = intel_dp->psr.transcoder;
1129
1130 if (transcoder_has_psr2(dev_priv, transcoder))
1131 drm_WARN_ON(&dev_priv->drm,
1132 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
1133
1134 drm_WARN_ON(&dev_priv->drm,
1135 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);
1136 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
1137 lockdep_assert_held(&intel_dp->psr.lock);
1138
1139 /* psr1 and psr2 are mutually exclusive.*/
1140 if (intel_dp->psr.psr2_enabled)
1141 hsw_activate_psr2(intel_dp);
1142 else
1143 hsw_activate_psr1(intel_dp);
1144
1145 intel_dp->psr.active = true;
1146 }
1147
intel_psr_enable_source(struct intel_dp * intel_dp)1148 static void intel_psr_enable_source(struct intel_dp *intel_dp)
1149 {
1150 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1151 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1152 u32 mask;
1153
1154 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
1155 * use hardcoded values PSR AUX transactions
1156 */
1157 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1158 hsw_psr_setup_aux(intel_dp);
1159
1160 if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {
1161 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
1162 u32 chicken = intel_de_read(dev_priv, reg);
1163
1164 chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
1165 PSR2_ADD_VERTICAL_LINE_COUNT;
1166 intel_de_write(dev_priv, reg, chicken);
1167 }
1168
1169 /*
1170 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
1171 * mask LPSP to avoid dependency on other drivers that might block
1172 * runtime_pm besides preventing other hw tracking issues now we
1173 * can rely on frontbuffer tracking.
1174 */
1175 mask = EDP_PSR_DEBUG_MASK_MEMUP |
1176 EDP_PSR_DEBUG_MASK_HPD |
1177 EDP_PSR_DEBUG_MASK_LPSP |
1178 EDP_PSR_DEBUG_MASK_MAX_SLEEP;
1179
1180 if (DISPLAY_VER(dev_priv) < 11)
1181 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
1182
1183 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
1184 mask);
1185
1186 psr_irq_control(intel_dp);
1187
1188 if (intel_dp->psr.dc3co_exitline) {
1189 u32 val;
1190
1191 /*
1192 * TODO: if future platforms supports DC3CO in more than one
1193 * transcoder, EXITLINE will need to be unset when disabling PSR
1194 */
1195 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
1196 val &= ~EXITLINE_MASK;
1197 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
1198 val |= EXITLINE_ENABLE;
1199 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
1200 }
1201
1202 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
1203 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
1204 intel_dp->psr.psr2_sel_fetch_enabled ?
1205 IGNORE_PSR2_HW_TRACKING : 0);
1206
1207 /* Wa_16011168373:adl-p */
1208 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
1209 intel_dp->psr.psr2_enabled)
1210 intel_de_rmw(dev_priv,
1211 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1212 TRANS_SET_CONTEXT_LATENCY_MASK,
1213 TRANS_SET_CONTEXT_LATENCY_VALUE(1));
1214 }
1215
psr_interrupt_error_check(struct intel_dp * intel_dp)1216 static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
1217 {
1218 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1219 u32 val;
1220
1221 /*
1222 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
1223 * will still keep the error set even after the reset done in the
1224 * irq_preinstall and irq_uninstall hooks.
1225 * And enabling in this situation cause the screen to freeze in the
1226 * first time that PSR HW tries to activate so lets keep PSR disabled
1227 * to avoid any rendering problems.
1228 */
1229 if (DISPLAY_VER(dev_priv) >= 12) {
1230 val = intel_de_read(dev_priv,
1231 TRANS_PSR_IIR(intel_dp->psr.transcoder));
1232 val &= EDP_PSR_ERROR(0);
1233 } else {
1234 val = intel_de_read(dev_priv, EDP_PSR_IIR);
1235 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
1236 }
1237 if (val) {
1238 intel_dp->psr.sink_not_reliable = true;
1239 drm_dbg_kms(&dev_priv->drm,
1240 "PSR interruption error set, not enabling PSR\n");
1241 return false;
1242 }
1243
1244 return true;
1245 }
1246
intel_psr_enable_locked(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1247 static void intel_psr_enable_locked(struct intel_dp *intel_dp,
1248 const struct intel_crtc_state *crtc_state,
1249 const struct drm_connector_state *conn_state)
1250 {
1251 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1252 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1253 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
1254 struct intel_encoder *encoder = &dig_port->base;
1255 u32 val;
1256
1257 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1258
1259 intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
1260 intel_dp->psr.busy_frontbuffer_bits = 0;
1261 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1262 intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1263 /* DC5/DC6 requires at least 6 idle frames */
1264 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
1265 intel_dp->psr.dc3co_exit_delay = val;
1266 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1267 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1268 intel_dp->psr.req_psr2_sdp_prior_scanline =
1269 crtc_state->req_psr2_sdp_prior_scanline;
1270
1271 if (!psr_interrupt_error_check(intel_dp))
1272 return;
1273
1274 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
1275 intel_dp->psr.psr2_enabled ? "2" : "1");
1276 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
1277 &intel_dp->psr.vsc);
1278 intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
1279 intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
1280 intel_psr_enable_sink(intel_dp);
1281 intel_psr_enable_source(intel_dp);
1282 intel_dp->psr.enabled = true;
1283 intel_dp->psr.paused = false;
1284
1285 intel_psr_activate(intel_dp);
1286 }
1287
1288 /**
1289 * intel_psr_enable - Enable PSR
1290 * @intel_dp: Intel DP
1291 * @crtc_state: new CRTC state
1292 * @conn_state: new CONNECTOR state
1293 *
1294 * This function can only be called after the pipe is fully trained and enabled.
1295 */
intel_psr_enable(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1296 void intel_psr_enable(struct intel_dp *intel_dp,
1297 const struct intel_crtc_state *crtc_state,
1298 const struct drm_connector_state *conn_state)
1299 {
1300 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1301
1302 if (!CAN_PSR(intel_dp))
1303 return;
1304
1305 if (!crtc_state->has_psr)
1306 return;
1307
1308 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
1309
1310 mutex_lock(&intel_dp->psr.lock);
1311 intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
1312 mutex_unlock(&intel_dp->psr.lock);
1313 }
1314
intel_psr_exit(struct intel_dp * intel_dp)1315 static void intel_psr_exit(struct intel_dp *intel_dp)
1316 {
1317 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1318 u32 val;
1319
1320 if (!intel_dp->psr.active) {
1321 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {
1322 val = intel_de_read(dev_priv,
1323 EDP_PSR2_CTL(intel_dp->psr.transcoder));
1324 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
1325 }
1326
1327 val = intel_de_read(dev_priv,
1328 EDP_PSR_CTL(intel_dp->psr.transcoder));
1329 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
1330
1331 return;
1332 }
1333
1334 if (intel_dp->psr.psr2_enabled) {
1335 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
1336 val = intel_de_read(dev_priv,
1337 EDP_PSR2_CTL(intel_dp->psr.transcoder));
1338 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
1339 val &= ~EDP_PSR2_ENABLE;
1340 intel_de_write(dev_priv,
1341 EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
1342 } else {
1343 val = intel_de_read(dev_priv,
1344 EDP_PSR_CTL(intel_dp->psr.transcoder));
1345 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
1346 val &= ~EDP_PSR_ENABLE;
1347 intel_de_write(dev_priv,
1348 EDP_PSR_CTL(intel_dp->psr.transcoder), val);
1349 }
1350 intel_dp->psr.active = false;
1351 }
1352
intel_psr_wait_exit_locked(struct intel_dp * intel_dp)1353 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
1354 {
1355 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1356 i915_reg_t psr_status;
1357 u32 psr_status_mask;
1358
1359 if (intel_dp->psr.psr2_enabled) {
1360 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1361 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
1362 } else {
1363 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1364 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
1365 }
1366
1367 /* Wait till PSR is idle */
1368 if (intel_de_wait_for_clear(dev_priv, psr_status,
1369 psr_status_mask, 2000))
1370 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
1371 }
1372
intel_psr_disable_locked(struct intel_dp * intel_dp)1373 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
1374 {
1375 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1376 enum phy phy = intel_port_to_phy(dev_priv,
1377 dp_to_dig_port(intel_dp)->base.port);
1378
1379 lockdep_assert_held(&intel_dp->psr.lock);
1380
1381 if (!intel_dp->psr.enabled)
1382 return;
1383
1384 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
1385 intel_dp->psr.psr2_enabled ? "2" : "1");
1386
1387 intel_psr_exit(intel_dp);
1388 intel_psr_wait_exit_locked(intel_dp);
1389
1390 /* Wa_1408330847 */
1391 if (intel_dp->psr.psr2_sel_fetch_enabled &&
1392 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1393 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1394 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
1395
1396 /* Wa_16011168373:adl-p */
1397 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
1398 intel_dp->psr.psr2_enabled)
1399 intel_de_rmw(dev_priv,
1400 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1401 TRANS_SET_CONTEXT_LATENCY_MASK, 0);
1402
1403 intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
1404
1405 /* Disable PSR on Sink */
1406 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
1407
1408 if (intel_dp->psr.psr2_enabled)
1409 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
1410
1411 intel_dp->psr.enabled = false;
1412 }
1413
1414 /**
1415 * intel_psr_disable - Disable PSR
1416 * @intel_dp: Intel DP
1417 * @old_crtc_state: old CRTC state
1418 *
1419 * This function needs to be called before disabling pipe.
1420 */
intel_psr_disable(struct intel_dp * intel_dp,const struct intel_crtc_state * old_crtc_state)1421 void intel_psr_disable(struct intel_dp *intel_dp,
1422 const struct intel_crtc_state *old_crtc_state)
1423 {
1424 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1425
1426 if (!old_crtc_state->has_psr)
1427 return;
1428
1429 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
1430 return;
1431
1432 mutex_lock(&intel_dp->psr.lock);
1433
1434 intel_psr_disable_locked(intel_dp);
1435
1436 mutex_unlock(&intel_dp->psr.lock);
1437 cancel_work_sync(&intel_dp->psr.work);
1438 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
1439 }
1440
1441 /**
1442 * intel_psr_pause - Pause PSR
1443 * @intel_dp: Intel DP
1444 *
1445 * This function need to be called after enabling psr.
1446 */
intel_psr_pause(struct intel_dp * intel_dp)1447 void intel_psr_pause(struct intel_dp *intel_dp)
1448 {
1449 struct intel_psr *psr = &intel_dp->psr;
1450
1451 if (!CAN_PSR(intel_dp))
1452 return;
1453
1454 mutex_lock(&psr->lock);
1455
1456 if (!psr->enabled) {
1457 mutex_unlock(&psr->lock);
1458 return;
1459 }
1460
1461 intel_psr_exit(intel_dp);
1462 intel_psr_wait_exit_locked(intel_dp);
1463 psr->paused = true;
1464
1465 mutex_unlock(&psr->lock);
1466
1467 cancel_work_sync(&psr->work);
1468 cancel_delayed_work_sync(&psr->dc3co_work);
1469 }
1470
1471 /**
1472 * intel_psr_resume - Resume PSR
1473 * @intel_dp: Intel DP
1474 *
1475 * This function need to be called after pausing psr.
1476 */
intel_psr_resume(struct intel_dp * intel_dp)1477 void intel_psr_resume(struct intel_dp *intel_dp)
1478 {
1479 struct intel_psr *psr = &intel_dp->psr;
1480
1481 if (!CAN_PSR(intel_dp))
1482 return;
1483
1484 mutex_lock(&psr->lock);
1485
1486 if (!psr->paused)
1487 goto unlock;
1488
1489 psr->paused = false;
1490 intel_psr_activate(intel_dp);
1491
1492 unlock:
1493 mutex_unlock(&psr->lock);
1494 }
1495
psr_force_hw_tracking_exit(struct intel_dp * intel_dp)1496 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
1497 {
1498 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1499
1500 if (DISPLAY_VER(dev_priv) >= 9)
1501 /*
1502 * Display WA #0884: skl+
1503 * This documented WA for bxt can be safely applied
1504 * broadly so we can force HW tracking to exit PSR
1505 * instead of disabling and re-enabling.
1506 * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1507 * but it makes more sense write to the current active
1508 * pipe.
1509 */
1510 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
1511 else
1512 /*
1513 * A write to CURSURFLIVE do not cause HW tracking to exit PSR
1514 * on older gens so doing the manual exit instead.
1515 */
1516 intel_psr_exit(intel_dp);
1517 }
1518
intel_psr2_program_plane_sel_fetch(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,int color_plane)1519 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
1520 const struct intel_crtc_state *crtc_state,
1521 const struct intel_plane_state *plane_state,
1522 int color_plane)
1523 {
1524 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1525 enum pipe pipe = plane->pipe;
1526 const struct drm_rect *clip;
1527 u32 val, offset;
1528 int ret, x, y;
1529
1530 if (!crtc_state->enable_psr2_sel_fetch)
1531 return;
1532
1533 val = plane_state ? plane_state->ctl : 0;
1534 val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
1535 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
1536 if (!val || plane->id == PLANE_CURSOR)
1537 return;
1538
1539 clip = &plane_state->psr2_sel_fetch_area;
1540
1541 val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
1542 val |= plane_state->uapi.dst.x1;
1543 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1544
1545 /* TODO: consider auxiliary surfaces */
1546 x = plane_state->uapi.src.x1 >> 16;
1547 y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
1548 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
1549 if (ret)
1550 drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n",
1551 ret);
1552 val = y << 16 | x;
1553 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1554 val);
1555
1556 /* Sizes are 0 based */
1557 val = (drm_rect_height(clip) - 1) << 16;
1558 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1559 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1560 }
1561
intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state * crtc_state)1562 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1563 {
1564 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1565
1566 if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
1567 !crtc_state->enable_psr2_sel_fetch)
1568 return;
1569
1570 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
1571 crtc_state->psr2_man_track_ctl);
1572 }
1573
psr2_man_trk_ctl_calc(struct intel_crtc_state * crtc_state,struct drm_rect * clip,bool full_update)1574 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
1575 struct drm_rect *clip, bool full_update)
1576 {
1577 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1578 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1579 u32 val = PSR2_MAN_TRK_CTL_ENABLE;
1580
1581 if (full_update) {
1582 if (IS_ALDERLAKE_P(dev_priv))
1583 val |= ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1584 else
1585 val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1586
1587 goto exit;
1588 }
1589
1590 if (clip->y1 == -1)
1591 goto exit;
1592
1593 if (IS_ALDERLAKE_P(dev_priv)) {
1594 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
1595 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
1596 } else {
1597 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
1598
1599 val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
1600 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
1601 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
1602 }
1603 exit:
1604 crtc_state->psr2_man_track_ctl = val;
1605 }
1606
clip_area_update(struct drm_rect * overlap_damage_area,struct drm_rect * damage_area)1607 static void clip_area_update(struct drm_rect *overlap_damage_area,
1608 struct drm_rect *damage_area)
1609 {
1610 if (overlap_damage_area->y1 == -1) {
1611 overlap_damage_area->y1 = damage_area->y1;
1612 overlap_damage_area->y2 = damage_area->y2;
1613 return;
1614 }
1615
1616 if (damage_area->y1 < overlap_damage_area->y1)
1617 overlap_damage_area->y1 = damage_area->y1;
1618
1619 if (damage_area->y2 > overlap_damage_area->y2)
1620 overlap_damage_area->y2 = damage_area->y2;
1621 }
1622
intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state * crtc_state,struct drm_rect * pipe_clip)1623 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
1624 struct drm_rect *pipe_clip)
1625 {
1626 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1627 const u16 y_alignment = crtc_state->su_y_granularity;
1628
1629 pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
1630 if (pipe_clip->y2 % y_alignment)
1631 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
1632
1633 if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
1634 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
1635 }
1636
1637 /*
1638 * FIXME: Not sure why but when moving the cursor fast it causes some artifacts
1639 * of the cursor to be left in the cursor path, adding some pixels above the
1640 * cursor to the damaged area fixes the issue.
1641 */
cursor_area_workaround(const struct intel_plane_state * new_plane_state,struct drm_rect * damaged_area,struct drm_rect * pipe_clip)1642 static void cursor_area_workaround(const struct intel_plane_state *new_plane_state,
1643 struct drm_rect *damaged_area,
1644 struct drm_rect *pipe_clip)
1645 {
1646 const struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
1647 int height;
1648
1649 if (plane->id != PLANE_CURSOR)
1650 return;
1651
1652 height = drm_rect_height(&new_plane_state->uapi.dst) / 2;
1653 damaged_area->y1 -= height;
1654 damaged_area->y1 = max(damaged_area->y1, 0);
1655
1656 clip_area_update(pipe_clip, damaged_area);
1657 }
1658
1659 /*
1660 * TODO: Not clear how to handle planes with negative position,
1661 * also planes are not updated if they have a negative X
1662 * position so for now doing a full update in this cases
1663 *
1664 * Plane scaling and rotation is not supported by selective fetch and both
1665 * properties can change without a modeset, so need to be check at every
1666 * atomic commit.
1667 */
psr2_sel_fetch_plane_state_supported(const struct intel_plane_state * plane_state)1668 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
1669 {
1670 if (plane_state->uapi.dst.y1 < 0 ||
1671 plane_state->uapi.dst.x1 < 0 ||
1672 plane_state->scaler_id >= 0 ||
1673 plane_state->uapi.rotation != DRM_MODE_ROTATE_0)
1674 return false;
1675
1676 return true;
1677 }
1678
1679 /*
1680 * Check for pipe properties that is not supported by selective fetch.
1681 *
1682 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed
1683 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch
1684 * enabled and going to the full update path.
1685 */
psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state * crtc_state)1686 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
1687 {
1688 if (crtc_state->scaler_state.scaler_id >= 0)
1689 return false;
1690
1691 return true;
1692 }
1693
intel_psr2_sel_fetch_update(struct intel_atomic_state * state,struct intel_crtc * crtc)1694 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
1695 struct intel_crtc *crtc)
1696 {
1697 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1698 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 };
1699 struct intel_plane_state *new_plane_state, *old_plane_state;
1700 struct intel_plane *plane;
1701 bool full_update = false;
1702 int i, ret;
1703
1704 if (!crtc_state->enable_psr2_sel_fetch)
1705 return 0;
1706
1707 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
1708 full_update = true;
1709 goto skip_sel_fetch_set_loop;
1710 }
1711
1712 /*
1713 * Calculate minimal selective fetch area of each plane and calculate
1714 * the pipe damaged area.
1715 * In the next loop the plane selective fetch area will actually be set
1716 * using whole pipe damaged area.
1717 */
1718 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1719 new_plane_state, i) {
1720 struct drm_rect src, damaged_area = { .y1 = -1 };
1721 struct drm_atomic_helper_damage_iter iter;
1722 struct drm_rect clip;
1723
1724 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
1725 continue;
1726
1727 if (!new_plane_state->uapi.visible &&
1728 !old_plane_state->uapi.visible)
1729 continue;
1730
1731 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
1732 full_update = true;
1733 break;
1734 }
1735
1736 /*
1737 * If visibility or plane moved, mark the whole plane area as
1738 * damaged as it needs to be complete redraw in the new and old
1739 * position.
1740 */
1741 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible ||
1742 !drm_rect_equals(&new_plane_state->uapi.dst,
1743 &old_plane_state->uapi.dst)) {
1744 if (old_plane_state->uapi.visible) {
1745 damaged_area.y1 = old_plane_state->uapi.dst.y1;
1746 damaged_area.y2 = old_plane_state->uapi.dst.y2;
1747 clip_area_update(&pipe_clip, &damaged_area);
1748 }
1749
1750 if (new_plane_state->uapi.visible) {
1751 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1752 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1753 clip_area_update(&pipe_clip, &damaged_area);
1754 }
1755
1756 cursor_area_workaround(new_plane_state, &damaged_area,
1757 &pipe_clip);
1758 continue;
1759 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
1760 /* If alpha changed mark the whole plane area as damaged */
1761 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1762 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1763 clip_area_update(&pipe_clip, &damaged_area);
1764 continue;
1765 }
1766
1767 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
1768
1769 drm_atomic_helper_damage_iter_init(&iter,
1770 &old_plane_state->uapi,
1771 &new_plane_state->uapi);
1772 drm_atomic_for_each_plane_damage(&iter, &clip) {
1773 if (drm_rect_intersect(&clip, &src))
1774 clip_area_update(&damaged_area, &clip);
1775 }
1776
1777 if (damaged_area.y1 == -1)
1778 continue;
1779
1780 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
1781 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
1782 clip_area_update(&pipe_clip, &damaged_area);
1783 }
1784
1785 if (full_update)
1786 goto skip_sel_fetch_set_loop;
1787
1788 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
1789 if (ret)
1790 return ret;
1791
1792 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
1793
1794 /*
1795 * Now that we have the pipe damaged area check if it intersect with
1796 * every plane, if it does set the plane selective fetch area.
1797 */
1798 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1799 new_plane_state, i) {
1800 struct drm_rect *sel_fetch_area, inter;
1801
1802 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc ||
1803 !new_plane_state->uapi.visible)
1804 continue;
1805
1806 inter = pipe_clip;
1807 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
1808 continue;
1809
1810 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
1811 full_update = true;
1812 break;
1813 }
1814
1815 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
1816 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
1817 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
1818 crtc_state->update_planes |= BIT(plane->id);
1819 }
1820
1821 skip_sel_fetch_set_loop:
1822 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
1823 return 0;
1824 }
1825
1826 /**
1827 * intel_psr_update - Update PSR state
1828 * @intel_dp: Intel DP
1829 * @crtc_state: new CRTC state
1830 * @conn_state: new CONNECTOR state
1831 *
1832 * This functions will update PSR states, disabling, enabling or switching PSR
1833 * version when executing fastsets. For full modeset, intel_psr_disable() and
1834 * intel_psr_enable() should be called instead.
1835 */
intel_psr_update(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1836 void intel_psr_update(struct intel_dp *intel_dp,
1837 const struct intel_crtc_state *crtc_state,
1838 const struct drm_connector_state *conn_state)
1839 {
1840 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1841 struct intel_psr *psr = &intel_dp->psr;
1842 bool enable, psr2_enable;
1843
1844 if (!CAN_PSR(intel_dp))
1845 return;
1846
1847 mutex_lock(&intel_dp->psr.lock);
1848
1849 enable = crtc_state->has_psr;
1850 psr2_enable = crtc_state->has_psr2;
1851
1852 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled &&
1853 crtc_state->enable_psr2_sel_fetch == psr->psr2_sel_fetch_enabled) {
1854 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
1855 if (crtc_state->crc_enabled && psr->enabled)
1856 psr_force_hw_tracking_exit(intel_dp);
1857 else if (DISPLAY_VER(dev_priv) < 9 && psr->enabled) {
1858 /*
1859 * Activate PSR again after a force exit when enabling
1860 * CRC in older gens
1861 */
1862 if (!intel_dp->psr.active &&
1863 !intel_dp->psr.busy_frontbuffer_bits)
1864 schedule_work(&intel_dp->psr.work);
1865 }
1866
1867 goto unlock;
1868 }
1869
1870 if (psr->enabled)
1871 intel_psr_disable_locked(intel_dp);
1872
1873 if (enable)
1874 intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
1875
1876 unlock:
1877 mutex_unlock(&intel_dp->psr.lock);
1878 }
1879
1880 /**
1881 * psr_wait_for_idle - wait for PSR1 to idle
1882 * @intel_dp: Intel DP
1883 * @out_value: PSR status in case of failure
1884 *
1885 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
1886 *
1887 */
psr_wait_for_idle(struct intel_dp * intel_dp,u32 * out_value)1888 static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
1889 {
1890 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1891
1892 /*
1893 * From bspec: Panel Self Refresh (BDW+)
1894 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
1895 * exit training time + 1.5 ms of aux channel handshake. 50 ms is
1896 * defensive enough to cover everything.
1897 */
1898 return __intel_wait_for_register(&dev_priv->uncore,
1899 EDP_PSR_STATUS(intel_dp->psr.transcoder),
1900 EDP_PSR_STATUS_STATE_MASK,
1901 EDP_PSR_STATUS_STATE_IDLE, 2, 50,
1902 out_value);
1903 }
1904
1905 /**
1906 * intel_psr_wait_for_idle - wait for PSR1 to idle
1907 * @new_crtc_state: new CRTC state
1908 *
1909 * This function is expected to be called from pipe_update_start() where it is
1910 * not expected to race with PSR enable or disable.
1911 */
intel_psr_wait_for_idle(const struct intel_crtc_state * new_crtc_state)1912 void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
1913 {
1914 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
1915 struct intel_encoder *encoder;
1916
1917 if (!new_crtc_state->has_psr)
1918 return;
1919
1920 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
1921 new_crtc_state->uapi.encoder_mask) {
1922 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1923 u32 psr_status;
1924
1925 mutex_lock(&intel_dp->psr.lock);
1926 if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) {
1927 mutex_unlock(&intel_dp->psr.lock);
1928 continue;
1929 }
1930
1931 /* when the PSR1 is enabled */
1932 if (psr_wait_for_idle(intel_dp, &psr_status))
1933 drm_err(&dev_priv->drm,
1934 "PSR idle timed out 0x%x, atomic update may fail\n",
1935 psr_status);
1936 mutex_unlock(&intel_dp->psr.lock);
1937 }
1938 }
1939
__psr_wait_for_idle_locked(struct intel_dp * intel_dp)1940 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
1941 {
1942 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1943 i915_reg_t reg;
1944 u32 mask;
1945 int err;
1946
1947 if (!intel_dp->psr.enabled)
1948 return false;
1949
1950 if (intel_dp->psr.psr2_enabled) {
1951 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1952 mask = EDP_PSR2_STATUS_STATE_MASK;
1953 } else {
1954 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1955 mask = EDP_PSR_STATUS_STATE_MASK;
1956 }
1957
1958 mutex_unlock(&intel_dp->psr.lock);
1959
1960 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
1961 if (err)
1962 drm_err(&dev_priv->drm,
1963 "Timed out waiting for PSR Idle for re-enable\n");
1964
1965 /* After the unlocked wait, verify that PSR is still wanted! */
1966 mutex_lock(&intel_dp->psr.lock);
1967 return err == 0 && intel_dp->psr.enabled;
1968 }
1969
intel_psr_fastset_force(struct drm_i915_private * dev_priv)1970 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
1971 {
1972 struct drm_connector_list_iter conn_iter;
1973 struct drm_device *dev = &dev_priv->drm;
1974 struct drm_modeset_acquire_ctx ctx;
1975 struct drm_atomic_state *state;
1976 struct drm_connector *conn;
1977 int err = 0;
1978
1979 state = drm_atomic_state_alloc(dev);
1980 if (!state)
1981 return -ENOMEM;
1982
1983 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1984 state->acquire_ctx = &ctx;
1985
1986 retry:
1987
1988 drm_connector_list_iter_begin(dev, &conn_iter);
1989 drm_for_each_connector_iter(conn, &conn_iter) {
1990 struct drm_connector_state *conn_state;
1991 struct drm_crtc_state *crtc_state;
1992
1993 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
1994 continue;
1995
1996 conn_state = drm_atomic_get_connector_state(state, conn);
1997 if (IS_ERR(conn_state)) {
1998 err = PTR_ERR(conn_state);
1999 break;
2000 }
2001
2002 if (!conn_state->crtc)
2003 continue;
2004
2005 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
2006 if (IS_ERR(crtc_state)) {
2007 err = PTR_ERR(crtc_state);
2008 break;
2009 }
2010
2011 /* Mark mode as changed to trigger a pipe->update() */
2012 crtc_state->mode_changed = true;
2013 }
2014 drm_connector_list_iter_end(&conn_iter);
2015
2016 if (err == 0)
2017 err = drm_atomic_commit(state);
2018
2019 if (err == -EDEADLK) {
2020 drm_atomic_state_clear(state);
2021 err = drm_modeset_backoff(&ctx);
2022 if (!err)
2023 goto retry;
2024 }
2025
2026 drm_modeset_drop_locks(&ctx);
2027 drm_modeset_acquire_fini(&ctx);
2028 drm_atomic_state_put(state);
2029
2030 return err;
2031 }
2032
intel_psr_debug_set(struct intel_dp * intel_dp,u64 val)2033 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
2034 {
2035 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2036 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
2037 u32 old_mode;
2038 int ret;
2039
2040 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
2041 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
2042 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
2043 return -EINVAL;
2044 }
2045
2046 ret = mutex_lock_interruptible(&intel_dp->psr.lock);
2047 if (ret)
2048 return ret;
2049
2050 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
2051 intel_dp->psr.debug = val;
2052
2053 /*
2054 * Do it right away if it's already enabled, otherwise it will be done
2055 * when enabling the source.
2056 */
2057 if (intel_dp->psr.enabled)
2058 psr_irq_control(intel_dp);
2059
2060 mutex_unlock(&intel_dp->psr.lock);
2061
2062 if (old_mode != mode)
2063 ret = intel_psr_fastset_force(dev_priv);
2064
2065 return ret;
2066 }
2067
intel_psr_handle_irq(struct intel_dp * intel_dp)2068 static void intel_psr_handle_irq(struct intel_dp *intel_dp)
2069 {
2070 struct intel_psr *psr = &intel_dp->psr;
2071
2072 intel_psr_disable_locked(intel_dp);
2073 psr->sink_not_reliable = true;
2074 /* let's make sure that sink is awaken */
2075 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
2076 }
2077
intel_psr_work(struct work_struct * work)2078 static void intel_psr_work(struct work_struct *work)
2079 {
2080 struct intel_dp *intel_dp =
2081 container_of(work, typeof(*intel_dp), psr.work);
2082
2083 mutex_lock(&intel_dp->psr.lock);
2084
2085 if (!intel_dp->psr.enabled)
2086 goto unlock;
2087
2088 if (READ_ONCE(intel_dp->psr.irq_aux_error))
2089 intel_psr_handle_irq(intel_dp);
2090
2091 /*
2092 * We have to make sure PSR is ready for re-enable
2093 * otherwise it keeps disabled until next full enable/disable cycle.
2094 * PSR might take some time to get fully disabled
2095 * and be ready for re-enable.
2096 */
2097 if (!__psr_wait_for_idle_locked(intel_dp))
2098 goto unlock;
2099
2100 /*
2101 * The delayed work can race with an invalidate hence we need to
2102 * recheck. Since psr_flush first clears this and then reschedules we
2103 * won't ever miss a flush when bailing out here.
2104 */
2105 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
2106 goto unlock;
2107
2108 intel_psr_activate(intel_dp);
2109 unlock:
2110 mutex_unlock(&intel_dp->psr.lock);
2111 }
2112
2113 /**
2114 * intel_psr_invalidate - Invalidate PSR
2115 * @dev_priv: i915 device
2116 * @frontbuffer_bits: frontbuffer plane tracking bits
2117 * @origin: which operation caused the invalidate
2118 *
2119 * Since the hardware frontbuffer tracking has gaps we need to integrate
2120 * with the software frontbuffer tracking. This function gets called every
2121 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
2122 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
2123 *
2124 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
2125 */
intel_psr_invalidate(struct drm_i915_private * dev_priv,unsigned frontbuffer_bits,enum fb_op_origin origin)2126 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2127 unsigned frontbuffer_bits, enum fb_op_origin origin)
2128 {
2129 struct intel_encoder *encoder;
2130
2131 if (origin == ORIGIN_FLIP)
2132 return;
2133
2134 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2135 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2136 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2137
2138 mutex_lock(&intel_dp->psr.lock);
2139 if (!intel_dp->psr.enabled) {
2140 mutex_unlock(&intel_dp->psr.lock);
2141 continue;
2142 }
2143
2144 pipe_frontbuffer_bits &=
2145 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2146 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
2147
2148 if (pipe_frontbuffer_bits)
2149 intel_psr_exit(intel_dp);
2150
2151 mutex_unlock(&intel_dp->psr.lock);
2152 }
2153 }
2154 /*
2155 * When we will be completely rely on PSR2 S/W tracking in future,
2156 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
2157 * event also therefore tgl_dc3co_flush() require to be changed
2158 * accordingly in future.
2159 */
2160 static void
tgl_dc3co_flush(struct intel_dp * intel_dp,unsigned int frontbuffer_bits,enum fb_op_origin origin)2161 tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
2162 enum fb_op_origin origin)
2163 {
2164 mutex_lock(&intel_dp->psr.lock);
2165
2166 if (!intel_dp->psr.dc3co_exitline)
2167 goto unlock;
2168
2169 if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
2170 goto unlock;
2171
2172 /*
2173 * At every frontbuffer flush flip event modified delay of delayed work,
2174 * when delayed work schedules that means display has been idle.
2175 */
2176 if (!(frontbuffer_bits &
2177 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
2178 goto unlock;
2179
2180 tgl_psr2_enable_dc3co(intel_dp);
2181 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
2182 intel_dp->psr.dc3co_exit_delay);
2183
2184 unlock:
2185 mutex_unlock(&intel_dp->psr.lock);
2186 }
2187
2188 /**
2189 * intel_psr_flush - Flush PSR
2190 * @dev_priv: i915 device
2191 * @frontbuffer_bits: frontbuffer plane tracking bits
2192 * @origin: which operation caused the flush
2193 *
2194 * Since the hardware frontbuffer tracking has gaps we need to integrate
2195 * with the software frontbuffer tracking. This function gets called every
2196 * time frontbuffer rendering has completed and flushed out to memory. PSR
2197 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
2198 *
2199 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
2200 */
intel_psr_flush(struct drm_i915_private * dev_priv,unsigned frontbuffer_bits,enum fb_op_origin origin)2201 void intel_psr_flush(struct drm_i915_private *dev_priv,
2202 unsigned frontbuffer_bits, enum fb_op_origin origin)
2203 {
2204 struct intel_encoder *encoder;
2205
2206 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2207 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2208 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2209
2210 if (origin == ORIGIN_FLIP) {
2211 tgl_dc3co_flush(intel_dp, frontbuffer_bits, origin);
2212 continue;
2213 }
2214
2215 mutex_lock(&intel_dp->psr.lock);
2216 if (!intel_dp->psr.enabled) {
2217 mutex_unlock(&intel_dp->psr.lock);
2218 continue;
2219 }
2220
2221 pipe_frontbuffer_bits &=
2222 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2223 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
2224
2225 /*
2226 * If the PSR is paused by an explicit intel_psr_paused() call,
2227 * we have to ensure that the PSR is not activated until
2228 * intel_psr_resume() is called.
2229 */
2230 if (intel_dp->psr.paused) {
2231 mutex_unlock(&intel_dp->psr.lock);
2232 continue;
2233 }
2234
2235 /* By definition flush = invalidate + flush */
2236 if (pipe_frontbuffer_bits)
2237 psr_force_hw_tracking_exit(intel_dp);
2238
2239 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
2240 schedule_work(&intel_dp->psr.work);
2241 mutex_unlock(&intel_dp->psr.lock);
2242 }
2243 }
2244
2245 /**
2246 * intel_psr_init - Init basic PSR work and mutex.
2247 * @intel_dp: Intel DP
2248 *
2249 * This function is called after the initializing connector.
2250 * (the initializing of connector treats the handling of connector capabilities)
2251 * And it initializes basic PSR stuff for each DP Encoder.
2252 */
intel_psr_init(struct intel_dp * intel_dp)2253 void intel_psr_init(struct intel_dp *intel_dp)
2254 {
2255 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2256 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2257
2258 if (!HAS_PSR(dev_priv))
2259 return;
2260
2261 /*
2262 * HSW spec explicitly says PSR is tied to port A.
2263 * BDW+ platforms have a instance of PSR registers per transcoder but
2264 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder
2265 * than eDP one.
2266 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11.
2267 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11.
2268 * But GEN12 supports a instance of PSR registers per transcoder.
2269 */
2270 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {
2271 drm_dbg_kms(&dev_priv->drm,
2272 "PSR condition failed: Port not supported\n");
2273 return;
2274 }
2275
2276 intel_dp->psr.source_support = true;
2277
2278 if (IS_HASWELL(dev_priv))
2279 /*
2280 * HSW don't have PSR registers on the same space as transcoder
2281 * so set this to a value that when subtract to the register
2282 * in transcoder space results in the right offset for HSW
2283 */
2284 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
2285
2286 if (dev_priv->params.enable_psr == -1)
2287 if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
2288 dev_priv->params.enable_psr = 0;
2289
2290 /* Set link_standby x link_off defaults */
2291 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2292 /* HSW and BDW require workarounds that we don't implement. */
2293 intel_dp->psr.link_standby = false;
2294 else if (DISPLAY_VER(dev_priv) < 12)
2295 /* For new platforms up to TGL let's respect VBT back again */
2296 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
2297
2298 INIT_WORK(&intel_dp->psr.work, intel_psr_work);
2299 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
2300 mutex_init(&intel_dp->psr.lock);
2301 }
2302
psr_get_status_and_error_status(struct intel_dp * intel_dp,u8 * status,u8 * error_status)2303 static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
2304 u8 *status, u8 *error_status)
2305 {
2306 struct drm_dp_aux *aux = &intel_dp->aux;
2307 int ret;
2308
2309 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
2310 if (ret != 1)
2311 return ret;
2312
2313 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
2314 if (ret != 1)
2315 return ret;
2316
2317 *status = *status & DP_PSR_SINK_STATE_MASK;
2318
2319 return 0;
2320 }
2321
psr_alpm_check(struct intel_dp * intel_dp)2322 static void psr_alpm_check(struct intel_dp *intel_dp)
2323 {
2324 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2325 struct drm_dp_aux *aux = &intel_dp->aux;
2326 struct intel_psr *psr = &intel_dp->psr;
2327 u8 val;
2328 int r;
2329
2330 if (!psr->psr2_enabled)
2331 return;
2332
2333 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
2334 if (r != 1) {
2335 drm_err(&dev_priv->drm, "Error reading ALPM status\n");
2336 return;
2337 }
2338
2339 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
2340 intel_psr_disable_locked(intel_dp);
2341 psr->sink_not_reliable = true;
2342 drm_dbg_kms(&dev_priv->drm,
2343 "ALPM lock timeout error, disabling PSR\n");
2344
2345 /* Clearing error */
2346 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
2347 }
2348 }
2349
psr_capability_changed_check(struct intel_dp * intel_dp)2350 static void psr_capability_changed_check(struct intel_dp *intel_dp)
2351 {
2352 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2353 struct intel_psr *psr = &intel_dp->psr;
2354 u8 val;
2355 int r;
2356
2357 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
2358 if (r != 1) {
2359 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
2360 return;
2361 }
2362
2363 if (val & DP_PSR_CAPS_CHANGE) {
2364 intel_psr_disable_locked(intel_dp);
2365 psr->sink_not_reliable = true;
2366 drm_dbg_kms(&dev_priv->drm,
2367 "Sink PSR capability changed, disabling PSR\n");
2368
2369 /* Clearing it */
2370 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
2371 }
2372 }
2373
intel_psr_short_pulse(struct intel_dp * intel_dp)2374 void intel_psr_short_pulse(struct intel_dp *intel_dp)
2375 {
2376 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2377 struct intel_psr *psr = &intel_dp->psr;
2378 u8 status, error_status;
2379 const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
2380 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
2381 DP_PSR_LINK_CRC_ERROR;
2382
2383 if (!CAN_PSR(intel_dp))
2384 return;
2385
2386 mutex_lock(&psr->lock);
2387
2388 if (!psr->enabled)
2389 goto exit;
2390
2391 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
2392 drm_err(&dev_priv->drm,
2393 "Error reading PSR status or error status\n");
2394 goto exit;
2395 }
2396
2397 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
2398 intel_psr_disable_locked(intel_dp);
2399 psr->sink_not_reliable = true;
2400 }
2401
2402 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
2403 drm_dbg_kms(&dev_priv->drm,
2404 "PSR sink internal error, disabling PSR\n");
2405 if (error_status & DP_PSR_RFB_STORAGE_ERROR)
2406 drm_dbg_kms(&dev_priv->drm,
2407 "PSR RFB storage error, disabling PSR\n");
2408 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
2409 drm_dbg_kms(&dev_priv->drm,
2410 "PSR VSC SDP uncorrectable error, disabling PSR\n");
2411 if (error_status & DP_PSR_LINK_CRC_ERROR)
2412 drm_dbg_kms(&dev_priv->drm,
2413 "PSR Link CRC error, disabling PSR\n");
2414
2415 if (error_status & ~errors)
2416 drm_err(&dev_priv->drm,
2417 "PSR_ERROR_STATUS unhandled errors %x\n",
2418 error_status & ~errors);
2419 /* clear status register */
2420 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
2421
2422 psr_alpm_check(intel_dp);
2423 psr_capability_changed_check(intel_dp);
2424
2425 exit:
2426 mutex_unlock(&psr->lock);
2427 }
2428
intel_psr_enabled(struct intel_dp * intel_dp)2429 bool intel_psr_enabled(struct intel_dp *intel_dp)
2430 {
2431 bool ret;
2432
2433 if (!CAN_PSR(intel_dp))
2434 return false;
2435
2436 mutex_lock(&intel_dp->psr.lock);
2437 ret = intel_dp->psr.enabled;
2438 mutex_unlock(&intel_dp->psr.lock);
2439
2440 return ret;
2441 }
2442