145 read_clk(struct gk104_clk *clk, int idx)  in read_clk()  argument
148 	u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));  in read_clk()
151 	if (idx < 7) {  in read_clk()
153 		if (ssel & (1 << idx)) {  in read_clk()
154 			sclk = read_pll(clk, 0x137000 + (idx * 0x20));  in read_clk()
157 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);  in read_clk()
161 		u32 ssrc = nvkm_rd32(device, 0x137160 + (idx * 0x04));  in read_clk()
163 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);  in read_clk()
172 			sclk = read_div(clk, idx, 0x137160, 0x1371d0);  in read_clk()
223 calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)  in calc_div()  argument
234 calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)  in calc_src()  argument
256 	sclk = read_vco(clk, 0x137160 + (idx * 4));  in calc_src()
257 	if (idx < 7)  in calc_src()
258 		sclk = calc_div(clk, idx, sclk, freq, ddiv);  in calc_src()
263 calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef)  in calc_pll()  argument
270 	ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);  in calc_pll()
274 	limits.refclk = read_div(clk, idx, 0x137120, 0x137140);  in calc_pll()
288 	 struct nvkm_cstate *cstate, int idx, int dom)  in calc_clk()  argument
290 	struct gk104_clk_info *info = &clk->eng[idx];  in calc_clk()
300 	clk0 = calc_src(clk, idx, freq, &src0, &div0);  in calc_clk()
301 	clk0 = calc_div(clk, idx, clk0, freq, &div1D);  in calc_clk()
304 	if (clk0 != freq && (0x0000ff87 & (1 << idx))) {  in calc_clk()
305 		if (idx <= 7)  in calc_clk()
306 			clk1 = calc_pll(clk, idx, freq, &info->coef);  in calc_clk()
309 		clk1 = calc_div(clk, idx, clk1, freq, &div1P);  in calc_clk()
330 		info->ssel = (1 << idx);  in calc_clk()
357 gk104_clk_prog_0(struct gk104_clk *clk, int idx)  in gk104_clk_prog_0()  argument
359 	struct gk104_clk_info *info = &clk->eng[idx];  in gk104_clk_prog_0()
362 		nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv);  in gk104_clk_prog_0()
363 		nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);  in gk104_clk_prog_0()
368 gk104_clk_prog_1_0(struct gk104_clk *clk, int idx)  in gk104_clk_prog_1_0()  argument
371 	nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);  in gk104_clk_prog_1_0()
373 		if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))  in gk104_clk_prog_1_0()
379 gk104_clk_prog_1_1(struct gk104_clk *clk, int idx)  in gk104_clk_prog_1_1()  argument
382 	nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000);  in gk104_clk_prog_1_1()
386 gk104_clk_prog_2(struct gk104_clk *clk, int idx)  in gk104_clk_prog_2()  argument
388 	struct gk104_clk_info *info = &clk->eng[idx];  in gk104_clk_prog_2()
390 	const u32 addr = 0x137000 + (idx * 0x20);  in gk104_clk_prog_2()
411 gk104_clk_prog_3(struct gk104_clk *clk, int idx)  in gk104_clk_prog_3()  argument
413 	struct gk104_clk_info *info = &clk->eng[idx];  in gk104_clk_prog_3()
416 		nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv);  in gk104_clk_prog_3()
418 		nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv);  in gk104_clk_prog_3()
422 gk104_clk_prog_4_0(struct gk104_clk *clk, int idx)  in gk104_clk_prog_4_0()  argument
424 	struct gk104_clk_info *info = &clk->eng[idx];  in gk104_clk_prog_4_0()
427 		nvkm_mask(device, 0x137100, (1 << idx), info->ssel);  in gk104_clk_prog_4_0()
429 			u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);  in gk104_clk_prog_4_0()
437 gk104_clk_prog_4_1(struct gk104_clk *clk, int idx)  in gk104_clk_prog_4_1()  argument
439 	struct gk104_clk_info *info = &clk->eng[idx];  in gk104_clk_prog_4_1()
442 		nvkm_mask(device, 0x137160 + (idx * 0x04), 0x40000000, 0x40000000);  in gk104_clk_prog_4_1()
443 		nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000100);  in gk104_clk_prog_4_1()