2987 	ha->pci_attr = rd_reg_dword(&reg->ctrl_status);  in qla24xx_pci_config()
3290 		if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)  in qla24xx_reset_risc()
3296 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))  in qla24xx_reset_risc()
3301 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3302 	    rd_reg_dword(&reg->ctrl_status),  in qla24xx_reset_risc()
3303 	    (rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE));  in qla24xx_reset_risc()
3327 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3331 	rd_reg_dword(&reg->ctrl_status);  in qla24xx_reset_risc()
3334 		if ((rd_reg_dword(&reg->ctrl_status) &  in qla24xx_reset_risc()
3340 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))  in qla24xx_reset_risc()
3345 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3346 	    rd_reg_dword(&reg->ctrl_status));  in qla24xx_reset_risc()
3366 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3369 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3373 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3397 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3418 	*data = rd_reg_dword(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET);  in qla25xx_read_risc_sema_reg()
7894 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()
7896 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()