Lines Matching refs:spi
239 int (*get_fifo_size)(struct stm32_spi *spi);
240 int (*get_bpw_mask)(struct stm32_spi *spi);
241 void (*disable)(struct stm32_spi *spi);
242 int (*config)(struct stm32_spi *spi);
243 void (*set_bpw)(struct stm32_spi *spi);
244 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
245 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
246 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
247 void (*transfer_one_dma_start)(struct stm32_spi *spi);
250 int (*transfer_one_irq)(struct stm32_spi *spi);
348 static inline void stm32_spi_set_bits(struct stm32_spi *spi, in stm32_spi_set_bits() argument
351 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
352 spi->base + offset); in stm32_spi_set_bits()
355 static inline void stm32_spi_clr_bits(struct stm32_spi *spi, in stm32_spi_clr_bits() argument
358 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
359 spi->base + offset); in stm32_spi_clr_bits()
366 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) in stm32h7_spi_get_fifo_size() argument
371 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
373 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
375 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
376 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
378 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
380 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
382 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
391 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) in stm32f4_spi_get_bpw_mask() argument
393 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
401 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) in stm32h7_spi_get_bpw_mask() argument
406 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
412 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); in stm32h7_spi_get_bpw_mask()
414 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
417 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
419 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
433 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, in stm32_spi_prepare_mbr() argument
439 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
457 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
459 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed); in stm32_spi_prepare_mbr()
469 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len) in stm32h7_spi_prepare_fthlv() argument
474 packet = clamp(xfer_len, 1U, spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
477 bpw = DIV_ROUND_UP(spi->cur_bpw, 8); in stm32h7_spi_prepare_fthlv()
488 static void stm32f4_spi_write_tx(struct stm32_spi *spi) in stm32f4_spi_write_tx() argument
490 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_write_tx()
492 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
494 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
495 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
497 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
498 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
500 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
502 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
503 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
507 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
517 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) in stm32h7_spi_write_txfifo() argument
519 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
520 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
522 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
524 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
525 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
527 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
528 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
529 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
530 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
532 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
533 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
535 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
537 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
538 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
542 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
552 static void stm32f4_spi_read_rx(struct stm32_spi *spi) in stm32f4_spi_read_rx() argument
554 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_read_rx()
556 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
558 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
559 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
561 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
562 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
564 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
566 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
567 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
571 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
581 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi) in stm32h7_spi_read_rxfifo() argument
583 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
586 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
590 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
592 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
594 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
596 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
597 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
598 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
600 (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
601 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
603 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
604 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
606 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
608 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
609 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
612 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
616 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32h7_spi_read_rxfifo()
617 __func__, spi->rx_len, sr); in stm32h7_spi_read_rxfifo()
624 static void stm32_spi_enable(struct stm32_spi *spi) in stm32_spi_enable() argument
626 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
628 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
629 spi->cfg->regs->en.mask); in stm32_spi_enable()
636 static void stm32f4_spi_disable(struct stm32_spi *spi) in stm32f4_spi_disable() argument
641 dev_dbg(spi->dev, "disable controller\n"); in stm32f4_spi_disable()
643 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_disable()
645 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & in stm32f4_spi_disable()
647 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
652 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE | in stm32f4_spi_disable()
657 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, in stm32f4_spi_disable()
660 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32f4_spi_disable()
663 if (spi->cur_usedma && spi->dma_tx) in stm32f4_spi_disable()
664 dmaengine_terminate_all(spi->dma_tx); in stm32f4_spi_disable()
665 if (spi->cur_usedma && spi->dma_rx) in stm32f4_spi_disable()
666 dmaengine_terminate_all(spi->dma_rx); in stm32f4_spi_disable()
668 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE); in stm32f4_spi_disable()
670 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN | in stm32f4_spi_disable()
674 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_disable()
675 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_disable()
677 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
686 static void stm32h7_spi_disable(struct stm32_spi *spi) in stm32h7_spi_disable() argument
691 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
693 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
695 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
698 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
703 if (spi->cur_half_period) in stm32h7_spi_disable()
704 udelay(spi->cur_half_period); in stm32h7_spi_disable()
706 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
707 dmaengine_terminate_all(spi->dma_tx); in stm32h7_spi_disable()
708 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
709 dmaengine_terminate_all(spi->dma_rx); in stm32h7_spi_disable()
711 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_disable()
713 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | in stm32h7_spi_disable()
717 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
718 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
720 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
737 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_can_dma() local
739 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
740 dma_size = spi->fifo_size; in stm32_spi_can_dma()
744 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
758 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32f4_spi_irq_event() local
762 spin_lock(&spi->lock); in stm32f4_spi_irq_event()
764 sr = readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
771 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32f4_spi_irq_event()
772 spi->cur_comm == SPI_3WIRE_TX)) { in stm32f4_spi_irq_event()
778 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_irq_event()
779 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_irq_event()
780 spi->cur_comm == SPI_3WIRE_RX)) { in stm32f4_spi_irq_event()
787 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32f4_spi_irq_event()
788 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
793 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32f4_spi_irq_event()
796 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_irq_event()
797 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
809 if (spi->tx_buf) in stm32f4_spi_irq_event()
810 stm32f4_spi_write_tx(spi); in stm32f4_spi_irq_event()
811 if (spi->tx_len == 0) in stm32f4_spi_irq_event()
816 stm32f4_spi_read_rx(spi); in stm32f4_spi_irq_event()
817 if (spi->rx_len == 0) in stm32f4_spi_irq_event()
819 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32f4_spi_irq_event()
820 stm32f4_spi_write_tx(spi); in stm32f4_spi_irq_event()
826 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, in stm32f4_spi_irq_event()
830 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
834 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
846 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32f4_spi_irq_thread() local
849 stm32f4_spi_disable(spi); in stm32f4_spi_irq_thread()
862 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32h7_spi_irq_thread() local
867 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
869 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
870 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
883 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma) in stm32h7_spi_irq_thread()
887 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
889 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
899 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
900 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
901 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
906 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
911 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
916 dev_err(spi->dev, "Overrun: RX data lost\n"); in stm32h7_spi_irq_thread()
921 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
922 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
923 if (!spi->cur_usedma || in stm32h7_spi_irq_thread()
924 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)) in stm32h7_spi_irq_thread()
929 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
930 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_irq_thread()
933 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
934 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
936 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
938 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
941 stm32h7_spi_disable(spi); in stm32h7_spi_irq_thread()
956 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_prepare_msg() local
957 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
963 spi->cur_midi = 0; in stm32_spi_prepare_msg()
964 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
965 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
968 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
970 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
973 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
975 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
978 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
980 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
982 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
992 if (spi->cfg->set_number_of_data) { in stm32_spi_prepare_msg()
1002 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
1007 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1009 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1011 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1024 struct stm32_spi *spi = data; in stm32f4_spi_dma_tx_cb() local
1026 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_dma_tx_cb()
1027 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_tx_cb()
1028 stm32f4_spi_disable(spi); in stm32f4_spi_dma_tx_cb()
1040 struct stm32_spi *spi = data; in stm32_spi_dma_rx_cb() local
1042 spi_finalize_current_transfer(spi->master); in stm32_spi_dma_rx_cb()
1043 spi->cfg->disable(spi); in stm32_spi_dma_rx_cb()
1053 static void stm32_spi_dma_config(struct stm32_spi *spi, in stm32_spi_dma_config() argument
1060 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1062 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1067 if (spi->cfg->has_fifo) { in stm32_spi_dma_config()
1069 if (spi->cur_fthlv == 2) in stm32_spi_dma_config()
1072 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1080 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1084 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1087 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1091 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1104 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) in stm32f4_spi_transfer_one_irq() argument
1110 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_transfer_one_irq()
1112 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_transfer_one_irq()
1113 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_transfer_one_irq()
1114 spi->cur_comm == SPI_3WIRE_RX) { in stm32f4_spi_transfer_one_irq()
1124 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1126 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2); in stm32f4_spi_transfer_one_irq()
1128 stm32_spi_enable(spi); in stm32f4_spi_transfer_one_irq()
1131 if (spi->tx_buf) in stm32f4_spi_transfer_one_irq()
1132 stm32f4_spi_write_tx(spi); in stm32f4_spi_transfer_one_irq()
1134 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1147 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) in stm32h7_spi_transfer_one_irq() argument
1153 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1155 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1157 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1164 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1166 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_irq()
1169 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1170 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_transfer_one_irq()
1172 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_irq()
1174 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1176 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1186 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32f4_spi_transfer_one_dma_start() argument
1189 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32f4_spi_transfer_one_dma_start()
1190 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_transfer_one_dma_start()
1196 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE); in stm32f4_spi_transfer_one_dma_start()
1199 stm32_spi_enable(spi); in stm32f4_spi_transfer_one_dma_start()
1207 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32h7_spi_transfer_one_dma_start() argument
1212 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) in stm32h7_spi_transfer_one_dma_start()
1215 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier); in stm32h7_spi_transfer_one_dma_start()
1217 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_dma_start()
1219 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_dma_start()
1230 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, in stm32_spi_transfer_one_dma() argument
1237 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1240 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1241 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); in stm32_spi_transfer_one_dma()
1242 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1245 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1246 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1249 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1256 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1257 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); in stm32_spi_transfer_one_dma()
1258 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1261 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1267 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1268 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1271 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1275 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1276 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1279 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1283 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1287 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1288 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1289 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1290 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1294 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1298 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1301 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1302 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1305 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1307 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1312 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1313 dmaengine_terminate_all(spi->dma_rx); in stm32_spi_transfer_one_dma()
1316 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1317 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1319 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1321 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1323 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1324 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1331 static void stm32f4_spi_set_bpw(struct stm32_spi *spi) in stm32f4_spi_set_bpw() argument
1333 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1334 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1336 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1343 static void stm32h7_spi_set_bpw(struct stm32_spi *spi) in stm32h7_spi_set_bpw() argument
1348 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1353 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1354 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1360 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1362 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1370 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) in stm32_spi_set_mbr() argument
1374 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1375 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1377 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1379 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1418 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32f4_spi_set_mode() argument
1421 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1426 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1430 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1432 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1446 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32h7_spi_set_mode() argument
1453 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1456 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1469 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1471 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1482 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) in stm32h7_spi_data_idleness() argument
1487 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1488 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed); in stm32h7_spi_data_idleness()
1490 DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1495 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1500 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1502 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1510 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) in stm32h7_spi_number_of_data() argument
1514 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1530 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, in stm32_spi_transfer_one_setup() argument
1539 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1541 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1543 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1544 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1547 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1548 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1549 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1555 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1556 stm32_spi_set_mbr(spi, mbr); in stm32_spi_transfer_one_setup()
1559 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1563 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1565 if (spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1566 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1568 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1570 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1575 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1576 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1581 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1582 spi->cur_comm); in stm32_spi_transfer_one_setup()
1583 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1585 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1586 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1587 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1588 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1589 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1590 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1593 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1611 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_transfer_one() local
1614 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1615 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1616 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1617 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1619 spi->cur_usedma = (master->can_dma && in stm32_spi_transfer_one()
1622 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); in stm32_spi_transfer_one()
1624 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1628 if (spi->cur_usedma) in stm32_spi_transfer_one()
1629 return stm32_spi_transfer_one_dma(spi, transfer); in stm32_spi_transfer_one()
1631 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1642 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_unprepare_msg() local
1644 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1653 static int stm32f4_spi_config(struct stm32_spi *spi) in stm32f4_spi_config() argument
1657 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_config()
1660 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR, in stm32f4_spi_config()
1670 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI | in stm32f4_spi_config()
1675 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_config()
1684 static int stm32h7_spi_config(struct stm32_spi *spi) in stm32h7_spi_config() argument
1688 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1691 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, in stm32h7_spi_config()
1699 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | in stm32h7_spi_config()
1709 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | in stm32h7_spi_config()
1713 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
1769 struct stm32_spi *spi; in stm32_spi_probe() local
1781 spi = spi_master_get_devdata(master); in stm32_spi_probe()
1782 spi->dev = &pdev->dev; in stm32_spi_probe()
1783 spi->master = master; in stm32_spi_probe()
1784 spin_lock_init(&spi->lock); in stm32_spi_probe()
1786 spi->cfg = (const struct stm32_spi_cfg *) in stm32_spi_probe()
1791 spi->base = devm_ioremap_resource(&pdev->dev, res); in stm32_spi_probe()
1792 if (IS_ERR(spi->base)) in stm32_spi_probe()
1793 return PTR_ERR(spi->base); in stm32_spi_probe()
1795 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
1797 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
1798 if (spi->irq <= 0) in stm32_spi_probe()
1799 return dev_err_probe(&pdev->dev, spi->irq, in stm32_spi_probe()
1802 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
1803 spi->cfg->irq_handler_event, in stm32_spi_probe()
1804 spi->cfg->irq_handler_thread, in stm32_spi_probe()
1807 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
1812 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
1813 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
1814 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
1819 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
1824 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
1825 if (!spi->clk_rate) { in stm32_spi_probe()
1844 if (spi->cfg->has_fifo) in stm32_spi_probe()
1845 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
1847 ret = spi->cfg->config(spi); in stm32_spi_probe()
1859 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
1860 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
1861 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
1868 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
1869 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
1870 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
1871 spi->dma_tx = NULL; in stm32_spi_probe()
1877 master->dma_tx = spi->dma_tx; in stm32_spi_probe()
1880 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
1881 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
1882 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
1883 spi->dma_rx = NULL; in stm32_spi_probe()
1889 master->dma_rx = spi->dma_rx; in stm32_spi_probe()
1892 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
1922 if (spi->dma_tx) in stm32_spi_probe()
1923 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
1924 if (spi->dma_rx) in stm32_spi_probe()
1925 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
1927 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
1935 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_remove() local
1940 spi->cfg->disable(spi); in stm32_spi_remove()
1952 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
1963 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_suspend() local
1965 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
1973 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_resume() local
1980 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
1998 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_resume() local
2007 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2018 spi->cfg->config(spi); in stm32_spi_resume()